assembler-mips.cc 126 KB
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

// The original source code covered by the above license above has been
// modified significantly by Google Inc.
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// Copyright 2012 the V8 project authors. All rights reserved.
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#include "src/mips/assembler-mips.h"

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#if V8_TARGET_ARCH_MIPS
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#include "src/base/bits.h"
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#include "src/base/cpu.h"
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#include "src/deoptimizer.h"
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#include "src/mips/assembler-mips-inl.h"
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#include "src/objects/heap-number-inl.h"
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#include "src/string-constants.h"
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namespace v8 {
namespace internal {

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// Get the CPU features enabled by the build. For cross compilation the
// preprocessor symbols CAN_USE_FPU_INSTRUCTIONS
// can be defined to enable FPU instructions when building the
// snapshot.
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static unsigned CpuFeaturesImpliedByCompiler() {
  unsigned answer = 0;
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#ifdef CAN_USE_FPU_INSTRUCTIONS
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  answer |= 1u << FPU;
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#endif  // def CAN_USE_FPU_INSTRUCTIONS

  // If the compiler is allowed to use FPU then we can use FPU too in our code
  // generation even when generating snapshots.  This won't work for cross
  // compilation.
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#if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0
  answer |= 1u << FPU;
#endif
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  return answer;
}


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void CpuFeatures::ProbeImpl(bool cross_compile) {
  supported_ |= CpuFeaturesImpliedByCompiler();
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  // Only use statically determined features for cross compile (snapshot).
  if (cross_compile) return;
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  // If the compiler is allowed to use fpu then we can use fpu too in our
  // code generation.
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#ifndef __mips__
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  // For the simulator build, use FPU.
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  supported_ |= 1u << FPU;
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#if defined(_MIPS_ARCH_MIPS32R6)
  // FP64 mode is implied on r6.
  supported_ |= 1u << FP64FPU;
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#if defined(_MIPS_MSA)
  supported_ |= 1u << MIPS_SIMD;
#endif
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#endif
#if defined(FPU_MODE_FP64)
  supported_ |= 1u << FP64FPU;
#endif
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#else
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  // Probe for additional features at runtime.
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  base::CPU cpu;
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  if (cpu.has_fpu()) supported_ |= 1u << FPU;
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#if defined(FPU_MODE_FPXX)
  if (cpu.is_fp64_mode()) supported_ |= 1u << FP64FPU;
#elif defined(FPU_MODE_FP64)
  supported_ |= 1u << FP64FPU;
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#if defined(_MIPS_ARCH_MIPS32R6)
#if defined(_MIPS_MSA)
  supported_ |= 1u << MIPS_SIMD;
#else
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  if (cpu.has_msa()) supported_ |= 1u << MIPS_SIMD;
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#endif
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#endif
#endif
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#if defined(_MIPS_ARCH_MIPS32RX)
  if (cpu.architecture() == 6) {
    supported_ |= 1u << MIPSr6;
  } else if (cpu.architecture() == 2) {
    supported_ |= 1u << MIPSr1;
    supported_ |= 1u << MIPSr2;
  } else {
    supported_ |= 1u << MIPSr1;
  }
#endif
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#endif
}
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void CpuFeatures::PrintTarget() { }
void CpuFeatures::PrintFeatures() { }


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int ToNumber(Register reg) {
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  DCHECK(reg.is_valid());
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  const int kNumbers[] = {
    0,    // zero_reg
    1,    // at
    2,    // v0
    3,    // v1
    4,    // a0
    5,    // a1
    6,    // a2
    7,    // a3
    8,    // t0
    9,    // t1
    10,   // t2
    11,   // t3
    12,   // t4
    13,   // t5
    14,   // t6
    15,   // t7
    16,   // s0
    17,   // s1
    18,   // s2
    19,   // s3
    20,   // s4
    21,   // s5
    22,   // s6
    23,   // s7
    24,   // t8
    25,   // t9
    26,   // k0
    27,   // k1
    28,   // gp
    29,   // sp
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    30,   // fp
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    31,   // ra
  };
  return kNumbers[reg.code()];
}

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Register ToRegister(int num) {
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  DCHECK(num >= 0 && num < kNumRegisters);
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  const Register kRegisters[] = {
    zero_reg,
    at,
    v0, v1,
    a0, a1, a2, a3,
    t0, t1, t2, t3, t4, t5, t6, t7,
    s0, s1, s2, s3, s4, s5, s6, s7,
    t8, t9,
    k0, k1,
    gp,
    sp,
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    fp,
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    ra
  };
  return kRegisters[num];
}


// -----------------------------------------------------------------------------
// Implementation of RelocInfo.

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const int RelocInfo::kApplyMask =
    RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE) |
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    RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE_ENCODED) |
    RelocInfo::ModeMask(RelocInfo::RELATIVE_CODE_TARGET);
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bool RelocInfo::IsCodedSpecially() {
  // The deserializer needs to know whether a pointer is specially coded.  Being
  // specially coded on MIPS means that it is a lui/ori instruction, and that is
  // always the case inside code objects.
  return true;
}


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bool RelocInfo::IsInConstantPool() {
  return false;
}

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uint32_t RelocInfo::wasm_call_tag() const {
  DCHECK(rmode_ == WASM_CALL || rmode_ == WASM_STUB_CALL);
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  return static_cast<uint32_t>(
      Assembler::target_address_at(pc_, constant_pool_));
}

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// -----------------------------------------------------------------------------
// Implementation of Operand and MemOperand.
// See assembler-mips-inl.h for inlined constructors.

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Operand::Operand(Handle<HeapObject> handle)
    : rm_(no_reg), rmode_(RelocInfo::EMBEDDED_OBJECT) {
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  value_.immediate = static_cast<intptr_t>(handle.address());
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}

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Operand Operand::EmbeddedNumber(double value) {
  int32_t smi;
  if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
  Operand result(0, RelocInfo::EMBEDDED_OBJECT);
  result.is_heap_object_request_ = true;
  result.value_.heap_object_request = HeapObjectRequest(value);
  return result;
}

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Operand Operand::EmbeddedStringConstant(const StringConstantBase* str) {
  Operand result(0, RelocInfo::EMBEDDED_OBJECT);
  result.is_heap_object_request_ = true;
  result.value_.heap_object_request = HeapObjectRequest(str);
  return result;
}

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MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) {
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  offset_ = offset;
}


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MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier,
                       OffsetAddend offset_addend) : Operand(rm) {
  offset_ = unit * multiplier + offset_addend;
}

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void Assembler::AllocateAndInstallRequestedHeapObjects(Isolate* isolate) {
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  DCHECK_IMPLIES(isolate == nullptr, heap_object_requests_.empty());
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  for (auto& request : heap_object_requests_) {
    Handle<HeapObject> object;
    switch (request.kind()) {
      case HeapObjectRequest::kHeapNumber:
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        object =
            isolate->factory()->NewHeapNumber(request.heap_number(), TENURED);
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        break;
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      case HeapObjectRequest::kStringConstant:
        const StringConstantBase* str = request.string();
        CHECK_NOT_NULL(str);
        object = str->AllocateStringConstant(isolate);
        break;
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    }
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    Address pc = reinterpret_cast<Address>(buffer_start_) + request.offset();
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    set_target_value_at(pc, reinterpret_cast<uint32_t>(object.location()));
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  }
}
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// -----------------------------------------------------------------------------
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// Specific instructions, constants, and masks.

static const int kNegOffset = 0x00008000;
// addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
// operations as post-increment of sp.
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const Instr kPopInstruction = ADDIU | (sp.code() << kRsShift) |
                              (sp.code() << kRtShift) |
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                              (kPointerSize & kImm16Mask);  // NOLINT
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// addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
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const Instr kPushInstruction = ADDIU | (sp.code() << kRsShift) |
                               (sp.code() << kRtShift) |
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                               (-kPointerSize & kImm16Mask);  // NOLINT
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// sw(r, MemOperand(sp, 0))
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const Instr kPushRegPattern =
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    SW | (sp.code() << kRsShift) | (0 & kImm16Mask);  // NOLINT
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//  lw(r, MemOperand(sp, 0))
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const Instr kPopRegPattern =
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    LW | (sp.code() << kRsShift) | (0 & kImm16Mask);  // NOLINT
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const Instr kLwRegFpOffsetPattern =
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    LW | (fp.code() << kRsShift) | (0 & kImm16Mask);  // NOLINT
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const Instr kSwRegFpOffsetPattern =
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    SW | (fp.code() << kRsShift) | (0 & kImm16Mask);  // NOLINT
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const Instr kLwRegFpNegOffsetPattern =
    LW | (fp.code() << kRsShift) | (kNegOffset & kImm16Mask);  // NOLINT
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const Instr kSwRegFpNegOffsetPattern =
    SW | (fp.code() << kRsShift) | (kNegOffset & kImm16Mask);  // NOLINT
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// A mask for the Rt register for push, pop, lw, sw instructions.
const Instr kRtMask = kRtFieldMask;
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const Instr kLwSwInstrTypeMask = 0xFFE00000;
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const Instr kLwSwInstrArgumentMask  = ~kLwSwInstrTypeMask;
const Instr kLwSwOffsetMask = kImm16Mask;

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Assembler::Assembler(const AssemblerOptions& options,
                     std::unique_ptr<AssemblerBuffer> buffer)
    : AssemblerBase(options, std::move(buffer)),
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      scratch_register_list_(at.bit()) {
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  reloc_info_writer.Reposition(buffer_start_ + buffer_->size(), pc_);
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  last_trampoline_pool_end_ = 0;
  no_trampoline_pool_before_ = 0;
  trampoline_pool_blocked_nesting_ = 0;
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  // We leave space (16 * kTrampolineSlotsSize)
  // for BlockTrampolinePoolScope buffer.
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  next_buffer_check_ = FLAG_force_long_branches
      ? kMaxInt : kMaxBranchOffset - kTrampolineSlotsSize * 16;
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  internal_trampoline_exception_ = false;
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  last_bound_pos_ = 0;
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  trampoline_emitted_ = FLAG_force_long_branches;
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  unbound_labels_count_ = 0;
  block_buffer_growth_ = false;
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}

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void Assembler::GetCode(Isolate* isolate, CodeDesc* desc,
                        SafepointTableBuilder* safepoint_table_builder,
                        int handler_table_offset) {
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  EmitForbiddenSlotInstruction();
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  int code_comments_size = WriteCodeComments();

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  DCHECK(pc_ <= reloc_info_writer.pos());  // No overlap.
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  AllocateAndInstallRequestedHeapObjects(isolate);

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  // Set up code descriptor.
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  // TODO(jgruber): Reconsider how these offsets and sizes are maintained up to
  // this point to make CodeDesc initialization less fiddly.

  static constexpr int kConstantPoolSize = 0;
  const int instruction_size = pc_offset();
  const int code_comments_offset = instruction_size - code_comments_size;
  const int constant_pool_offset = code_comments_offset - kConstantPoolSize;
  const int handler_table_offset2 = (handler_table_offset == kNoHandlerTable)
                                        ? constant_pool_offset
                                        : handler_table_offset;
  const int safepoint_table_offset =
      (safepoint_table_builder == kNoSafepointTable)
          ? handler_table_offset2
          : safepoint_table_builder->GetCodeOffset();
  const int reloc_info_offset =
      static_cast<int>(reloc_info_writer.pos() - buffer_->start());
  CodeDesc::Initialize(desc, this, safepoint_table_offset,
                       handler_table_offset2, constant_pool_offset,
                       code_comments_offset, reloc_info_offset);
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}

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void Assembler::Align(int m) {
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  DCHECK(m >= 4 && base::bits::IsPowerOfTwo(m));
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  EmitForbiddenSlotInstruction();
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  while ((pc_offset() & (m - 1)) != 0) {
    nop();
  }
}


void Assembler::CodeTargetAlign() {
  // No advantage to aligning branch/call targets to more than
  // single instruction, that I am aware of.
  Align(4);
}


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Register Assembler::GetRtReg(Instr instr) {
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  return Register::from_code((instr & kRtFieldMask) >> kRtShift);
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}


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Register Assembler::GetRsReg(Instr instr) {
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  return Register::from_code((instr & kRsFieldMask) >> kRsShift);
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}


Register Assembler::GetRdReg(Instr instr) {
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  return Register::from_code((instr & kRdFieldMask) >> kRdShift);
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}


uint32_t Assembler::GetRt(Instr instr) {
  return (instr & kRtFieldMask) >> kRtShift;
}


uint32_t Assembler::GetRtField(Instr instr) {
  return instr & kRtFieldMask;
}


uint32_t Assembler::GetRs(Instr instr) {
  return (instr & kRsFieldMask) >> kRsShift;
}


uint32_t Assembler::GetRsField(Instr instr) {
  return instr & kRsFieldMask;
}


uint32_t Assembler::GetRd(Instr instr) {
  return  (instr & kRdFieldMask) >> kRdShift;
}


uint32_t Assembler::GetRdField(Instr instr) {
  return  instr & kRdFieldMask;
}


uint32_t Assembler::GetSa(Instr instr) {
  return (instr & kSaFieldMask) >> kSaShift;
}


uint32_t Assembler::GetSaField(Instr instr) {
  return instr & kSaFieldMask;
}


uint32_t Assembler::GetOpcodeField(Instr instr) {
  return instr & kOpcodeMask;
}


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uint32_t Assembler::GetFunction(Instr instr) {
  return (instr & kFunctionFieldMask) >> kFunctionShift;
}


uint32_t Assembler::GetFunctionField(Instr instr) {
  return instr & kFunctionFieldMask;
}


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uint32_t Assembler::GetImmediate16(Instr instr) {
  return instr & kImm16Mask;
}


uint32_t Assembler::GetLabelConst(Instr instr) {
  return instr & ~kImm16Mask;
}


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bool Assembler::IsPop(Instr instr) {
  return (instr & ~kRtMask) == kPopRegPattern;
}


bool Assembler::IsPush(Instr instr) {
  return (instr & ~kRtMask) == kPushRegPattern;
}


bool Assembler::IsSwRegFpOffset(Instr instr) {
  return ((instr & kLwSwInstrTypeMask) == kSwRegFpOffsetPattern);
}


bool Assembler::IsLwRegFpOffset(Instr instr) {
  return ((instr & kLwSwInstrTypeMask) == kLwRegFpOffsetPattern);
}


bool Assembler::IsSwRegFpNegOffset(Instr instr) {
  return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
          kSwRegFpNegOffsetPattern);
}


bool Assembler::IsLwRegFpNegOffset(Instr instr) {
  return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
          kLwRegFpNegOffsetPattern);
}


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// Labels refer to positions in the (to be) generated code.
// There are bound, linked, and unused labels.
//
// Bound labels refer to known positions in the already
// generated code. pos() is the position the label refers to.
//
// Linked labels refer to unknown positions in the code
// to be generated; pos() is the position of the last
// instruction using the label.

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// The link chain is terminated by a value in the instruction of -1,
// which is an otherwise illegal value (branch -1 is inf loop).
// The instruction 16-bit offset field addresses 32-bit words, but in
// code is conv to an 18-bit value addressing bytes, hence the -4 value.
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const int kEndOfChain = -4;
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// Determines the end of the Jump chain (a subset of the label link chain).
const int kEndOfJumpChain = 0;
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bool Assembler::IsMsaBranch(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rs_field = GetRsField(instr);
  if (opcode == COP1) {
    switch (rs_field) {
      case BZ_V:
      case BZ_B:
      case BZ_H:
      case BZ_W:
      case BZ_D:
      case BNZ_V:
      case BNZ_B:
      case BNZ_H:
      case BNZ_W:
      case BNZ_D:
        return true;
      default:
        return false;
    }
  } else {
    return false;
  }
}
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bool Assembler::IsBranch(Instr instr) {
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  uint32_t opcode   = GetOpcodeField(instr);
  uint32_t rt_field = GetRtField(instr);
  uint32_t rs_field = GetRsField(instr);
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  // Checks if the instruction is a branch.
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  bool isBranch =
      opcode == BEQ || opcode == BNE || opcode == BLEZ || opcode == BGTZ ||
      opcode == BEQL || opcode == BNEL || opcode == BLEZL || opcode == BGTZL ||
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      (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
                            rt_field == BLTZAL || rt_field == BGEZAL)) ||
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      (opcode == COP1 && rs_field == BC1) ||  // Coprocessor branch.
      (opcode == COP1 && rs_field == BC1EQZ) ||
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      (opcode == COP1 && rs_field == BC1NEZ) || IsMsaBranch(instr);
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  if (!isBranch && IsMipsArchVariant(kMips32r6)) {
    // All the 3 variants of POP10 (BOVC, BEQC, BEQZALC) and
    // POP30 (BNVC, BNEC, BNEZALC) are branch ops.
    isBranch |= opcode == POP10 || opcode == POP30 || opcode == BC ||
                opcode == BALC ||
                (opcode == POP66 && rs_field != 0) ||  // BEQZC
                (opcode == POP76 && rs_field != 0);    // BNEZC
  }
  return isBranch;
}


bool Assembler::IsBc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a BC or BALC.
  return opcode == BC || opcode == BALC;
}

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bool Assembler::IsNal(Instr instr) {
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  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rt_field = GetRtField(instr);
  uint32_t rs_field = GetRsField(instr);
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  return opcode == REGIMM && rt_field == BLTZAL && rs_field == 0;
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}
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bool Assembler::IsBzc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is BEQZC or BNEZC.
  return (opcode == POP66 && GetRsField(instr) != 0) ||
         (opcode == POP76 && GetRsField(instr) != 0);
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}

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bool Assembler::IsEmittedConstant(Instr instr) {
  uint32_t label_constant = GetLabelConst(instr);
  return label_constant == 0;  // Emitted label const in reg-exp engine.
}
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bool Assembler::IsBeq(Instr instr) {
  return GetOpcodeField(instr) == BEQ;
}


bool Assembler::IsBne(Instr instr) {
  return GetOpcodeField(instr) == BNE;
}


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bool Assembler::IsBeqzc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  return opcode == POP66 && GetRsField(instr) != 0;
}


bool Assembler::IsBnezc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  return opcode == POP76 && GetRsField(instr) != 0;
}


bool Assembler::IsBeqc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rs = GetRsField(instr);
  uint32_t rt = GetRtField(instr);
  return opcode == POP10 && rs != 0 && rs < rt;  // && rt != 0
}


bool Assembler::IsBnec(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rs = GetRsField(instr);
  uint32_t rt = GetRtField(instr);
  return opcode == POP30 && rs != 0 && rs < rt;  // && rt != 0
}

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bool Assembler::IsJicOrJialc(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rs = GetRsField(instr);
  return (opcode == POP66 || opcode == POP76) && rs == 0;
}
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bool Assembler::IsJump(Instr instr) {
  uint32_t opcode   = GetOpcodeField(instr);
  uint32_t rt_field = GetRtField(instr);
  uint32_t rd_field = GetRdField(instr);
  uint32_t function_field = GetFunctionField(instr);
  // Checks if the instruction is a jump.
  return opcode == J || opcode == JAL ||
      (opcode == SPECIAL && rt_field == 0 &&
      ((function_field == JALR) || (rd_field == 0 && (function_field == JR))));
}

bool Assembler::IsJ(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a jump.
  return opcode == J;
}


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bool Assembler::IsJal(Instr instr) {
  return GetOpcodeField(instr) == JAL;
}

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bool Assembler::IsJr(Instr instr) {
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  if (!IsMipsArchVariant(kMips32r6))  {
    return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR;
  } else {
    return GetOpcodeField(instr) == SPECIAL &&
        GetRdField(instr) == 0  && GetFunctionField(instr) == JALR;
  }
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}

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bool Assembler::IsJalr(Instr instr) {
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  return GetOpcodeField(instr) == SPECIAL &&
         GetRdField(instr) != 0  && GetFunctionField(instr) == JALR;
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}


662 663 664 665 666 667 668 669 670 671 672 673 674
bool Assembler::IsLui(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a load upper immediate.
  return opcode == LUI;
}


bool Assembler::IsOri(Instr instr) {
  uint32_t opcode = GetOpcodeField(instr);
  // Checks if the instruction is a load upper immediate.
  return opcode == ORI;
}

675 676 677 678 679 680 681 682 683 684 685 686 687 688
bool Assembler::IsAddu(Instr instr, Register rd, Register rs, Register rt) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rd_field = GetRd(instr);
  uint32_t rs_field = GetRs(instr);
  uint32_t rt_field = GetRt(instr);
  uint32_t sa_field = GetSaField(instr);
  uint32_t rd_reg = static_cast<uint32_t>(rd.code());
  uint32_t rs_reg = static_cast<uint32_t>(rs.code());
  uint32_t rt_reg = static_cast<uint32_t>(rt.code());
  uint32_t function_field = GetFunction(instr);
  return opcode == SPECIAL && sa_field == 0 && function_field == ADDU &&
         rd_reg == rd_field && rs_reg == rs_field && rt_reg == rt_field;
}

689 690 691 692 693 694 695 696 697 698 699 700 701
bool Assembler::IsMov(Instr instr, Register rd, Register rs) {
  uint32_t opcode = GetOpcodeField(instr);
  uint32_t rd_field = GetRd(instr);
  uint32_t rs_field = GetRs(instr);
  uint32_t rt_field = GetRt(instr);
  uint32_t rd_reg = static_cast<uint32_t>(rd.code());
  uint32_t rs_reg = static_cast<uint32_t>(rs.code());
  uint32_t function_field = GetFunctionField(instr);
  // Checks if the instruction is a OR with zero_reg argument (aka MOV).
  bool res = opcode == SPECIAL && function_field == OR && rd_field == rd_reg &&
             rs_field == rs_reg && rt_field == 0;
  return res;
}
702

703 704
bool Assembler::IsNop(Instr instr, unsigned int type) {
  // See Assembler::nop(type).
705
  DCHECK_LT(type, 32);
706
  uint32_t opcode = GetOpcodeField(instr);
707
  uint32_t function = GetFunctionField(instr);
708
  uint32_t rt = GetRt(instr);
709
  uint32_t rd = GetRd(instr);
710
  uint32_t sa = GetSa(instr);
711

712 713 714 715
  // Traditional mips nop == sll(zero_reg, zero_reg, 0)
  // When marking non-zero type, use sll(zero_reg, at, type)
  // to avoid use of mips ssnop and ehb special encodings
  // of the sll instruction.
716

717 718 719 720
  Register nop_rt_reg = (type == 0) ? zero_reg : at;
  bool ret = (opcode == SPECIAL && function == SLL &&
              rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
              rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) &&
721 722 723 724 725 726 727
              sa == type);

  return ret;
}


int32_t Assembler::GetBranchOffset(Instr instr) {
728
  DCHECK(IsBranch(instr));
729
  return (static_cast<int16_t>(instr & kImm16Mask)) << 2;
730 731 732 733
}


bool Assembler::IsLw(Instr instr) {
734
  return (static_cast<uint32_t>(instr & kOpcodeMask) == LW);
735 736 737 738
}


int16_t Assembler::GetLwOffset(Instr instr) {
739
  DCHECK(IsLw(instr));
740 741 742 743 744
  return ((instr & kImm16Mask));
}


Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {
745
  DCHECK(IsLw(instr));
746 747 748 749 750 751 752 753 754 755

  // We actually create a new lw instruction based on the original one.
  Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
      | (offset & kImm16Mask);

  return temp_instr;
}


bool Assembler::IsSw(Instr instr) {
756
  return (static_cast<uint32_t>(instr & kOpcodeMask) == SW);
757 758 759 760
}


Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {
761
  DCHECK(IsSw(instr));
762 763 764 765 766 767 768 769 770 771
  return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
}


bool Assembler::IsAddImmediate(Instr instr) {
  return ((instr & kOpcodeMask) == ADDIU);
}


Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {
772
  DCHECK(IsAddImmediate(instr));
773
  return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
774 775 776
}


777 778 779 780 781
bool Assembler::IsAndImmediate(Instr instr) {
  return GetOpcodeField(instr) == ANDI;
}


782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810
static Assembler::OffsetSize OffsetSizeInBits(Instr instr) {
  if (IsMipsArchVariant(kMips32r6)) {
    if (Assembler::IsBc(instr)) {
      return Assembler::OffsetSize::kOffset26;
    } else if (Assembler::IsBzc(instr)) {
      return Assembler::OffsetSize::kOffset21;
    }
  }
  return Assembler::OffsetSize::kOffset16;
}


static inline int32_t AddBranchOffset(int pos, Instr instr) {
  int bits = OffsetSizeInBits(instr);
  const int32_t mask = (1 << bits) - 1;
  bits = 32 - bits;

  // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming
  // the compiler uses arithmetic shifts for signed integers.
  int32_t imm = ((instr & mask) << bits) >> (bits - 2);

  if (imm == kEndOfChain) {
    // EndOfChain sentinel is returned directly, not relative to pc or pos.
    return kEndOfChain;
  } else {
    return pos + Assembler::kBranchPCOffset + imm;
  }
}

811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827
uint32_t Assembler::CreateTargetAddress(Instr instr_lui, Instr instr_jic) {
  DCHECK(IsLui(instr_lui) && IsJicOrJialc(instr_jic));
  int16_t jic_offset = GetImmediate16(instr_jic);
  int16_t lui_offset = GetImmediate16(instr_lui);

  if (jic_offset < 0) {
    lui_offset += kImm16Mask;
  }
  uint32_t lui_offset_u = (static_cast<uint32_t>(lui_offset)) << kLuiShift;
  uint32_t jic_offset_u = static_cast<uint32_t>(jic_offset) & kImm16Mask;

  return lui_offset_u | jic_offset_u;
}

// Use just lui and jic instructions. Insert lower part of the target address in
// jic offset part. Since jic sign-extends offset and then add it with register,
// before that addition, difference between upper part of the target address and
828
// upper part of the sign-extended offset (0xFFFF or 0x0000), will be inserted
829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851
// in jic register with lui instruction.
void Assembler::UnpackTargetAddress(uint32_t address, int16_t& lui_offset,
                                    int16_t& jic_offset) {
  lui_offset = (address & kHiMask) >> kLuiShift;
  jic_offset = address & kLoMask;

  if (jic_offset < 0) {
    lui_offset -= kImm16Mask;
  }
}

void Assembler::UnpackTargetAddressUnsigned(uint32_t address,
                                            uint32_t& lui_offset,
                                            uint32_t& jic_offset) {
  int16_t lui_offset16 = (address & kHiMask) >> kLuiShift;
  int16_t jic_offset16 = address & kLoMask;

  if (jic_offset16 < 0) {
    lui_offset16 -= kImm16Mask;
  }
  lui_offset = static_cast<uint32_t>(lui_offset16) & kImm16Mask;
  jic_offset = static_cast<uint32_t>(jic_offset16) & kImm16Mask;
}
852

853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881
void Assembler::PatchLuiOriImmediate(int pc, int32_t imm, Instr instr_lui,
                                     Address offset_lui, Instr instr_ori,
                                     Address offset_ori) {
  DCHECK(IsLui(instr_lui));
  DCHECK(IsOri(instr_ori));
  instr_at_put(static_cast<int>(pc + offset_lui),
               instr_lui | ((imm >> kLuiShift) & kImm16Mask));
  instr_at_put(static_cast<int>(pc + offset_ori),
               instr_ori | (imm & kImm16Mask));
}

void Assembler::PatchLuiOriImmediate(Address pc, int32_t imm, Instr instr_lui,
                                     Address offset_lui, Instr instr_ori,
                                     Address offset_ori) {
  DCHECK(IsLui(instr_lui));
  DCHECK(IsOri(instr_ori));
  instr_at_put(pc + offset_lui, instr_lui | ((imm >> kLuiShift) & kImm16Mask));
  instr_at_put(pc + offset_ori, instr_ori | (imm & kImm16Mask));
}

int32_t Assembler::GetLuiOriImmediate(Instr instr_lui, Instr instr_ori) {
  DCHECK(IsLui(instr_lui));
  DCHECK(IsOri(instr_ori));
  int32_t imm;
  imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift;
  imm |= (instr_ori & static_cast<int32_t>(kImm16Mask));
  return imm;
}

882
int Assembler::target_at(int pos, bool is_internal) {
883
  Instr instr = instr_at(pos);
884 885 886 887
  if (is_internal) {
    if (instr == 0) {
      return kEndOfChain;
    } else {
888
      int32_t instr_address = reinterpret_cast<int32_t>(buffer_start_ + pos);
889
      int delta = static_cast<int>(instr_address - instr);
890 891 892 893
      DCHECK(pos > delta);
      return pos - delta;
    }
  }
894 895
  if ((instr & ~kImm16Mask) == 0) {
    // Emitted label constant, not part of a branch.
896 897 898 899 900 901
    if (instr == 0) {
       return kEndOfChain;
     } else {
       int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
       return (imm18 + pos);
     }
902
  }
903
  // Check we have a branch or jump instruction.
904
  DCHECK(IsBranch(instr) || IsLui(instr) || IsMov(instr, t8, ra));
905
  if (IsBranch(instr)) {
906
    return AddBranchOffset(pos, instr);
907 908
  } else if (IsMov(instr, t8, ra)) {
    int32_t imm32;
909 910
    Instr instr_lui = instr_at(pos + 2 * kInstrSize);
    Instr instr_ori = instr_at(pos + 3 * kInstrSize);
911
    imm32 = GetLuiOriImmediate(instr_lui, instr_ori);
912
    if (imm32 == kEndOfJumpChain) {
913 914
      // EndOfChain sentinel is returned directly, not relative to pc or pos.
      return kEndOfChain;
915 916 917 918
    }
    return pos + Assembler::kLongBranchPCOffset + imm32;
  } else {
    DCHECK(IsLui(instr));
919
    if (IsNal(instr_at(pos + kInstrSize))) {
920
      int32_t imm32;
921 922
      Instr instr_lui = instr_at(pos + 0 * kInstrSize);
      Instr instr_ori = instr_at(pos + 2 * kInstrSize);
923
      imm32 = GetLuiOriImmediate(instr_lui, instr_ori);
924 925 926 927 928
      if (imm32 == kEndOfJumpChain) {
        // EndOfChain sentinel is returned directly, not relative to pc or pos.
        return kEndOfChain;
      }
      return pos + Assembler::kLongBranchPCOffset + imm32;
929
    } else {
930 931
      Instr instr1 = instr_at(pos + 0 * kInstrSize);
      Instr instr2 = instr_at(pos + 1 * kInstrSize);
932 933 934 935 936
      DCHECK(IsOri(instr2) || IsJicOrJialc(instr2));
      int32_t imm;
      if (IsJicOrJialc(instr2)) {
        imm = CreateTargetAddress(instr1, instr2);
      } else {
937
        imm = GetLuiOriImmediate(instr1, instr2);
938 939 940 941 942 943
      }

      if (imm == kEndOfJumpChain) {
        // EndOfChain sentinel is returned directly, not relative to pc or pos.
        return kEndOfChain;
      } else {
944
        uint32_t instr_address = reinterpret_cast<int32_t>(buffer_start_ + pos);
945 946 947 948
        int32_t delta = instr_address - imm;
        DCHECK(pos > delta);
        return pos - delta;
      }
949
    }
950
  }
951 952 953 954 955 956 957 958
  return 0;
}


static inline Instr SetBranchOffset(int32_t pos, int32_t target_pos,
                                    Instr instr) {
  int32_t bits = OffsetSizeInBits(instr);
  int32_t imm = target_pos - (pos + Assembler::kBranchPCOffset);
959
  DCHECK_EQ(imm & 3, 0);
960 961 962 963 964 965 966
  imm >>= 2;

  const int32_t mask = (1 << bits) - 1;
  instr &= ~mask;
  DCHECK(is_intn(imm, bits));

  return instr | (imm & mask);
967 968 969
}


970 971
void Assembler::target_at_put(int32_t pos, int32_t target_pos,
                              bool is_internal) {
972
  Instr instr = instr_at(pos);
973 974

  if (is_internal) {
975
    uint32_t imm = reinterpret_cast<uint32_t>(buffer_start_) + target_pos;
976 977 978
    instr_at_put(pos, imm);
    return;
  }
979
  if ((instr & ~kImm16Mask) == 0) {
980
    DCHECK(target_pos == kEndOfChain || target_pos >= 0);
981
    // Emitted label constant, not part of a branch.
982
    // Make label relative to Code pointer of generated Code object.
983 984 985 986
    instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
    return;
  }

987
  DCHECK(IsBranch(instr) || IsLui(instr) || IsMov(instr, t8, ra));
988
  if (IsBranch(instr)) {
989 990
    instr = SetBranchOffset(pos, target_pos, instr);
    instr_at_put(pos, instr);
991
  } else if (IsMov(instr, t8, ra)) {
992 993
    Instr instr_lui = instr_at(pos + 2 * kInstrSize);
    Instr instr_ori = instr_at(pos + 3 * kInstrSize);
994 995 996 997 998 999 1000 1001 1002 1003 1004
    DCHECK(IsLui(instr_lui));
    DCHECK(IsOri(instr_ori));

    int32_t imm_short = target_pos - (pos + Assembler::kBranchPCOffset);

    if (is_int16(imm_short)) {
      // Optimize by converting to regular branch with 16-bit
      // offset
      Instr instr_b = BEQ;
      instr_b = SetBranchOffset(pos, target_pos, instr_b);

1005 1006 1007 1008
      Instr instr_j = instr_at(pos + 5 * kInstrSize);
      Instr instr_branch_delay;

      if (IsJump(instr_j)) {
1009 1010
        // Case when branch delay slot is protected.
        instr_branch_delay = nopInstr;
1011
      } else {
1012
        // Case when branch delay slot is used.
1013 1014 1015 1016
        instr_branch_delay = instr_at(pos + 7 * kInstrSize);
      }
      instr_at_put(pos + 0 * kInstrSize, instr_b);
      instr_at_put(pos + 1 * kInstrSize, instr_branch_delay);
1017 1018 1019 1020 1021 1022 1023
    } else {
      int32_t imm = target_pos - (pos + Assembler::kLongBranchPCOffset);
      DCHECK_EQ(imm & 3, 0);

      instr_lui &= ~kImm16Mask;
      instr_ori &= ~kImm16Mask;

1024 1025
      PatchLuiOriImmediate(pos, imm, instr_lui, 2 * kInstrSize, instr_ori,
                           3 * kInstrSize);
1026
    }
1027
  } else {
1028
    DCHECK(IsLui(instr));
1029
    if (IsNal(instr_at(pos + kInstrSize))) {
1030 1031
      Instr instr_lui = instr_at(pos + 0 * kInstrSize);
      Instr instr_ori = instr_at(pos + 2 * kInstrSize);
1032 1033 1034 1035
      DCHECK(IsLui(instr_lui));
      DCHECK(IsOri(instr_ori));
      int32_t imm = target_pos - (pos + Assembler::kLongBranchPCOffset);
      DCHECK_EQ(imm & 3, 0);
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
      if (is_int16(imm + Assembler::kLongBranchPCOffset -
                   Assembler::kBranchPCOffset)) {
        // Optimize by converting to regular branch and link with 16-bit
        // offset.
        Instr instr_b = REGIMM | BGEZAL;  // Branch and link.
        instr_b = SetBranchOffset(pos, target_pos, instr_b);
        // Correct ra register to point to one instruction after jalr from
        // TurboAssembler::BranchAndLinkLong.
        Instr instr_a = ADDIU | ra.code() << kRsShift | ra.code() << kRtShift |
                        kOptimizedBranchAndLinkLongReturnOffset;

        instr_at_put(pos, instr_b);
        instr_at_put(pos + 1 * kInstrSize, instr_a);
      } else {
        instr_lui &= ~kImm16Mask;
        instr_ori &= ~kImm16Mask;
1052 1053
        PatchLuiOriImmediate(pos, imm, instr_lui, 0 * kInstrSize, instr_ori,
                             2 * kInstrSize);
1054
      }
1055
    } else {
1056 1057
      Instr instr1 = instr_at(pos + 0 * kInstrSize);
      Instr instr2 = instr_at(pos + 1 * kInstrSize);
1058
      DCHECK(IsOri(instr2) || IsJicOrJialc(instr2));
1059
      uint32_t imm = reinterpret_cast<uint32_t>(buffer_start_) + target_pos;
1060 1061 1062 1063 1064 1065 1066 1067
      DCHECK_EQ(imm & 3, 0);
      DCHECK(IsLui(instr1) && (IsJicOrJialc(instr2) || IsOri(instr2)));
      instr1 &= ~kImm16Mask;
      instr2 &= ~kImm16Mask;

      if (IsJicOrJialc(instr2)) {
        uint32_t lui_offset_u, jic_offset_u;
        UnpackTargetAddressUnsigned(imm, lui_offset_u, jic_offset_u);
1068 1069
        instr_at_put(pos + 0 * kInstrSize, instr1 | lui_offset_u);
        instr_at_put(pos + 1 * kInstrSize, instr2 | jic_offset_u);
1070
      } else {
1071 1072
        PatchLuiOriImmediate(pos, imm, instr1, 0 * kInstrSize, instr2,
                             1 * kInstrSize);
1073
      }
1074
    }
1075
  }
1076 1077
}

1078
void Assembler::print(const Label* L) {
1079 1080 1081 1082 1083
  if (L->is_unused()) {
    PrintF("unused label\n");
  } else if (L->is_bound()) {
    PrintF("bound label to %d\n", L->pos());
  } else if (L->is_linked()) {
1084 1085
    Label l;
    l.link_to(L->pos());
1086 1087 1088 1089 1090 1091 1092 1093 1094
    PrintF("unbound label");
    while (l.is_linked()) {
      PrintF("@ %d ", l.pos());
      Instr instr = instr_at(l.pos());
      if ((instr & ~kImm16Mask) == 0) {
        PrintF("value\n");
      } else {
        PrintF("%d\n", instr);
      }
1095
      next(&l, is_internal_reference(&l));
1096 1097 1098 1099 1100 1101 1102 1103
    }
  } else {
    PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
  }
}


void Assembler::bind_to(Label* L, int pos) {
1104
  DCHECK(0 <= pos && pos <= pc_offset());  // Must have valid binding position.
1105
  int32_t trampoline_pos = kInvalidSlotPos;
1106
  bool is_internal = false;
1107 1108
  if (L->is_linked() && !trampoline_emitted_) {
    unbound_labels_count_--;
1109 1110 1111
    if (!is_internal_reference(L)) {
      next_buffer_check_ += kTrampolineSlotsSize;
    }
1112 1113
  }

1114 1115
  while (L->is_linked()) {
    int32_t fixup_pos = L->pos();
1116
    int32_t dist = pos - fixup_pos;
1117
    is_internal = is_internal_reference(L);
1118 1119
    next(L, is_internal);  // Call next before overwriting link with target at
                           // fixup_pos.
1120
    Instr instr = instr_at(fixup_pos);
1121 1122
    if (is_internal) {
      target_at_put(fixup_pos, pos, is_internal);
1123 1124
    } else {
      if (IsBranch(instr)) {
1125 1126
        int branch_offset = BranchOffset(instr);
        if (dist > branch_offset) {
1127 1128
          if (trampoline_pos == kInvalidSlotPos) {
            trampoline_pos = get_trampoline_entry(fixup_pos);
1129
            CHECK_NE(trampoline_pos, kInvalidSlotPos);
1130
          }
1131
          CHECK((trampoline_pos - fixup_pos) <= branch_offset);
1132 1133
          target_at_put(fixup_pos, trampoline_pos, false);
          fixup_pos = trampoline_pos;
1134
        }
1135 1136 1137
        target_at_put(fixup_pos, pos, false);
      } else {
        target_at_put(fixup_pos, pos, false);
1138 1139
      }
    }
1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150
  }
  L->bind_to(pos);

  // Keep track of the last bound label so we don't eliminate any instructions
  // before a bound label.
  if (pos > last_bound_pos_)
    last_bound_pos_ = pos;
}


void Assembler::bind(Label* L) {
1151
  DCHECK(!L->is_bound());  // Label can only be bound once.
1152 1153 1154 1155
  bind_to(L, pc_offset());
}


1156
void Assembler::next(Label* L, bool is_internal) {
1157
  DCHECK(L->is_linked());
1158
  int link = target_at(L->pos(), is_internal);
1159
  if (link == kEndOfChain) {
1160
    L->Unuse();
1161
  } else {
1162
    DCHECK_GE(link, 0);
1163
    L->link_to(link);
1164 1165 1166
  }
}

1167

1168
bool Assembler::is_near(Label* L) {
1169
  DCHECK(L->is_bound());
1170
  return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize;
1171 1172 1173 1174 1175
}


bool Assembler::is_near(Label* L, OffsetSize bits) {
  if (L == nullptr || !L->is_bound()) return true;
1176
  return pc_offset() - L->pos() < (1 << (bits + 2 - 1)) - 1 - 5 * kInstrSize;
1177 1178 1179 1180 1181
}


bool Assembler::is_near_branch(Label* L) {
  DCHECK(L->is_bound());
1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
  return IsMipsArchVariant(kMips32r6) ? is_near_r6(L) : is_near_pre_r6(L);
}


int Assembler::BranchOffset(Instr instr) {
  // At pre-R6 and for other R6 branches the offset is 16 bits.
  int bits = OffsetSize::kOffset16;

  if (IsMipsArchVariant(kMips32r6)) {
    uint32_t opcode = GetOpcodeField(instr);
    switch (opcode) {
      // Checks BC or BALC.
      case BC:
      case BALC:
        bits = OffsetSize::kOffset26;
        break;

      // Checks BEQZC or BNEZC.
      case POP66:
      case POP76:
        if (GetRsField(instr) != 0) bits = OffsetSize::kOffset21;
        break;
      default:
        break;
    }
  }

  return (1 << (bits + 2 - 1)) - 1;
1210
}
1211

1212

1213 1214 1215 1216
// We have to use a temporary register for things that can be relocated even
// if they can be encoded in the MIPS's 16 bits of immediate-offset instruction
// space.  There is no guarantee that the relocated location can be similarly
// encoded.
1217
bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
1218
  return !RelocInfo::IsNone(rmode);
1219 1220 1221 1222 1223 1224 1225 1226
}

void Assembler::GenInstrRegister(Opcode opcode,
                                 Register rs,
                                 Register rt,
                                 Register rd,
                                 uint16_t sa,
                                 SecondaryField func) {
1227
  DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
1228 1229 1230 1231 1232 1233
  Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
      | (rd.code() << kRdShift) | (sa << kSaShift) | func;
  emit(instr);
}


1234 1235 1236 1237 1238 1239
void Assembler::GenInstrRegister(Opcode opcode,
                                 Register rs,
                                 Register rt,
                                 uint16_t msb,
                                 uint16_t lsb,
                                 SecondaryField func) {
1240
  DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
1241 1242 1243 1244 1245 1246
  Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
      | (msb << kRdShift) | (lsb << kSaShift) | func;
  emit(instr);
}


1247 1248 1249 1250 1251 1252
void Assembler::GenInstrRegister(Opcode opcode,
                                 SecondaryField fmt,
                                 FPURegister ft,
                                 FPURegister fs,
                                 FPURegister fd,
                                 SecondaryField func) {
1253
  DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid());
1254 1255
  Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift)
      | (fd.code() << kFdShift) | func;
1256 1257 1258 1259
  emit(instr);
}


1260 1261 1262 1263 1264 1265
void Assembler::GenInstrRegister(Opcode opcode,
                                 FPURegister fr,
                                 FPURegister ft,
                                 FPURegister fs,
                                 FPURegister fd,
                                 SecondaryField func) {
1266
  DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());
1267 1268 1269 1270 1271 1272
  Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift)
      | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
  emit(instr);
}


1273 1274 1275 1276 1277 1278
void Assembler::GenInstrRegister(Opcode opcode,
                                 SecondaryField fmt,
                                 Register rt,
                                 FPURegister fs,
                                 FPURegister fd,
                                 SecondaryField func) {
1279
  DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid());
1280
  Instr instr = opcode | fmt | (rt.code() << kRtShift)
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290
      | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
  emit(instr);
}


void Assembler::GenInstrRegister(Opcode opcode,
                                 SecondaryField fmt,
                                 Register rt,
                                 FPUControlRegister fs,
                                 SecondaryField func) {
1291
  DCHECK(fs.is_valid() && rt.is_valid());
1292 1293
  Instr instr =
      opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
1294 1295 1296 1297 1298 1299
  emit(instr);
}


// Instructions with immediate value.
// Registers are in the order of the instruction encoding, from left to right.
1300 1301 1302
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt,
                                  int32_t j,
                                  CompactBranchType is_compact_branch) {
1303
  DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
1304 1305
  Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
      | (j & kImm16Mask);
1306
  emit(instr, is_compact_branch);
1307 1308
}

1309 1310 1311 1312 1313 1314 1315 1316 1317 1318
void Assembler::GenInstrImmediate(Opcode opcode, Register base, Register rt,
                                  int32_t offset9, int bit6,
                                  SecondaryField func) {
  DCHECK(base.is_valid() && rt.is_valid() && is_int9(offset9) &&
         is_uint1(bit6));
  Instr instr = opcode | (base.code() << kBaseShift) | (rt.code() << kRtShift) |
                ((offset9 << kImm9Shift) & kImm9Mask) | bit6 << kBit6Shift |
                func;
  emit(instr);
}
1319

1320 1321 1322
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF,
                                  int32_t j,
                                  CompactBranchType is_compact_branch) {
1323
  DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));
1324
  Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
1325
  emit(instr, is_compact_branch);
1326 1327 1328
}


1329 1330 1331
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft,
                                  int32_t j,
                                  CompactBranchType is_compact_branch) {
1332
  DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
1333 1334
  Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)
      | (j & kImm16Mask);
1335
  emit(instr, is_compact_branch);
1336 1337 1338
}


1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350
void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21,
                                  CompactBranchType is_compact_branch) {
  DCHECK(rs.is_valid() && (is_int21(offset21)));
  Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
  emit(instr, is_compact_branch);
}


void Assembler::GenInstrImmediate(Opcode opcode, Register rs,
                                  uint32_t offset21) {
  DCHECK(rs.is_valid() && (is_uint21(offset21)));
  Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1351 1352 1353 1354
  emit(instr);
}


1355 1356
void Assembler::GenInstrImmediate(Opcode opcode, int32_t offset26,
                                  CompactBranchType is_compact_branch) {
1357 1358
  DCHECK(is_int26(offset26));
  Instr instr = opcode | (offset26 & kImm26Mask);
1359
  emit(instr, is_compact_branch);
1360 1361 1362
}


1363
void Assembler::GenInstrJump(Opcode opcode,
1364
                             uint32_t address) {
1365
  BlockTrampolinePoolScope block_trampoline_pool(this);
1366
  DCHECK(is_uint26(address));
1367 1368
  Instr instr = opcode | address;
  emit(instr);
1369 1370 1371
  BlockTrampolinePoolFor(1);  // For associated delay slot.
}

1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
// MSA instructions
void Assembler::GenInstrMsaI8(SecondaryField operation, uint32_t imm8,
                              MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(ws.is_valid() && wd.is_valid() && is_uint8(imm8));
  Instr instr = MSA | operation | ((imm8 & kImm8Mask) << kWtShift) |
                (ws.code() << kWsShift) | (wd.code() << kWdShift);
  emit(instr);
}

void Assembler::GenInstrMsaI5(SecondaryField operation, SecondaryField df,
                              int32_t imm5, MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(ws.is_valid() && wd.is_valid());
  DCHECK((operation == MAXI_S) || (operation == MINI_S) ||
                 (operation == CEQI) || (operation == CLTI_S) ||
                 (operation == CLEI_S)
             ? is_int5(imm5)
             : is_uint5(imm5));
  Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) |
                (ws.code() << kWsShift) | (wd.code() << kWdShift);
  emit(instr);
}

void Assembler::GenInstrMsaBit(SecondaryField operation, SecondaryField df,
                               uint32_t m, MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(ws.is_valid() && wd.is_valid() && is_valid_msa_df_m(df, m));
  Instr instr = MSA | operation | df | (m << kWtShift) |
                (ws.code() << kWsShift) | (wd.code() << kWdShift);
  emit(instr);
}

void Assembler::GenInstrMsaI10(SecondaryField operation, SecondaryField df,
                               int32_t imm10, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(wd.is_valid() && is_int10(imm10));
  Instr instr = MSA | operation | df | ((imm10 & kImm10Mask) << kWsShift) |
                (wd.code() << kWdShift);
  emit(instr);
}

template <typename RegType>
void Assembler::GenInstrMsa3R(SecondaryField operation, SecondaryField df,
                              RegType t, MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(t.is_valid() && ws.is_valid() && wd.is_valid());
  Instr instr = MSA | operation | df | (t.code() << kWtShift) |
                (ws.code() << kWsShift) | (wd.code() << kWdShift);
  emit(instr);
}

template <typename DstType, typename SrcType>
void Assembler::GenInstrMsaElm(SecondaryField operation, SecondaryField df,
                               uint32_t n, SrcType src, DstType dst) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(src.is_valid() && dst.is_valid() && is_valid_msa_df_n(df, n));
  Instr instr = MSA | operation | df | (n << kWtShift) |
                (src.code() << kWsShift) | (dst.code() << kWdShift) |
                MSA_ELM_MINOR;
  emit(instr);
}

void Assembler::GenInstrMsa3RF(SecondaryField operation, uint32_t df,
                               MSARegister wt, MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(wt.is_valid() && ws.is_valid() && wd.is_valid());
1439
  DCHECK_LT(df, 2);
1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492
  Instr instr = MSA | operation | (df << 21) | (wt.code() << kWtShift) |
                (ws.code() << kWsShift) | (wd.code() << kWdShift);
  emit(instr);
}

void Assembler::GenInstrMsaVec(SecondaryField operation, MSARegister wt,
                               MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(wt.is_valid() && ws.is_valid() && wd.is_valid());
  Instr instr = MSA | operation | (wt.code() << kWtShift) |
                (ws.code() << kWsShift) | (wd.code() << kWdShift) |
                MSA_VEC_2R_2RF_MINOR;
  emit(instr);
}

void Assembler::GenInstrMsaMI10(SecondaryField operation, int32_t s10,
                                Register rs, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(rs.is_valid() && wd.is_valid() && is_int10(s10));
  Instr instr = MSA | operation | ((s10 & kImm10Mask) << kWtShift) |
                (rs.code() << kWsShift) | (wd.code() << kWdShift);
  emit(instr);
}

void Assembler::GenInstrMsa2R(SecondaryField operation, SecondaryField df,
                              MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(ws.is_valid() && wd.is_valid());
  Instr instr = MSA | MSA_2R_FORMAT | operation | df | (ws.code() << kWsShift) |
                (wd.code() << kWdShift) | MSA_VEC_2R_2RF_MINOR;
  emit(instr);
}

void Assembler::GenInstrMsa2RF(SecondaryField operation, SecondaryField df,
                               MSARegister ws, MSARegister wd) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(ws.is_valid() && wd.is_valid());
  Instr instr = MSA | MSA_2RF_FORMAT | operation | df |
                (ws.code() << kWsShift) | (wd.code() << kWdShift) |
                MSA_VEC_2R_2RF_MINOR;
  emit(instr);
}

void Assembler::GenInstrMsaBranch(SecondaryField operation, MSARegister wt,
                                  int32_t offset16) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(wt.is_valid() && is_int16(offset16));
  BlockTrampolinePoolScope block_trampoline_pool(this);
  Instr instr =
      COP1 | operation | (wt.code() << kWtShift) | (offset16 & kImm16Mask);
  emit(instr);
  BlockTrampolinePoolFor(1);  // For associated delay slot.
}
1493

1494 1495 1496
// Returns the next free trampoline entry.
int32_t Assembler::get_trampoline_entry(int32_t pos) {
  int32_t trampoline_entry = kInvalidSlotPos;
1497

1498 1499 1500
  if (!internal_trampoline_exception_) {
    if (trampoline_.start() > pos) {
     trampoline_entry = trampoline_.take_slot();
1501
    }
1502 1503 1504

    if (kInvalidSlotPos == trampoline_entry) {
      internal_trampoline_exception_ = true;
1505 1506
    }
  }
1507
  return trampoline_entry;
1508 1509 1510
}


1511 1512
uint32_t Assembler::jump_address(Label* L) {
  int32_t target_pos;
1513

1514 1515 1516 1517 1518 1519 1520 1521 1522
  if (L->is_bound()) {
    target_pos = L->pos();
  } else {
    if (L->is_linked()) {
      target_pos = L->pos();  // L's link.
      L->link_to(pc_offset());
    } else {
      L->link_to(pc_offset());
      return kEndOfJumpChain;
1523
    }
1524
  }
1525

1526
  uint32_t imm = reinterpret_cast<uint32_t>(buffer_start_) + target_pos;
1527
  DCHECK_EQ(imm & 3, 0);
1528 1529

  return imm;
1530 1531
}

1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553
uint32_t Assembler::branch_long_offset(Label* L) {
  int32_t target_pos;

  if (L->is_bound()) {
    target_pos = L->pos();
  } else {
    if (L->is_linked()) {
      target_pos = L->pos();  // L's link.
      L->link_to(pc_offset());
    } else {
      L->link_to(pc_offset());
      return kEndOfJumpChain;
    }
  }

  DCHECK(is_int32(static_cast<int64_t>(target_pos) -
                  static_cast<int64_t>(pc_offset() + kLongBranchPCOffset)));
  int32_t offset = target_pos - (pc_offset() + kLongBranchPCOffset);
  DCHECK_EQ(offset & 3, 0);

  return offset;
}
1554

1555
int32_t Assembler::branch_offset_helper(Label* L, OffsetSize bits) {
1556
  int32_t target_pos;
1557
  int32_t pad = IsPrevInstrCompactBranch() ? kInstrSize : 0;
1558 1559 1560 1561 1562 1563

  if (L->is_bound()) {
    target_pos = L->pos();
  } else {
    if (L->is_linked()) {
      target_pos = L->pos();
1564
      L->link_to(pc_offset() + pad);
1565
    } else {
1566
      L->link_to(pc_offset() + pad);
1567 1568 1569 1570 1571 1572 1573 1574
      if (!trampoline_emitted_) {
        unbound_labels_count_++;
        next_buffer_check_ -= kTrampolineSlotsSize;
      }
      return kEndOfChain;
    }
  }

1575 1576
  int32_t offset = target_pos - (pc_offset() + kBranchPCOffset + pad);
  DCHECK(is_intn(offset, bits + 2));
1577
  DCHECK_EQ(offset & 3, 0);
1578 1579 1580 1581 1582

  return offset;
}


1583 1584 1585 1586
void Assembler::label_at_put(Label* L, int at_offset) {
  int target_pos;
  if (L->is_bound()) {
    target_pos = L->pos();
1587
    instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
1588 1589
  } else {
    if (L->is_linked()) {
1590 1591
      target_pos = L->pos();  // L's link.
      int32_t imm18 = target_pos - at_offset;
1592
      DCHECK_EQ(imm18 & 3, 0);
1593
      int32_t imm16 = imm18 >> 2;
1594
      DCHECK(is_int16(imm16));
1595
      instr_at_put(at_offset, (imm16 & kImm16Mask));
1596 1597
    } else {
      target_pos = kEndOfChain;
1598
      instr_at_put(at_offset, 0);
1599 1600 1601 1602
      if (!trampoline_emitted_) {
        unbound_labels_count_++;
        next_buffer_check_ -= kTrampolineSlotsSize;
      }
1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
    }
    L->link_to(at_offset);
  }
}


//------- Branch and jump instructions --------

void Assembler::b(int16_t offset) {
  beq(zero_reg, zero_reg, offset);
}


void Assembler::bal(int16_t offset) {
  bgezal(zero_reg, offset);
}


1621 1622
void Assembler::bc(int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1623
  GenInstrImmediate(BC, offset, CompactBranchType::COMPACT_BRANCH);
1624 1625 1626 1627 1628
}


void Assembler::balc(int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1629
  GenInstrImmediate(BALC, offset, CompactBranchType::COMPACT_BRANCH);
1630 1631 1632
}


1633
void Assembler::beq(Register rs, Register rt, int16_t offset) {
1634
  BlockTrampolinePoolScope block_trampoline_pool(this);
1635
  GenInstrImmediate(BEQ, rs, rt, offset);
1636
  BlockTrampolinePoolFor(1);  // For associated delay slot.
1637 1638 1639 1640
}


void Assembler::bgez(Register rs, int16_t offset) {
1641
  BlockTrampolinePoolScope block_trampoline_pool(this);
1642
  GenInstrImmediate(REGIMM, rs, BGEZ, offset);
1643
  BlockTrampolinePoolFor(1);  // For associated delay slot.
1644 1645 1646
}


1647 1648
void Assembler::bgezc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1649
  DCHECK(rt != zero_reg);
1650
  GenInstrImmediate(BLEZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
1651 1652 1653 1654 1655
}


void Assembler::bgeuc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1656 1657
  DCHECK(rs != zero_reg);
  DCHECK(rt != zero_reg);
1658
  DCHECK(rs.code() != rt.code());
1659
  GenInstrImmediate(BLEZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1660 1661 1662 1663 1664
}


void Assembler::bgec(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1665 1666
  DCHECK(rs != zero_reg);
  DCHECK(rt != zero_reg);
1667
  DCHECK(rs.code() != rt.code());
1668
  GenInstrImmediate(BLEZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1669 1670 1671
}


1672
void Assembler::bgezal(Register rs, int16_t offset) {
1673 1674
  DCHECK(!IsMipsArchVariant(kMips32r6) || rs == zero_reg);
  DCHECK(rs != ra);
1675
  BlockTrampolinePoolScope block_trampoline_pool(this);
1676
  GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
1677
  BlockTrampolinePoolFor(1);  // For associated delay slot.
1678 1679 1680 1681
}


void Assembler::bgtz(Register rs, int16_t offset) {
1682
  BlockTrampolinePoolScope block_trampoline_pool(this);
1683
  GenInstrImmediate(BGTZ, rs, zero_reg, offset);
1684
  BlockTrampolinePoolFor(1);  // For associated delay slot.
1685 1686 1687
}


1688 1689
void Assembler::bgtzc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1690
  DCHECK(rt != zero_reg);
1691 1692
  GenInstrImmediate(BGTZL, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
1693 1694 1695
}


1696
void Assembler::blez(Register rs, int16_t offset) {
1697
  BlockTrampolinePoolScope block_trampoline_pool(this);
1698
  GenInstrImmediate(BLEZ, rs, zero_reg, offset);
1699
  BlockTrampolinePoolFor(1);  // For associated delay slot.
1700 1701 1702
}


1703 1704
void Assembler::blezc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1705
  DCHECK(rt != zero_reg);
1706 1707
  GenInstrImmediate(BLEZL, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
1708 1709 1710 1711 1712
}


void Assembler::bltzc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1713
  DCHECK(rt != zero_reg);
1714
  GenInstrImmediate(BGTZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
1715 1716 1717 1718 1719
}


void Assembler::bltuc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1720 1721
  DCHECK(rs != zero_reg);
  DCHECK(rt != zero_reg);
1722
  DCHECK(rs.code() != rt.code());
1723
  GenInstrImmediate(BGTZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1724 1725 1726 1727 1728
}


void Assembler::bltc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
1729 1730
  DCHECK(rs != zero_reg);
  DCHECK(rt != zero_reg);
1731
  DCHECK(rs.code() != rt.code());
1732
  GenInstrImmediate(BGTZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1733 1734 1735
}


1736
void Assembler::bltz(Register rs, int16_t offset) {
1737
  BlockTrampolinePoolScope block_trampoline_pool(this);
1738
  GenInstrImmediate(REGIMM, rs, BLTZ, offset);
1739
  BlockTrampolinePoolFor(1);  // For associated delay slot.
1740 1741 1742 1743
}


void Assembler::bltzal(Register rs, int16_t offset) {
1744 1745
  DCHECK(!IsMipsArchVariant(kMips32r6) || rs == zero_reg);
  DCHECK(rs != ra);
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::bne(Register rs, Register rt, int16_t offset) {
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(BNE, rs, rt, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


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void Assembler::bovc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  if (rs.code() >= rt.code()) {
    GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  if (rs.code() >= rt.code()) {
    GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::blezalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rt != zero_reg);
  DCHECK(rt != ra);
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  GenInstrImmediate(BLEZ, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgezalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rt != zero_reg);
  DCHECK(rt != ra);
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  GenInstrImmediate(BLEZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgezall(Register rs, int16_t offset) {
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  DCHECK(!IsMipsArchVariant(kMips32r6));
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  DCHECK(rs != zero_reg);
  DCHECK(rs != ra);
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::bltzalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rt != zero_reg);
  DCHECK(rt != ra);
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  GenInstrImmediate(BGTZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bgtzalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rt != zero_reg);
  DCHECK(rt != ra);
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  GenInstrImmediate(BGTZ, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::beqzalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rt != zero_reg);
  DCHECK(rt != ra);
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  GenInstrImmediate(ADDI, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bnezalc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rt != zero_reg);
  DCHECK(rt != ra);
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  GenInstrImmediate(DADDI, zero_reg, rt, offset,
                    CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::beqc(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
  if (rs.code() < rt.code()) {
    GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::beqzc(Register rs, int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs != zero_reg);
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  GenInstrImmediate(POP66, rs, offset, CompactBranchType::COMPACT_BRANCH);
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}


void Assembler::bnec(Register rs, Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0);
  if (rs.code() < rt.code()) {
    GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
  } else {
    GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
  }
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}


void Assembler::bnezc(Register rs, int32_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs != zero_reg);
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  GenInstrImmediate(POP76, rs, offset, CompactBranchType::COMPACT_BRANCH);
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}


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void Assembler::j(int32_t target) {
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#if DEBUG
  // Get pc of delay slot.
  uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
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  bool in_range = ((ipc ^ static_cast<uint32_t>(target)) >>
                   (kImm26Bits + kImmFieldShift)) == 0;
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  DCHECK(in_range && ((target & 3) == 0));
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#endif
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrJump(J, (target >> 2) & kImm26Mask);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::jr(Register rs) {
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  if (!IsMipsArchVariant(kMips32r6)) {
    BlockTrampolinePoolScope block_trampoline_pool(this);
    GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
    BlockTrampolinePoolFor(1);  // For associated delay slot.
  } else {
    jalr(rs, zero_reg);
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  }
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}


void Assembler::jal(int32_t target) {
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#ifdef DEBUG
  // Get pc of delay slot.
  uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
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  bool in_range = ((ipc ^ static_cast<uint32_t>(target)) >>
                   (kImm26Bits + kImmFieldShift)) == 0;
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  DCHECK(in_range && ((target & 3) == 0));
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#endif
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrJump(JAL, (target >> 2) & kImm26Mask);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


void Assembler::jalr(Register rs, Register rd) {
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  DCHECK(rs.code() != rd.code());
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  BlockTrampolinePoolScope block_trampoline_pool(this);
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  GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
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  BlockTrampolinePoolFor(1);  // For associated delay slot.
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}


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void Assembler::jic(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  GenInstrImmediate(POP66, zero_reg, rt, offset);
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}


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void Assembler::jialc(Register rt, int16_t offset) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  GenInstrImmediate(POP76, zero_reg, rt, offset);
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}


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// -------Data-processing-instructions---------
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// Arithmetic.

void Assembler::addu(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
}


void Assembler::addiu(Register rd, Register rs, int32_t j) {
  GenInstrImmediate(ADDIU, rs, rd, j);
}


void Assembler::subu(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
}


void Assembler::mul(Register rd, Register rs, Register rt) {
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  if (!IsMipsArchVariant(kMips32r6)) {
    GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
  } else {
    GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
  }
}


void Assembler::mulu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
}


void Assembler::muh(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
}


void Assembler::muhu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
}


void Assembler::mod(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
}


void Assembler::modu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
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}


void Assembler::mult(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
}


void Assembler::multu(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
}


void Assembler::div(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
}


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void Assembler::div(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
}


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void Assembler::divu(Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
}


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void Assembler::divu(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
}


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// Logical.

void Assembler::and_(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
}


void Assembler::andi(Register rt, Register rs, int32_t j) {
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  DCHECK(is_uint16(j));
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  GenInstrImmediate(ANDI, rs, rt, j);
}


void Assembler::or_(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
}


void Assembler::ori(Register rt, Register rs, int32_t j) {
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  DCHECK(is_uint16(j));
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  GenInstrImmediate(ORI, rs, rt, j);
}


void Assembler::xor_(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
}


void Assembler::xori(Register rt, Register rs, int32_t j) {
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  DCHECK(is_uint16(j));
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  GenInstrImmediate(XORI, rs, rt, j);
}


void Assembler::nor(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
}


// Shifts.
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void Assembler::sll(Register rd,
                    Register rt,
                    uint16_t sa,
                    bool coming_from_nop) {
  // Don't allow nop instructions in the form sll zero_reg, zero_reg to be
  // generated using the sll instruction. They must be generated using
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  // nop(int/NopMarkerTypes).
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  DCHECK(coming_from_nop || !(rd == zero_reg && rt == zero_reg));
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  GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
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}


void Assembler::sllv(Register rd, Register rt, Register rs) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
}


void Assembler::srl(Register rd, Register rt, uint16_t sa) {
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  GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
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}


void Assembler::srlv(Register rd, Register rt, Register rs) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
}


void Assembler::sra(Register rd, Register rt, uint16_t sa) {
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  GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA);
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}


void Assembler::srav(Register rd, Register rt, Register rs) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
}


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void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
  // Should be called via MacroAssembler::Ror.
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  DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
      | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
  emit(instr);
}


void Assembler::rotrv(Register rd, Register rt, Register rs) {
  // Should be called via MacroAssembler::Ror.
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  DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
     | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
  emit(instr);
}


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void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) {
  DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid());
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  DCHECK_LE(sa, 3);
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  DCHECK(IsMipsArchVariant(kMips32r6));
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  Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift |
                rd.code() << kRdShift | sa << kSaShift | LSA;
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  emit(instr);
}


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// ------------Memory-instructions-------------
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void Assembler::AdjustBaseAndOffset(MemOperand& src,
                                    OffsetAccessType access_type,
                                    int second_access_add_to_offset) {
  // This method is used to adjust the base register and offset pair
  // for a load/store when the offset doesn't fit into int16_t.
  // It is assumed that 'base + offset' is sufficiently aligned for memory
  // operands that are machine word in size or smaller. For doubleword-sized
  // operands it's assumed that 'base' is a multiple of 8, while 'offset'
  // may be a multiple of 4 (e.g. 4-byte-aligned long and double arguments
  // and spilled variables on the stack accessed relative to the stack
  // pointer register).
  // We preserve the "alignment" of 'offset' by adjusting it by a multiple of 8.

  bool doubleword_aligned = (src.offset() & (kDoubleSize - 1)) == 0;
  bool two_accesses = static_cast<bool>(access_type) || !doubleword_aligned;
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  DCHECK_LE(second_access_add_to_offset, 7);  // Must be <= 7.
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  // is_int16 must be passed a signed value, hence the static cast below.
  if (is_int16(src.offset()) &&
      (!two_accesses || is_int16(static_cast<int32_t>(
                            src.offset() + second_access_add_to_offset)))) {
    // Nothing to do: 'offset' (and, if needed, 'offset + 4', or other specified
    // value) fits into int16_t.
    return;
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  }
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  UseScratchRegisterScope temps(this);
  Register scratch = temps.Acquire();
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  DCHECK(src.rm() != scratch);  // Must not overwrite the register 'base'
                                // while loading 'offset'.
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#ifdef DEBUG
  // Remember the "(mis)alignment" of 'offset', it will be checked at the end.
  uint32_t misalignment = src.offset() & (kDoubleSize - 1);
#endif

  // Do not load the whole 32-bit 'offset' if it can be represented as
  // a sum of two 16-bit signed offsets. This can save an instruction or two.
  // To simplify matters, only do this for a symmetric range of offsets from
  // about -64KB to about +64KB, allowing further addition of 4 when accessing
  // 64-bit variables with two 32-bit accesses.
  constexpr int32_t kMinOffsetForSimpleAdjustment =
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      0x7FF8;  // Max int16_t that's a multiple of 8.
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  constexpr int32_t kMaxOffsetForSimpleAdjustment =
      2 * kMinOffsetForSimpleAdjustment;
  if (0 <= src.offset() && src.offset() <= kMaxOffsetForSimpleAdjustment) {
    addiu(at, src.rm(), kMinOffsetForSimpleAdjustment);
    src.offset_ -= kMinOffsetForSimpleAdjustment;
  } else if (-kMaxOffsetForSimpleAdjustment <= src.offset() &&
             src.offset() < 0) {
    addiu(at, src.rm(), -kMinOffsetForSimpleAdjustment);
    src.offset_ += kMinOffsetForSimpleAdjustment;
  } else if (IsMipsArchVariant(kMips32r6)) {
    // On r6 take advantage of the aui instruction, e.g.:
    //   aui   at, base, offset_high
    //   lw    reg_lo, offset_low(at)
    //   lw    reg_hi, (offset_low+4)(at)
    // or when offset_low+4 overflows int16_t:
    //   aui   at, base, offset_high
    //   addiu at, at, 8
    //   lw    reg_lo, (offset_low-8)(at)
    //   lw    reg_hi, (offset_low-4)(at)
    int16_t offset_high = static_cast<uint16_t>(src.offset() >> 16);
    int16_t offset_low = static_cast<uint16_t>(src.offset());
    offset_high += (offset_low < 0)
                       ? 1
                       : 0;  // Account for offset sign extension in load/store.
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    aui(scratch, src.rm(), static_cast<uint16_t>(offset_high));
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    if (two_accesses && !is_int16(static_cast<int32_t>(
                            offset_low + second_access_add_to_offset))) {
      // Avoid overflow in the 16-bit offset of the load/store instruction when
      // adding 4.
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      addiu(scratch, scratch, kDoubleSize);
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      offset_low -= kDoubleSize;
    }
    src.offset_ = offset_low;
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  } else {
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    // Do not load the whole 32-bit 'offset' if it can be represented as
    // a sum of three 16-bit signed offsets. This can save an instruction.
    // To simplify matters, only do this for a symmetric range of offsets from
    // about -96KB to about +96KB, allowing further addition of 4 when accessing
    // 64-bit variables with two 32-bit accesses.
    constexpr int32_t kMinOffsetForMediumAdjustment =
        2 * kMinOffsetForSimpleAdjustment;
    constexpr int32_t kMaxOffsetForMediumAdjustment =
        3 * kMinOffsetForSimpleAdjustment;
    if (0 <= src.offset() && src.offset() <= kMaxOffsetForMediumAdjustment) {
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      addiu(scratch, src.rm(), kMinOffsetForMediumAdjustment / 2);
      addiu(scratch, scratch, kMinOffsetForMediumAdjustment / 2);
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      src.offset_ -= kMinOffsetForMediumAdjustment;
    } else if (-kMaxOffsetForMediumAdjustment <= src.offset() &&
               src.offset() < 0) {
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      addiu(scratch, src.rm(), -kMinOffsetForMediumAdjustment / 2);
      addiu(scratch, scratch, -kMinOffsetForMediumAdjustment / 2);
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      src.offset_ += kMinOffsetForMediumAdjustment;
    } else {
      // Now that all shorter options have been exhausted, load the full 32-bit
      // offset.
      int32_t loaded_offset = RoundDown(src.offset(), kDoubleSize);
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      lui(scratch, (loaded_offset >> kLuiShift) & kImm16Mask);
      ori(scratch, scratch, loaded_offset & kImm16Mask);  // Load 32-bit offset.
      addu(scratch, scratch, src.rm());
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      src.offset_ -= loaded_offset;
    }
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  }
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  src.rm_ = scratch;
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  DCHECK(is_int16(src.offset()));
  if (two_accesses) {
    DCHECK(is_int16(
        static_cast<int32_t>(src.offset() + second_access_add_to_offset)));
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  }
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  DCHECK(misalignment == (src.offset() & (kDoubleSize - 1)));
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}
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void Assembler::lb(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(LB, source.rm(), rd, source.offset());
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}


void Assembler::lbu(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(LBU, source.rm(), rd, source.offset());
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}


void Assembler::lh(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(LH, source.rm(), rd, source.offset());
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}


void Assembler::lhu(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(LHU, source.rm(), rd, source.offset());
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}


void Assembler::lw(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(LW, source.rm(), rd, source.offset());
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}


void Assembler::lwl(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
}


void Assembler::lwr(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
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}


void Assembler::sb(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(SB, source.rm(), rd, source.offset());
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}


void Assembler::sh(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(SH, source.rm(), rd, source.offset());
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}


void Assembler::sw(Register rd, const MemOperand& rs) {
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  MemOperand source = rs;
  AdjustBaseAndOffset(source);
  GenInstrImmediate(SW, source.rm(), rd, source.offset());
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}


void Assembler::swl(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
}


void Assembler::swr(Register rd, const MemOperand& rs) {
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  DCHECK(is_int16(rs.offset_));
  DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
         IsMipsArchVariant(kMips32r2));
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  GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
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}

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void Assembler::ll(Register rd, const MemOperand& rs) {
  if (IsMipsArchVariant(kMips32r6)) {
    DCHECK(is_int9(rs.offset_));
    GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, LL_R6);
  } else {
    DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
           IsMipsArchVariant(kMips32r2));
    DCHECK(is_int16(rs.offset_));
    GenInstrImmediate(LL, rs.rm(), rd, rs.offset_);
  }
}

void Assembler::sc(Register rd, const MemOperand& rs) {
  if (IsMipsArchVariant(kMips32r6)) {
    DCHECK(is_int9(rs.offset_));
    GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 0, SC_R6);
  } else {
    DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
           IsMipsArchVariant(kMips32r2));
    GenInstrImmediate(SC, rs.rm(), rd, rs.offset_);
  }
}
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void Assembler::llx(Register rd, const MemOperand& rs) {
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  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(is_int9(rs.offset_));
  GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 1, LL_R6);
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}

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void Assembler::scx(Register rd, const MemOperand& rs) {
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  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(is_int9(rs.offset_));
  GenInstrImmediate(SPECIAL3, rs.rm(), rd, rs.offset_, 1, SC_R6);
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}

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void Assembler::lui(Register rd, int32_t j) {
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  DCHECK(is_uint16(j) || is_int16(j));
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  GenInstrImmediate(LUI, zero_reg, rd, j);
}


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void Assembler::aui(Register rt, Register rs, int32_t j) {
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  // This instruction uses same opcode as 'lui'. The difference in encoding is
  // 'lui' has zero reg. for rs field.
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  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs != zero_reg);
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  DCHECK(is_uint16(j));
  GenInstrImmediate(LUI, rs, rt, j);
}

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// ---------PC-Relative instructions-----------

void Assembler::addiupc(Register rs, int32_t imm19) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(rs.is_valid() && is_int19(imm19));
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  uint32_t imm21 = ADDIUPC << kImm19Bits | (imm19 & kImm19Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


void Assembler::lwpc(Register rs, int32_t offset19) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(rs.is_valid() && is_int19(offset19));
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  uint32_t imm21 = LWPC << kImm19Bits | (offset19 & kImm19Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


void Assembler::auipc(Register rs, int16_t imm16) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.is_valid());
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  uint32_t imm21 = AUIPC << kImm16Bits | (imm16 & kImm16Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


void Assembler::aluipc(Register rs, int16_t imm16) {
  DCHECK(IsMipsArchVariant(kMips32r6));
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  DCHECK(rs.is_valid());
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  uint32_t imm21 = ALUIPC << kImm16Bits | (imm16 & kImm16Mask);
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  GenInstrImmediate(PCREL, rs, imm21);
}


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// -------------Misc-instructions--------------
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// Break / Trap instructions.
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void Assembler::break_(uint32_t code, bool break_as_stop) {
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  DCHECK_EQ(code & ~0xFFFFF, 0);
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  // We need to invalidate breaks that could be stops as well because the
  // simulator expects a char pointer after the stop instruction.
  // See constants-mips.h for explanation.
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  DCHECK((break_as_stop &&
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          code <= kMaxStopCode &&
          code > kMaxWatchpointCode) ||
         (!break_as_stop &&
          (code > kMaxStopCode ||
           code <= kMaxWatchpointCode)));
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  Instr break_instr = SPECIAL | BREAK | (code << 6);
  emit(break_instr);
}


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void Assembler::stop(const char* msg, uint32_t code) {
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  DCHECK_GT(code, kMaxWatchpointCode);
  DCHECK_LE(code, kMaxStopCode);
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#if V8_HOST_ARCH_MIPS
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  break_(0x54321);
#else  // V8_HOST_ARCH_MIPS
  break_(code, true);
#endif
}


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void Assembler::tge(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr = SPECIAL | TGE | rs.code() << kRsShift
      | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr = SPECIAL | TGEU | rs.code() << kRsShift
      | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tlt(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tltu(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TLTU | rs.code() << kRsShift
      | rt.code() << kRtShift | code << 6;
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  emit(instr);
}


void Assembler::teq(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
  emit(instr);
}


void Assembler::tne(Register rs, Register rt, uint16_t code) {
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  DCHECK(is_uint10(code));
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  Instr instr =
      SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
  emit(instr);
}

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void Assembler::sync() {
  Instr sync_instr = SPECIAL | SYNC;
  emit(sync_instr);
}
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// Move from HI/LO register.

void Assembler::mfhi(Register rd) {
  GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
}


void Assembler::mflo(Register rd) {
  GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
}


// Set on less than instructions.
void Assembler::slt(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
}


void Assembler::sltu(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
}


void Assembler::slti(Register rt, Register rs, int32_t j) {
  GenInstrImmediate(SLTI, rs, rt, j);
}


void Assembler::sltiu(Register rt, Register rs, int32_t j) {
  GenInstrImmediate(SLTIU, rs, rt, j);
}


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// Conditional move.
void Assembler::movz(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
}


void Assembler::movn(Register rd, Register rs, Register rt) {
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
}


void Assembler::movt(Register rd, Register rs, uint16_t cc) {
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  Register rt = Register::from_code((cc & 0x0007) << 2 | 1);
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  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
}


void Assembler::movf(Register rd, Register rs, uint16_t cc) {
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  Register rt = Register::from_code((cc & 0x0007) << 2 | 0);
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  GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
}


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void Assembler::seleqz(Register rd, Register rs, Register rt) {
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  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
}


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// Bit twiddling.
void Assembler::clz(Register rd, Register rs) {
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  if (!IsMipsArchVariant(kMips32r6)) {
    // Clz instr requires same GPR number in 'rd' and 'rt' fields.
    GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
  } else {
    GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
  }
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}


void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
  // Should be called via MacroAssembler::Ins.
  // Ins instr has 'rt' field as dest, and two uint5: msb, lsb.
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);
}


void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
  // Should be called via MacroAssembler::Ext.
  // Ext instr has 'rt' field as dest, and two uint5: msb, lsb.
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  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
}


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void Assembler::bitswap(Register rd, Register rt) {
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  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL);
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}


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void Assembler::pref(int32_t hint, const MemOperand& rs) {
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  DCHECK(!IsMipsArchVariant(kLoongson));
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  DCHECK(is_uint5(hint) && is_uint16(rs.offset_));
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plind44@gmail.com committed
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  Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift)
      | (rs.offset_);
  emit(instr);
}


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void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK(is_uint3(bp));
  uint16_t sa = (ALIGN << kBp2Bits) | bp;
  GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL);
}

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// Byte swap.
void Assembler::wsbh(Register rd, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL);
}

void Assembler::seh(Register rd, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEH, BSHFL);
}

void Assembler::seb(Register rd, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEB, BSHFL);
}
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// --------Coprocessor-instructions----------------
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// Load, store, move.
void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
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  MemOperand tmp = src;
  AdjustBaseAndOffset(tmp);
  GenInstrImmediate(LWC1, tmp.rm(), fd, tmp.offset());
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}


void Assembler::swc1(FPURegister fd, const MemOperand& src) {
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  MemOperand tmp = src;
  AdjustBaseAndOffset(tmp);
  GenInstrImmediate(SWC1, tmp.rm(), fd, tmp.offset());
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}


2648
void Assembler::mtc1(Register rt, FPURegister fs) {
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  GenInstrRegister(COP1, MTC1, rt, fs, f0);
}


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void Assembler::mthc1(Register rt, FPURegister fs) {
  GenInstrRegister(COP1, MTHC1, rt, fs, f0);
}


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void Assembler::mfc1(Register rt, FPURegister fs) {
  GenInstrRegister(COP1, MFC1, rt, fs, f0);
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}


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void Assembler::mfhc1(Register rt, FPURegister fs) {
  GenInstrRegister(COP1, MFHC1, rt, fs, f0);
}


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void Assembler::ctc1(Register rt, FPUControlRegister fs) {
  GenInstrRegister(COP1, CTC1, rt, fs);
}


void Assembler::cfc1(Register rt, FPUControlRegister fs) {
  GenInstrRegister(COP1, CFC1, rt, fs);
}

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2678
void Assembler::movn_s(FPURegister fd, FPURegister fs, Register rt) {
2679
  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, S, rt, fs, fd, MOVN_C);
}


void Assembler::movn_d(FPURegister fd, FPURegister fs, Register rt) {
2685
  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, D, rt, fs, fd, MOVN_C);
}


void Assembler::sel(SecondaryField fmt, FPURegister fd, FPURegister fs,
                    FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));

  GenInstrRegister(COP1, fmt, ft, fs, fd, SEL);
}


void Assembler::sel_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  sel(S, fd, fs, ft);
}


void Assembler::sel_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  sel(D, fd, fs, ft);
}


void Assembler::seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, SELEQZ_C);
}


void Assembler::selnez(Register rd, Register rs, Register rt) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S);
}


void Assembler::selnez(SecondaryField fmt, FPURegister fd, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, SELNEZ_C);
}


void Assembler::seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  seleqz(D, fd, fs, ft);
}


void Assembler::seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  seleqz(S, fd, fs, ft);
}


void Assembler::selnez_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  selnez(D, fd, fs, ft);
}


void Assembler::selnez_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  selnez(S, fd, fs, ft);
}


void Assembler::movz_s(FPURegister fd, FPURegister fs, Register rt) {
2752
  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, S, rt, fs, fd, MOVZ_C);
}


void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) {
2758
  DCHECK(!IsMipsArchVariant(kMips32r6));
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  GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C);
}


void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) {
2764
  DCHECK(!IsMipsArchVariant(kMips32r6));
2765
  FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 1);
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  GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
}


void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2771
  DCHECK(!IsMipsArchVariant(kMips32r6));
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  FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 1);
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  GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
}


void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) {
2778
  DCHECK(!IsMipsArchVariant(kMips32r6));
2779
  FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 0);
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  GenInstrRegister(COP1, S, ft, fs, fd, MOVF);
}


void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) {
2785
  DCHECK(!IsMipsArchVariant(kMips32r6));
2786
  FPURegister ft = FPURegister::from_code((cc & 0x0007) << 2 | 0);
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  GenInstrRegister(COP1, D, ft, fs, fd, MOVF);
}


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// Arithmetic.

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void Assembler::add_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2794
  GenInstrRegister(COP1, S, ft, fs, fd, ADD_S);
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}


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void Assembler::add_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, ADD_D);
}


2803
void Assembler::sub_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2804
  GenInstrRegister(COP1, S, ft, fs, fd, SUB_S);
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}


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void Assembler::sub_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, SUB_D);
}


2813
void Assembler::mul_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2814
  GenInstrRegister(COP1, S, ft, fs, fd, MUL_S);
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}


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void Assembler::mul_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, MUL_D);
}

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void Assembler::madd_s(FPURegister fd, FPURegister fr, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r2));
  GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_S);
}
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void Assembler::madd_d(FPURegister fd, FPURegister fr, FPURegister fs,
    FPURegister ft) {
2830
  DCHECK(IsMipsArchVariant(kMips32r2));
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  GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_D);
}

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void Assembler::msub_s(FPURegister fd, FPURegister fr, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r2));
  GenInstrRegister(COP1X, fr, ft, fs, fd, MSUB_S);
}

void Assembler::msub_d(FPURegister fd, FPURegister fr, FPURegister fs,
                       FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r2));
  GenInstrRegister(COP1X, fr, ft, fs, fd, MSUB_D);
}

void Assembler::maddf_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, S, ft, fs, fd, MADDF_S);
}

void Assembler::maddf_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, D, ft, fs, fd, MADDF_D);
}

void Assembler::msubf_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, S, ft, fs, fd, MSUBF_S);
}

void Assembler::msubf_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, D, ft, fs, fd, MSUBF_D);
}
2865

2866
void Assembler::div_s(FPURegister fd, FPURegister fs, FPURegister ft) {
2867
  GenInstrRegister(COP1, S, ft, fs, fd, DIV_S);
2868 2869 2870
}


2871 2872 2873 2874 2875
void Assembler::div_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  GenInstrRegister(COP1, D, ft, fs, fd, DIV_D);
}


2876
void Assembler::abs_s(FPURegister fd, FPURegister fs) {
2877
  GenInstrRegister(COP1, S, f0, fs, fd, ABS_S);
2878 2879 2880
}


2881 2882
void Assembler::abs_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, ABS_D);
2883 2884 2885
}


2886
void Assembler::mov_d(FPURegister fd, FPURegister fs) {
2887
  GenInstrRegister(COP1, D, f0, fs, fd, MOV_D);
2888 2889 2890 2891
}


void Assembler::mov_s(FPURegister fd, FPURegister fs) {
2892
  GenInstrRegister(COP1, S, f0, fs, fd, MOV_S);
2893 2894 2895
}


2896
void Assembler::neg_s(FPURegister fd, FPURegister fs) {
2897
  GenInstrRegister(COP1, S, f0, fs, fd, NEG_S);
2898 2899 2900
}


2901 2902 2903 2904 2905
void Assembler::neg_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, NEG_D);
}


2906
void Assembler::sqrt_s(FPURegister fd, FPURegister fs) {
2907
  GenInstrRegister(COP1, S, f0, fs, fd, SQRT_S);
2908 2909 2910
}


2911 2912
void Assembler::sqrt_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, SQRT_D);
2913 2914 2915
}


2916
void Assembler::rsqrt_s(FPURegister fd, FPURegister fs) {
2917
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2918 2919 2920 2921 2922
  GenInstrRegister(COP1, S, f0, fs, fd, RSQRT_S);
}


void Assembler::rsqrt_d(FPURegister fd, FPURegister fs) {
2923
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2924 2925 2926 2927 2928
  GenInstrRegister(COP1, D, f0, fs, fd, RSQRT_D);
}


void Assembler::recip_d(FPURegister fd, FPURegister fs) {
2929
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2930 2931 2932 2933 2934
  GenInstrRegister(COP1, D, f0, fs, fd, RECIP_D);
}


void Assembler::recip_s(FPURegister fd, FPURegister fs) {
2935
  DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2936 2937 2938 2939
  GenInstrRegister(COP1, S, f0, fs, fd, RECIP_S);
}


2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951
// Conversions.

void Assembler::cvt_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, CVT_W_S);
}


void Assembler::cvt_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, CVT_W_D);
}


2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991
void Assembler::trunc_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_W_S);
}


void Assembler::trunc_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_W_D);
}


void Assembler::round_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, ROUND_W_S);
}


void Assembler::round_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, ROUND_W_D);
}


void Assembler::floor_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_W_S);
}


void Assembler::floor_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_W_D);
}


void Assembler::ceil_w_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S);
}


void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D);
}


2992 2993 2994 2995 2996
void Assembler::rint_s(FPURegister fd, FPURegister fs) { rint(S, fd, fs); }


void Assembler::rint(SecondaryField fmt, FPURegister fd, FPURegister fs) {
  DCHECK(IsMipsArchVariant(kMips32r6));
2997
  DCHECK((fmt == D) || (fmt == S));
2998 2999 3000 3001 3002 3003 3004
  GenInstrRegister(COP1, fmt, f0, fs, fd, RINT);
}


void Assembler::rint_d(FPURegister fd, FPURegister fs) { rint(D, fd, fs); }


3005
void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {
3006 3007
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3008 3009 3010 3011 3012
  GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);
}


void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {
3013 3014
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3015 3016 3017 3018
  GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);
}


3019
void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {
3020 3021
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3022 3023 3024 3025 3026
  GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);
}


void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {
3027 3028
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3029 3030 3031 3032 3033
  GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);
}


void Assembler::round_l_s(FPURegister fd, FPURegister fs) {
3034 3035
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3036 3037 3038 3039 3040
  GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S);
}


void Assembler::round_l_d(FPURegister fd, FPURegister fs) {
3041 3042
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3043 3044 3045 3046 3047
  GenInstrRegister(COP1, D, f0, fs, fd, ROUND_L_D);
}


void Assembler::floor_l_s(FPURegister fd, FPURegister fs) {
3048 3049
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3050 3051 3052 3053 3054
  GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_L_S);
}


void Assembler::floor_l_d(FPURegister fd, FPURegister fs) {
3055 3056
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3057 3058 3059 3060 3061
  GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_L_D);
}


void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) {
3062 3063
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3064 3065 3066 3067 3068
  GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S);
}


void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) {
3069 3070
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3071 3072 3073 3074
  GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D);
}


3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086
void Assembler::class_s(FPURegister fd, FPURegister fs) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, S, f0, fs, fd, CLASS_S);
}


void Assembler::class_d(FPURegister fd, FPURegister fs) {
  DCHECK(IsMipsArchVariant(kMips32r6));
  GenInstrRegister(COP1, D, f0, fs, fd, CLASS_D);
}


3087 3088
void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister fs,
                    FPURegister ft) {
3089 3090 3091 3092 3093 3094
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MIN);
}


3095 3096
void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister fs,
                     FPURegister ft) {
3097 3098 3099 3100 3101 3102
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MINA);
}


3103 3104
void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister fs,
                    FPURegister ft) {
3105 3106 3107 3108 3109 3110
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MAX);
}


3111 3112
void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister fs,
                     FPURegister ft) {
3113 3114 3115 3116 3117 3118
  DCHECK(IsMipsArchVariant(kMips32r6));
  DCHECK((fmt == D) || (fmt == S));
  GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA);
}


3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158
void Assembler::min_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  min(S, fd, fs, ft);
}


void Assembler::min_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  min(D, fd, fs, ft);
}


void Assembler::max_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  max(S, fd, fs, ft);
}


void Assembler::max_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  max(D, fd, fs, ft);
}


void Assembler::mina_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  mina(S, fd, fs, ft);
}


void Assembler::mina_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  mina(D, fd, fs, ft);
}


void Assembler::maxa_s(FPURegister fd, FPURegister fs, FPURegister ft) {
  maxa(S, fd, fs, ft);
}


void Assembler::maxa_d(FPURegister fd, FPURegister fs, FPURegister ft) {
  maxa(D, fd, fs, ft);
}


3159 3160 3161 3162 3163 3164
void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W);
}


void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {
3165 3166
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181
  GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);
}


void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D);
}


void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W);
}


void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {
3182 3183
  DCHECK((IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) &&
         IsFp64Mode());
3184 3185 3186 3187 3188 3189 3190 3191 3192
  GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);
}


void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) {
  GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S);
}


3193 3194 3195 3196
// Conditions for >= MIPSr6.
void Assembler::cmp(FPUCondition cond, SecondaryField fmt,
    FPURegister fd, FPURegister fs, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
3197
  DCHECK_EQ(fmt & ~(31 << kRsShift), 0);
3198 3199 3200 3201 3202 3203
  Instr instr = COP1 | fmt | ft.code() << kFtShift |
      fs.code() << kFsShift | fd.code() << kFdShift | (0 << 5) | cond;
  emit(instr);
}


3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214
void Assembler::cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs,
                      FPURegister ft) {
  cmp(cond, W, fd, fs, ft);
}

void Assembler::cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs,
                      FPURegister ft) {
  cmp(cond, L, fd, fs, ft);
}


3215 3216
void Assembler::bc1eqz(int16_t offset, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
3217
  BlockTrampolinePoolScope block_trampoline_pool(this);
3218
  Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask);
3219 3220
  emit(instr);
  BlockTrampolinePoolFor(1);  // For associated delay slot.
3221 3222 3223 3224 3225
}


void Assembler::bc1nez(int16_t offset, FPURegister ft) {
  DCHECK(IsMipsArchVariant(kMips32r6));
3226
  BlockTrampolinePoolScope block_trampoline_pool(this);
3227
  Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask);
3228 3229
  emit(instr);
  BlockTrampolinePoolFor(1);  // For associated delay slot.
3230 3231 3232 3233
}


// Conditions for < MIPSr6.
3234
void Assembler::c(FPUCondition cond, SecondaryField fmt,
3235
    FPURegister fs, FPURegister ft, uint16_t cc) {
3236
  DCHECK(is_uint3(cc));
3237
  DCHECK(fmt == S || fmt == D);
3238
  DCHECK_EQ(fmt & ~(31 << kRsShift), 0);
3239 3240 3241 3242 3243 3244
  Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift
      | cc << 8 | 3 << 4 | cond;
  emit(instr);
}


3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256
void Assembler::c_s(FPUCondition cond, FPURegister fs, FPURegister ft,
                    uint16_t cc) {
  c(cond, S, fs, ft, cc);
}


void Assembler::c_d(FPUCondition cond, FPURegister fs, FPURegister ft,
                    uint16_t cc) {
  c(cond, D, fs, ft, cc);
}


3257 3258
void Assembler::fcmp(FPURegister src1, const double src2,
      FPUCondition cond) {
3259
  DCHECK_EQ(src2, 0.0);
3260 3261 3262 3263 3264 3265
  mtc1(zero_reg, f14);
  cvt_d_w(f14, f14);
  c(cond, D, src1, f14, 0);
}


3266
void Assembler::bc1f(int16_t offset, uint16_t cc) {
3267
  BlockTrampolinePoolScope block_trampoline_pool(this);
3268
  DCHECK(is_uint3(cc));
3269 3270
  Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);
  emit(instr);
3271
  BlockTrampolinePoolFor(1);  // For associated delay slot.
3272 3273 3274 3275
}


void Assembler::bc1t(int16_t offset, uint16_t cc) {
3276
  BlockTrampolinePoolScope block_trampoline_pool(this);
3277
  DCHECK(is_uint3(cc));
3278 3279
  Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);
  emit(instr);
3280
  BlockTrampolinePoolFor(1);  // For associated delay slot.
3281 3282
}

3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314
// ---------- MSA instructions ------------
#define MSA_BRANCH_LIST(V) \
  V(bz_v, BZ_V)            \
  V(bz_b, BZ_B)            \
  V(bz_h, BZ_H)            \
  V(bz_w, BZ_W)            \
  V(bz_d, BZ_D)            \
  V(bnz_v, BNZ_V)          \
  V(bnz_b, BNZ_B)          \
  V(bnz_h, BNZ_H)          \
  V(bnz_w, BNZ_W)          \
  V(bnz_d, BNZ_D)

#define MSA_BRANCH(name, opcode)                         \
  void Assembler::name(MSARegister wt, int16_t offset) { \
    GenInstrMsaBranch(opcode, wt, offset);               \
  }

MSA_BRANCH_LIST(MSA_BRANCH)
#undef MSA_BRANCH
#undef MSA_BRANCH_LIST

#define MSA_LD_ST_LIST(V) \
  V(ld_b, LD_B)           \
  V(ld_h, LD_H)           \
  V(ld_w, LD_W)           \
  V(ld_d, LD_D)           \
  V(st_b, ST_B)           \
  V(st_h, ST_H)           \
  V(st_w, ST_W)           \
  V(st_d, ST_D)

3315 3316 3317 3318 3319 3320 3321
#define MSA_LD_ST(name, opcode)                                  \
  void Assembler::name(MSARegister wd, const MemOperand& rs) {   \
    MemOperand source = rs;                                      \
    AdjustBaseAndOffset(source);                                 \
    if (is_int10(source.offset())) {                             \
      GenInstrMsaMI10(opcode, source.offset(), source.rm(), wd); \
    } else {                                                     \
3322 3323
      UseScratchRegisterScope temps(this);                       \
      Register scratch = temps.Acquire();                        \
3324
      DCHECK(rs.rm() != scratch);                                \
3325 3326
      addiu(scratch, source.rm(), source.offset());              \
      GenInstrMsaMI10(opcode, 0, scratch, wd);                   \
3327
    }                                                            \
3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786
  }

MSA_LD_ST_LIST(MSA_LD_ST)
#undef MSA_LD_ST
#undef MSA_BRANCH_LIST

#define MSA_I10_LIST(V) \
  V(ldi_b, I5_DF_b)     \
  V(ldi_h, I5_DF_h)     \
  V(ldi_w, I5_DF_w)     \
  V(ldi_d, I5_DF_d)

#define MSA_I10(name, format)                           \
  void Assembler::name(MSARegister wd, int32_t imm10) { \
    GenInstrMsaI10(LDI, format, imm10, wd);             \
  }
MSA_I10_LIST(MSA_I10)
#undef MSA_I10
#undef MSA_I10_LIST

#define MSA_I5_LIST(V) \
  V(addvi, ADDVI)      \
  V(subvi, SUBVI)      \
  V(maxi_s, MAXI_S)    \
  V(maxi_u, MAXI_U)    \
  V(mini_s, MINI_S)    \
  V(mini_u, MINI_U)    \
  V(ceqi, CEQI)        \
  V(clti_s, CLTI_S)    \
  V(clti_u, CLTI_U)    \
  V(clei_s, CLEI_S)    \
  V(clei_u, CLEI_U)

#define MSA_I5_FORMAT(name, opcode, format)                       \
  void Assembler::name##_##format(MSARegister wd, MSARegister ws, \
                                  uint32_t imm5) {                \
    GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd);          \
  }

#define MSA_I5(name, opcode)     \
  MSA_I5_FORMAT(name, opcode, b) \
  MSA_I5_FORMAT(name, opcode, h) \
  MSA_I5_FORMAT(name, opcode, w) \
  MSA_I5_FORMAT(name, opcode, d)

MSA_I5_LIST(MSA_I5)
#undef MSA_I5
#undef MSA_I5_FORMAT
#undef MSA_I5_LIST

#define MSA_I8_LIST(V) \
  V(andi_b, ANDI_B)    \
  V(ori_b, ORI_B)      \
  V(nori_b, NORI_B)    \
  V(xori_b, XORI_B)    \
  V(bmnzi_b, BMNZI_B)  \
  V(bmzi_b, BMZI_B)    \
  V(bseli_b, BSELI_B)  \
  V(shf_b, SHF_B)      \
  V(shf_h, SHF_H)      \
  V(shf_w, SHF_W)

#define MSA_I8(name, opcode)                                            \
  void Assembler::name(MSARegister wd, MSARegister ws, uint32_t imm8) { \
    GenInstrMsaI8(opcode, imm8, ws, wd);                                \
  }

MSA_I8_LIST(MSA_I8)
#undef MSA_I8
#undef MSA_I8_LIST

#define MSA_VEC_LIST(V) \
  V(and_v, AND_V)       \
  V(or_v, OR_V)         \
  V(nor_v, NOR_V)       \
  V(xor_v, XOR_V)       \
  V(bmnz_v, BMNZ_V)     \
  V(bmz_v, BMZ_V)       \
  V(bsel_v, BSEL_V)

#define MSA_VEC(name, opcode)                                            \
  void Assembler::name(MSARegister wd, MSARegister ws, MSARegister wt) { \
    GenInstrMsaVec(opcode, wt, ws, wd);                                  \
  }

MSA_VEC_LIST(MSA_VEC)
#undef MSA_VEC
#undef MSA_VEC_LIST

#define MSA_2R_LIST(V) \
  V(pcnt, PCNT)        \
  V(nloc, NLOC)        \
  V(nlzc, NLZC)

#define MSA_2R_FORMAT(name, opcode, format)                         \
  void Assembler::name##_##format(MSARegister wd, MSARegister ws) { \
    GenInstrMsa2R(opcode, MSA_2R_DF_##format, ws, wd);              \
  }

#define MSA_2R(name, opcode)     \
  MSA_2R_FORMAT(name, opcode, b) \
  MSA_2R_FORMAT(name, opcode, h) \
  MSA_2R_FORMAT(name, opcode, w) \
  MSA_2R_FORMAT(name, opcode, d)

MSA_2R_LIST(MSA_2R)
#undef MSA_2R
#undef MSA_2R_FORMAT
#undef MSA_2R_LIST

#define MSA_FILL(format)                                              \
  void Assembler::fill_##format(MSARegister wd, Register rs) {        \
    DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));     \
    DCHECK(rs.is_valid() && wd.is_valid());                           \
    Instr instr = MSA | MSA_2R_FORMAT | FILL | MSA_2R_DF_##format |   \
                  (rs.code() << kWsShift) | (wd.code() << kWdShift) | \
                  MSA_VEC_2R_2RF_MINOR;                               \
    emit(instr);                                                      \
  }

MSA_FILL(b)
MSA_FILL(h)
MSA_FILL(w)
#undef MSA_FILL

#define MSA_2RF_LIST(V) \
  V(fclass, FCLASS)     \
  V(ftrunc_s, FTRUNC_S) \
  V(ftrunc_u, FTRUNC_U) \
  V(fsqrt, FSQRT)       \
  V(frsqrt, FRSQRT)     \
  V(frcp, FRCP)         \
  V(frint, FRINT)       \
  V(flog2, FLOG2)       \
  V(fexupl, FEXUPL)     \
  V(fexupr, FEXUPR)     \
  V(ffql, FFQL)         \
  V(ffqr, FFQR)         \
  V(ftint_s, FTINT_S)   \
  V(ftint_u, FTINT_U)   \
  V(ffint_s, FFINT_S)   \
  V(ffint_u, FFINT_U)

#define MSA_2RF_FORMAT(name, opcode, format)                        \
  void Assembler::name##_##format(MSARegister wd, MSARegister ws) { \
    GenInstrMsa2RF(opcode, MSA_2RF_DF_##format, ws, wd);            \
  }

#define MSA_2RF(name, opcode)     \
  MSA_2RF_FORMAT(name, opcode, w) \
  MSA_2RF_FORMAT(name, opcode, d)

MSA_2RF_LIST(MSA_2RF)
#undef MSA_2RF
#undef MSA_2RF_FORMAT
#undef MSA_2RF_LIST

#define MSA_3R_LIST(V)  \
  V(sll, SLL_MSA)       \
  V(sra, SRA_MSA)       \
  V(srl, SRL_MSA)       \
  V(bclr, BCLR)         \
  V(bset, BSET)         \
  V(bneg, BNEG)         \
  V(binsl, BINSL)       \
  V(binsr, BINSR)       \
  V(addv, ADDV)         \
  V(subv, SUBV)         \
  V(max_s, MAX_S)       \
  V(max_u, MAX_U)       \
  V(min_s, MIN_S)       \
  V(min_u, MIN_U)       \
  V(max_a, MAX_A)       \
  V(min_a, MIN_A)       \
  V(ceq, CEQ)           \
  V(clt_s, CLT_S)       \
  V(clt_u, CLT_U)       \
  V(cle_s, CLE_S)       \
  V(cle_u, CLE_U)       \
  V(add_a, ADD_A)       \
  V(adds_a, ADDS_A)     \
  V(adds_s, ADDS_S)     \
  V(adds_u, ADDS_U)     \
  V(ave_s, AVE_S)       \
  V(ave_u, AVE_U)       \
  V(aver_s, AVER_S)     \
  V(aver_u, AVER_U)     \
  V(subs_s, SUBS_S)     \
  V(subs_u, SUBS_U)     \
  V(subsus_u, SUBSUS_U) \
  V(subsuu_s, SUBSUU_S) \
  V(asub_s, ASUB_S)     \
  V(asub_u, ASUB_U)     \
  V(mulv, MULV)         \
  V(maddv, MADDV)       \
  V(msubv, MSUBV)       \
  V(div_s, DIV_S_MSA)   \
  V(div_u, DIV_U)       \
  V(mod_s, MOD_S)       \
  V(mod_u, MOD_U)       \
  V(dotp_s, DOTP_S)     \
  V(dotp_u, DOTP_U)     \
  V(dpadd_s, DPADD_S)   \
  V(dpadd_u, DPADD_U)   \
  V(dpsub_s, DPSUB_S)   \
  V(dpsub_u, DPSUB_U)   \
  V(pckev, PCKEV)       \
  V(pckod, PCKOD)       \
  V(ilvl, ILVL)         \
  V(ilvr, ILVR)         \
  V(ilvev, ILVEV)       \
  V(ilvod, ILVOD)       \
  V(vshf, VSHF)         \
  V(srar, SRAR)         \
  V(srlr, SRLR)         \
  V(hadd_s, HADD_S)     \
  V(hadd_u, HADD_U)     \
  V(hsub_s, HSUB_S)     \
  V(hsub_u, HSUB_U)

#define MSA_3R_FORMAT(name, opcode, format)                             \
  void Assembler::name##_##format(MSARegister wd, MSARegister ws,       \
                                  MSARegister wt) {                     \
    GenInstrMsa3R<MSARegister>(opcode, MSA_3R_DF_##format, wt, ws, wd); \
  }

#define MSA_3R_FORMAT_SLD_SPLAT(name, opcode, format)                \
  void Assembler::name##_##format(MSARegister wd, MSARegister ws,    \
                                  Register rt) {                     \
    GenInstrMsa3R<Register>(opcode, MSA_3R_DF_##format, rt, ws, wd); \
  }

#define MSA_3R(name, opcode)     \
  MSA_3R_FORMAT(name, opcode, b) \
  MSA_3R_FORMAT(name, opcode, h) \
  MSA_3R_FORMAT(name, opcode, w) \
  MSA_3R_FORMAT(name, opcode, d)

#define MSA_3R_SLD_SPLAT(name, opcode)     \
  MSA_3R_FORMAT_SLD_SPLAT(name, opcode, b) \
  MSA_3R_FORMAT_SLD_SPLAT(name, opcode, h) \
  MSA_3R_FORMAT_SLD_SPLAT(name, opcode, w) \
  MSA_3R_FORMAT_SLD_SPLAT(name, opcode, d)

MSA_3R_LIST(MSA_3R)
MSA_3R_SLD_SPLAT(sld, SLD)
MSA_3R_SLD_SPLAT(splat, SPLAT)

#undef MSA_3R
#undef MSA_3R_FORMAT
#undef MSA_3R_FORMAT_SLD_SPLAT
#undef MSA_3R_SLD_SPLAT
#undef MSA_3R_LIST

#define MSA_3RF_LIST1(V) \
  V(fcaf, FCAF)          \
  V(fcun, FCUN)          \
  V(fceq, FCEQ)          \
  V(fcueq, FCUEQ)        \
  V(fclt, FCLT)          \
  V(fcult, FCULT)        \
  V(fcle, FCLE)          \
  V(fcule, FCULE)        \
  V(fsaf, FSAF)          \
  V(fsun, FSUN)          \
  V(fseq, FSEQ)          \
  V(fsueq, FSUEQ)        \
  V(fslt, FSLT)          \
  V(fsult, FSULT)        \
  V(fsle, FSLE)          \
  V(fsule, FSULE)        \
  V(fadd, FADD)          \
  V(fsub, FSUB)          \
  V(fmul, FMUL)          \
  V(fdiv, FDIV)          \
  V(fmadd, FMADD)        \
  V(fmsub, FMSUB)        \
  V(fexp2, FEXP2)        \
  V(fmin, FMIN)          \
  V(fmin_a, FMIN_A)      \
  V(fmax, FMAX)          \
  V(fmax_a, FMAX_A)      \
  V(fcor, FCOR)          \
  V(fcune, FCUNE)        \
  V(fcne, FCNE)          \
  V(fsor, FSOR)          \
  V(fsune, FSUNE)        \
  V(fsne, FSNE)

#define MSA_3RF_LIST2(V) \
  V(fexdo, FEXDO)        \
  V(ftq, FTQ)            \
  V(mul_q, MUL_Q)        \
  V(madd_q, MADD_Q)      \
  V(msub_q, MSUB_Q)      \
  V(mulr_q, MULR_Q)      \
  V(maddr_q, MADDR_Q)    \
  V(msubr_q, MSUBR_Q)

#define MSA_3RF_FORMAT(name, opcode, df, df_c)                \
  void Assembler::name##_##df(MSARegister wd, MSARegister ws, \
                              MSARegister wt) {               \
    GenInstrMsa3RF(opcode, df_c, wt, ws, wd);                 \
  }

#define MSA_3RF_1(name, opcode)      \
  MSA_3RF_FORMAT(name, opcode, w, 0) \
  MSA_3RF_FORMAT(name, opcode, d, 1)

#define MSA_3RF_2(name, opcode)      \
  MSA_3RF_FORMAT(name, opcode, h, 0) \
  MSA_3RF_FORMAT(name, opcode, w, 1)

MSA_3RF_LIST1(MSA_3RF_1)
MSA_3RF_LIST2(MSA_3RF_2)
#undef MSA_3RF_1
#undef MSA_3RF_2
#undef MSA_3RF_FORMAT
#undef MSA_3RF_LIST1
#undef MSA_3RF_LIST2

void Assembler::sldi_b(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_B, n, ws, wd);
}

void Assembler::sldi_h(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_H, n, ws, wd);
}

void Assembler::sldi_w(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_W, n, ws, wd);
}

void Assembler::sldi_d(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SLDI, ELM_DF_D, n, ws, wd);
}

void Assembler::splati_b(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_B, n, ws, wd);
}

void Assembler::splati_h(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_H, n, ws, wd);
}

void Assembler::splati_w(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_W, n, ws, wd);
}

void Assembler::splati_d(MSARegister wd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<MSARegister, MSARegister>(SPLATI, ELM_DF_D, n, ws, wd);
}

void Assembler::copy_s_b(Register rd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_B, n, ws, rd);
}

void Assembler::copy_s_h(Register rd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_H, n, ws, rd);
}

void Assembler::copy_s_w(Register rd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<Register, MSARegister>(COPY_S, ELM_DF_W, n, ws, rd);
}

void Assembler::copy_u_b(Register rd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_B, n, ws, rd);
}

void Assembler::copy_u_h(Register rd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_H, n, ws, rd);
}

void Assembler::copy_u_w(Register rd, MSARegister ws, uint32_t n) {
  GenInstrMsaElm<Register, MSARegister>(COPY_U, ELM_DF_W, n, ws, rd);
}

void Assembler::insert_b(MSARegister wd, uint32_t n, Register rs) {
  GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_B, n, rs, wd);
}

void Assembler::insert_h(MSARegister wd, uint32_t n, Register rs) {
  GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_H, n, rs, wd);
}

void Assembler::insert_w(MSARegister wd, uint32_t n, Register rs) {
  GenInstrMsaElm<MSARegister, Register>(INSERT, ELM_DF_W, n, rs, wd);
}

void Assembler::insve_b(MSARegister wd, uint32_t n, MSARegister ws) {
  GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_B, n, ws, wd);
}

void Assembler::insve_h(MSARegister wd, uint32_t n, MSARegister ws) {
  GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_H, n, ws, wd);
}

void Assembler::insve_w(MSARegister wd, uint32_t n, MSARegister ws) {
  GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_W, n, ws, wd);
}

void Assembler::insve_d(MSARegister wd, uint32_t n, MSARegister ws) {
  GenInstrMsaElm<MSARegister, MSARegister>(INSVE, ELM_DF_D, n, ws, wd);
}

void Assembler::move_v(MSARegister wd, MSARegister ws) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(ws.is_valid() && wd.is_valid());
  Instr instr = MSA | MOVE_V | (ws.code() << kWsShift) |
                (wd.code() << kWdShift) | MSA_ELM_MINOR;
  emit(instr);
}

void Assembler::ctcmsa(MSAControlRegister cd, Register rs) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(cd.is_valid() && rs.is_valid());
  Instr instr = MSA | CTCMSA | (rs.code() << kWsShift) |
                (cd.code() << kWdShift) | MSA_ELM_MINOR;
  emit(instr);
}

void Assembler::cfcmsa(Register rd, MSAControlRegister cs) {
  DCHECK(IsMipsArchVariant(kMips32r6) && IsEnabled(MIPS_SIMD));
  DCHECK(rd.is_valid() && cs.is_valid());
  Instr instr = MSA | CFCMSA | (cs.code() << kWsShift) |
                (rd.code() << kWdShift) | MSA_ELM_MINOR;
  emit(instr);
}

#define MSA_BIT_LIST(V) \
  V(slli, SLLI)         \
  V(srai, SRAI)         \
  V(srli, SRLI)         \
  V(bclri, BCLRI)       \
  V(bseti, BSETI)       \
  V(bnegi, BNEGI)       \
  V(binsli, BINSLI)     \
  V(binsri, BINSRI)     \
  V(sat_s, SAT_S)       \
  V(sat_u, SAT_U)       \
  V(srari, SRARI)       \
  V(srlri, SRLRI)

#define MSA_BIT_FORMAT(name, opcode, format)                      \
  void Assembler::name##_##format(MSARegister wd, MSARegister ws, \
                                  uint32_t m) {                   \
    GenInstrMsaBit(opcode, BIT_DF_##format, m, ws, wd);           \
  }

#define MSA_BIT(name, opcode)     \
  MSA_BIT_FORMAT(name, opcode, b) \
  MSA_BIT_FORMAT(name, opcode, h) \
  MSA_BIT_FORMAT(name, opcode, w) \
  MSA_BIT_FORMAT(name, opcode, d)

MSA_BIT_LIST(MSA_BIT)
#undef MSA_BIT
#undef MSA_BIT_FORMAT
#undef MSA_BIT_LIST
3787

3788
int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, Address pc,
3789
                                         intptr_t pc_delta) {
3790
  Instr instr = instr_at(pc);
3791

3792
  if (RelocInfo::IsInternalReference(rmode)) {
3793
    int32_t* p = reinterpret_cast<int32_t*>(pc);
3794
    if (*p == 0) {
3795
      return 0;  // Number of instructions patched.
3796
    }
3797 3798
    *p += pc_delta;
    return 1;  // Number of instructions patched.
3799 3800 3801
  } else {
    DCHECK(RelocInfo::IsInternalReferenceEncoded(rmode));
    if (IsLui(instr)) {
3802 3803
      Instr instr1 = instr_at(pc + 0 * kInstrSize);
      Instr instr2 = instr_at(pc + 1 * kInstrSize);
3804 3805 3806 3807 3808
      DCHECK(IsOri(instr2) || IsJicOrJialc(instr2));
      int32_t imm;
      if (IsJicOrJialc(instr2)) {
        imm = CreateTargetAddress(instr1, instr2);
      } else {
3809
        imm = GetLuiOriImmediate(instr1, instr2);
3810 3811
      }

3812 3813 3814 3815
      if (imm == kEndOfJumpChain) {
        return 0;  // Number of instructions patched.
      }
      imm += pc_delta;
3816
      DCHECK_EQ(imm & 3, 0);
3817 3818 3819 3820 3821 3822
      instr1 &= ~kImm16Mask;
      instr2 &= ~kImm16Mask;

      if (IsJicOrJialc(instr2)) {
        uint32_t lui_offset_u, jic_offset_u;
        Assembler::UnpackTargetAddressUnsigned(imm, lui_offset_u, jic_offset_u);
3823 3824
        instr_at_put(pc + 0 * kInstrSize, instr1 | lui_offset_u);
        instr_at_put(pc + 1 * kInstrSize, instr2 | jic_offset_u);
3825
      } else {
3826 3827
        PatchLuiOriImmediate(pc, imm, instr1, 0 * kInstrSize, instr2,
                             1 * kInstrSize);
3828
      }
3829 3830 3831 3832
      return 2;  // Number of instructions patched.
    } else {
      UNREACHABLE();
    }
3833 3834 3835
  }
}

3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868
void Assembler::RelocateRelativeReference(RelocInfo::Mode rmode, Address pc,
                                          intptr_t pc_delta) {
  Instr instr = instr_at(pc);

  DCHECK(RelocInfo::IsRelativeCodeTarget(rmode));
  if (IsLui(instr)) {
    Instr instr1 = instr_at(pc + 0 * kInstrSize);
    Instr instr2 = instr_at(pc + 1 * kInstrSize);
    Instr instr3 = instr_at(pc + 2 * kInstrSize);
    int32_t imm;
    Address ori_offset;
    if (IsNal(instr2)) {
      instr2 = instr3;
      ori_offset = 2 * kInstrSize;
    } else {
      ori_offset = 1 * kInstrSize;
    }
    DCHECK(IsOri(instr2));
    imm = GetLuiOriImmediate(instr1, instr2);
    instr1 &= ~kImm16Mask;
    instr2 &= ~kImm16Mask;

    if (imm == kEndOfJumpChain) {
      return;
    }
    imm += pc_delta;
    DCHECK_EQ(imm & 3, 0);
    PatchLuiOriImmediate(pc, imm, instr1, 0 * kInstrSize, instr2, ori_offset);
    return;
  } else {
    UNREACHABLE();
  }
}
3869

3870 3871
void Assembler::GrowBuffer() {
  // Compute new buffer size.
3872 3873
  int old_size = buffer_->size();
  int new_size = std::min(2 * old_size, old_size + 1 * MB);
3874 3875 3876

  // Some internal data structures overflow for very large buffers,
  // they must ensure that kMaximalBufferSize is not too large.
3877
  if (new_size > kMaximalBufferSize) {
3878
    V8::FatalProcessOutOfMemory(nullptr, "Assembler::GrowBuffer");
3879
  }
3880

3881
  // Set up new buffer.
3882 3883 3884
  std::unique_ptr<AssemblerBuffer> new_buffer = buffer_->Grow(new_size);
  DCHECK_EQ(new_size, new_buffer->size());
  byte* new_start = new_buffer->start();
3885 3886

  // Copy the data.
3887 3888 3889 3890
  int pc_delta = new_start - buffer_start_;
  int rc_delta = (new_start + new_size) - (buffer_start_ + old_size);
  size_t reloc_size = (buffer_start_ + old_size) - reloc_info_writer.pos();
  MemMove(new_start, buffer_start_, pc_offset());
3891
  MemMove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(),
3892
          reloc_size);
3893 3894

  // Switch buffers.
3895 3896
  buffer_ = std::move(new_buffer);
  buffer_start_ = new_start;
3897 3898 3899 3900
  pc_ += pc_delta;
  reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
                               reloc_info_writer.last_pc() + pc_delta);

3901
  // Relocate runtime entries.
3902 3903 3904
  Vector<byte> instructions{buffer_start_, pc_offset()};
  Vector<const byte> reloc_info{reloc_info_writer.pos(), reloc_size};
  for (RelocIterator it(instructions, reloc_info, 0); !it.done(); it.next()) {
3905
    RelocInfo::Mode rmode = it.rinfo()->rmode();
3906 3907
    if (rmode == RelocInfo::INTERNAL_REFERENCE_ENCODED ||
        rmode == RelocInfo::INTERNAL_REFERENCE) {
3908
      RelocateInternalReference(rmode, it.rinfo()->pc(), pc_delta);
3909 3910
    }
  }
3911
  DCHECK(!overflow());
3912 3913 3914
}


3915
void Assembler::db(uint8_t data) {
3916 3917
  CheckForEmitInForbiddenSlot();
  EmitHelper(data);
3918 3919 3920 3921
}


void Assembler::dd(uint32_t data) {
3922 3923
  CheckForEmitInForbiddenSlot();
  EmitHelper(data);
3924 3925 3926
}


3927
void Assembler::dq(uint64_t data) {
3928 3929
  CheckForEmitInForbiddenSlot();
  EmitHelper(data);
3930 3931 3932
}


3933
void Assembler::dd(Label* label) {
3934
  uint32_t data;
3935
  CheckForEmitInForbiddenSlot();
3936
  if (label->is_bound()) {
3937
    data = reinterpret_cast<uint32_t>(buffer_start_ + label->pos());
3938
  } else {
3939
    data = jump_address(label);
3940
    unbound_labels_count_++;
3941
    internal_reference_positions_.insert(label->pos());
3942
  }
3943 3944
  RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
  EmitHelper(data);
3945 3946 3947
}


3948
void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
3949
  if (!ShouldRecordRelocInfo(rmode)) return;
3950
  // We do not try to reuse pool constants.
3951
  RelocInfo rinfo(reinterpret_cast<Address>(pc_), rmode, data, Code());
3952 3953
  DCHECK_GE(buffer_space(), kMaxRelocSize);  // Too late to grow buffer here.
  reloc_info_writer.Write(&rinfo);
3954 3955
}

3956
void Assembler::BlockTrampolinePoolFor(int instructions) {
3957
  CheckTrampolinePoolQuick(instructions);
3958 3959 3960 3961
  BlockTrampolinePoolBefore(pc_offset() + instructions * kInstrSize);
}


3962
void Assembler::CheckTrampolinePool() {
3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979
  // Some small sequences of instructions must not be broken up by the
  // insertion of a trampoline pool; such sequences are protected by setting
  // either trampoline_pool_blocked_nesting_ or no_trampoline_pool_before_,
  // which are both checked here. Also, recursive calls to CheckTrampolinePool
  // are blocked by trampoline_pool_blocked_nesting_.
  if ((trampoline_pool_blocked_nesting_ > 0) ||
      (pc_offset() < no_trampoline_pool_before_)) {
    // Emission is currently blocked; make sure we try again as soon as
    // possible.
    if (trampoline_pool_blocked_nesting_ > 0) {
      next_buffer_check_ = pc_offset() + kInstrSize;
    } else {
      next_buffer_check_ = no_trampoline_pool_before_;
    }
    return;
  }

3980
  DCHECK(!trampoline_emitted_);
3981
  DCHECK_GE(unbound_labels_count_, 0);
3982 3983 3984 3985
  if (unbound_labels_count_ > 0) {
    // First we emit jump (2 instructions), then we emit trampoline pool.
    { BlockTrampolinePoolScope block_trampoline_pool(this);
      Label after_pool;
3986 3987 3988 3989 3990
      if (IsMipsArchVariant(kMips32r6)) {
        bc(&after_pool);
      } else {
        b(&after_pool);
      }
3991
      nop();
3992 3993

      int pool_start = pc_offset();
3994 3995 3996 3997 3998 3999
      for (int i = 0; i < unbound_labels_count_; i++) {
        {
          if (IsMipsArchVariant(kMips32r6)) {
            bc(&after_pool);
            nop();
          } else {
4000 4001
            GenPCRelativeJump(t8, t9, 0, RelocInfo::NONE,
                              BranchDelaySlot::PROTECT);
4002
          }
4003 4004 4005 4006 4007 4008 4009 4010 4011
        }
      }
      bind(&after_pool);
      trampoline_ = Trampoline(pool_start, unbound_labels_count_);

      trampoline_emitted_ = true;
      // As we are only going to emit trampoline once, we need to prevent any
      // further emission.
      next_buffer_check_ = kMaxInt;
4012
    }
4013 4014 4015 4016 4017
  } else {
    // Number of branches to unbound label at this point is zero, so we can
    // move next buffer check to maximum.
    next_buffer_check_ = pc_offset() +
        kMaxBranchOffset - kTrampolineSlotsSize * 16;
4018 4019 4020 4021 4022
  }
  return;
}


4023 4024 4025
Address Assembler::target_address_at(Address pc) {
  Instr instr1 = instr_at(pc);
  Instr instr2 = instr_at(pc + kInstrSize);
4026
  Instr instr3 = instr_at(pc + 2 * kInstrSize);
4027 4028 4029 4030
  // Interpret 2 instructions generated by li (lui/ori) or optimized pairs
  // lui/jic, aui/jic or lui/jialc.
  if (IsLui(instr1)) {
    if (IsOri(instr2)) {
4031
      Address target_address;
4032
      // Assemble the 32 bit value.
4033 4034 4035 4036 4037
      target_address = GetLuiOriImmediate(instr1, instr2);
      if (IsAddu(instr3, t9, ra, t9)) {
        target_address += pc + kRelativeJumpForBuiltinsOffset;
      }
      return target_address;
4038 4039
    } else if (IsJicOrJialc(instr2)) {
      // Assemble the 32 bit value.
4040
      return static_cast<Address>(CreateTargetAddress(instr1, instr2));
4041 4042 4043 4044 4045
    } else if (IsNal(instr2)) {
      DCHECK(IsOri(instr3));
      Address target_address;
      target_address = GetLuiOriImmediate(instr1, instr3);
      return target_address + pc + kRelativeCallForBuiltinsOffset;
4046
    }
4047 4048
  }

4049
  // We should never get here, force a bad address if we do.
4050 4051 4052 4053
  UNREACHABLE();
}


4054 4055 4056 4057
// MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32
// qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap
// snapshot generated on ia32, the resulting MIPS sNaN must be quieted.
// OS::nan_value() returns a qNaN.
4058
void Assembler::QuietNaN(HeapObject object) {
4059
  HeapNumber::cast(object)->set_value(std::numeric_limits<double>::quiet_NaN());
4060 4061
}

4062 4063 4064
// On Mips, a target address is stored in a lui/ori instruction pair, each
// of which load 16 bits of the 32-bit address to a register.
// Patching the address must replace both instr, and flush the i-cache.
4065 4066
// On r6, target address is stored in a lui/jic pair, and both instr have to be
// patched.
4067
void Assembler::set_target_value_at(Address pc, uint32_t target,
4068
                                    ICacheFlushMode icache_flush_mode) {
4069
  Instr instr1 = instr_at(pc);
4070
  Instr instr2 = instr_at(pc + kInstrSize);
4071

4072
#ifdef DEBUG
4073
  // Check we have the result from a li macro-instruction, using instr pair.
4074 4075
  DCHECK(IsLui(instr1) &&
         (IsOri(instr2) || IsJicOrJialc(instr2) || IsNal(instr2)));
4076 4077
#endif

4078 4079 4080
  if (IsJicOrJialc(instr2)) {
    // Must use 2 instructions to insure patchable code => use lui and jic
    uint32_t lui_offset, jic_offset;
4081
    Assembler::UnpackTargetAddressUnsigned(target, lui_offset, jic_offset);
4082

4083 4084
    instr1 &= ~kImm16Mask;
    instr2 &= ~kImm16Mask;
4085

4086 4087
    instr1 |= lui_offset;
    instr2 |= jic_offset;
4088

4089 4090
    instr_at_put(pc, instr1);
    instr_at_put(pc + kInstrSize, instr2);
4091
  } else {
4092 4093 4094 4095 4096 4097 4098 4099
    Instr instr3 = instr_at(pc + 2 * kInstrSize);
    // If we are using relative calls/jumps for builtins.
    if (IsNal(instr2)) {
      target -= pc + kRelativeCallForBuiltinsOffset;
    }
    if (IsAddu(instr3, t9, ra, t9)) {
      target -= pc + kRelativeJumpForBuiltinsOffset;
    }
4100 4101 4102
    // Must use 2 instructions to insure patchable code => just use lui and ori.
    // lui rt, upper-16.
    // ori rt rt, lower-16.
4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113
    if (IsNal(instr2)) {
      instr1 &= ~kImm16Mask;
      instr3 &= ~kImm16Mask;
      PatchLuiOriImmediate(pc, target, instr1, 0 * kInstrSize, instr3,
                           2 * kInstrSize);
    } else {
      instr1 &= ~kImm16Mask;
      instr2 &= ~kImm16Mask;
      PatchLuiOriImmediate(pc, target, instr1, 0 * kInstrSize, instr2,
                           1 * kInstrSize);
    }
4114
  }
4115

4116
  if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
4117
    FlushInstructionCache(pc, 2 * sizeof(int32_t));
4118
  }
4119 4120
}

4121 4122 4123 4124 4125 4126 4127
void Assembler::GenPCRelativeJump(Register tf, Register ts, int32_t imm32,
                                  RelocInfo::Mode rmode,
                                  BranchDelaySlot bdslot) {
  // Order of these instructions is relied upon when patching them
  // or when changing imm32 that lui/ori pair loads.
  or_(tf, ra, zero_reg);
  nal();  // Relative place of nal instruction determines kLongBranchPCOffset.
4128 4129 4130
  if (!RelocInfo::IsNone(rmode)) {
    RecordRelocInfo(rmode);
  }
4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145
  lui(ts, (imm32 & kHiMask) >> kLuiShift);
  ori(ts, ts, (imm32 & kImm16Mask));
  addu(ts, ra, ts);
  if (bdslot == USE_DELAY_SLOT) {
    or_(ra, tf, zero_reg);
  }
  jr(ts);
  if (bdslot == PROTECT) {
    or_(ra, tf, zero_reg);
  }
}

void Assembler::GenPCRelativeJumpAndLink(Register t, int32_t imm32,
                                         RelocInfo::Mode rmode,
                                         BranchDelaySlot bdslot) {
4146 4147 4148
  if (!RelocInfo::IsNone(rmode)) {
    RecordRelocInfo(rmode);
  }
4149 4150 4151 4152 4153 4154 4155 4156 4157 4158
  // Order of these instructions is relied upon when patching them
  // or when changing imm32 that lui/ori pair loads.
  lui(t, (imm32 & kHiMask) >> kLuiShift);
  nal();  // Relative place of nal instruction determines kLongBranchPCOffset.
  ori(t, t, (imm32 & kImm16Mask));
  addu(t, ra, t);
  jalr(t);
  if (bdslot == PROTECT) nop();
}

4159 4160 4161 4162 4163 4164 4165 4166 4167
UseScratchRegisterScope::UseScratchRegisterScope(Assembler* assembler)
    : available_(assembler->GetScratchRegisterList()),
      old_available_(*available_) {}

UseScratchRegisterScope::~UseScratchRegisterScope() {
  *available_ = old_available_;
}

Register UseScratchRegisterScope::Acquire() {
4168 4169
  DCHECK_NOT_NULL(available_);
  DCHECK_NE(*available_, 0);
4170 4171 4172 4173 4174 4175 4176 4177
  int index = static_cast<int>(base::bits::CountTrailingZeros32(*available_));
  *available_ &= ~(1UL << index);

  return Register::from_code(index);
}

bool UseScratchRegisterScope::hasAvailable() const { return *available_ != 0; }

4178 4179
}  // namespace internal
}  // namespace v8
4180

4181
#endif  // V8_TARGET_ARCH_MIPS