MIPS[64] Optimization to LongBranchAndLink PIC

Also, since trampoline code is position independent now,
these builtins can be deleted from this list of Isolate dependent
builtins.

Bug: v8:7882
Change-Id: Ie65f739ebd3136993548e9737b22e7de0f09bf25
Reviewed-on: https://chromium-review.googlesource.com/1163513Reviewed-by: Ivica Bogosavljevic <ibogosavljevic@wavecomp.com>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Michael Stanton <mvstanton@chromium.org>
Commit-Queue: Ivica Bogosavljevic <ibogosavljevic@wavecomp.com>
Cr-Commit-Position: refs/heads/master@{#54983}

src/builtins/builtins.cc

@@ -324,22 +324,6 @@ bool Builtins::IsIsolateIndependent(int index) {
     //    of the builtin itself (and not just the trampoline).
     case kInterpreterEntryTrampoline:
       return false;
-#if V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_MIPS
-    // TODO(7882): The size of these builtins on MIP64 and MIPS32 is greater
-    // than 128KB, and this triggers generation of MIPS specific trampolines.
-    // Trampoline code is not PIC and therefore the builtin is not isolate
-    // independent.
-    case kKeyedLoadIC_Megamorphic:
-    case kKeyedStoreIC_Megamorphic:
-    case kObjectAssign:
-    case kObjectGetOwnPropertyDescriptor:
-    case kRegExpMatchFast:
-    case kRegExpReplace:
-    case kRegExpSplit:
-    case kRegExpStringIteratorPrototypeNext:
-    case kStoreIC_Uninitialized:
-      return false;
-#endif
     default:
       return true;
   }

src/mips/assembler-mips.cc

@@ -994,13 +994,27 @@ void Assembler::target_at_put(int32_t pos, int32_t target_pos,
       DCHECK(IsOri(instr_ori));
       int32_t imm = target_pos - (pos + Assembler::kLongBranchPCOffset);
       DCHECK_EQ(imm & 3, 0);
+      if (is_int16(imm + Assembler::kLongBranchPCOffset -
+                   Assembler::kBranchPCOffset)) {
+        // Optimize by converting to regular branch and link with 16-bit
+        // offset.
+        Instr instr_b = REGIMM | BGEZAL;  // Branch and link.
+        instr_b = SetBranchOffset(pos, target_pos, instr_b);
+        // Correct ra register to point to one instruction after jalr from
+        // TurboAssembler::BranchAndLinkLong.
+        Instr instr_a = ADDIU | ra.code() << kRsShift | ra.code() << kRtShift |
+                        kOptimizedBranchAndLinkLongReturnOffset;
+
+        instr_at_put(pos, instr_b);
+        instr_at_put(pos + 1 * kInstrSize, instr_a);
+      } else {
+        instr_lui &= ~kImm16Mask;
+        instr_ori &= ~kImm16Mask;
 
-      instr_lui &= ~kImm16Mask;
-      instr_ori &= ~kImm16Mask;
-
-      instr_at_put(pos + 0 * kInstrSize,
-                   instr_lui | ((imm >> 16) & kImm16Mask));
-      instr_at_put(pos + 2 * kInstrSize, instr_ori | (imm & kImm16Mask));
+        instr_at_put(pos + 0 * kInstrSize,
+                     instr_lui | ((imm >> kLuiShift) & kImm16Mask));
+        instr_at_put(pos + 2 * kInstrSize, instr_ori | (imm & kImm16Mask));
+      }
     } else {
       Instr instr1 = instr_at(pos + 0 * kInstrSize);
       Instr instr2 = instr_at(pos + 1 * kInstrSize);

src/mips/assembler-mips.h

@@ -615,12 +615,19 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   // branches
   static constexpr int kLongBranchPCOffset = 3 * kInstrSize;
 
+  // Adjust ra register in branch delay slot of bal instruction so to skip
+  // instructions not needed after optimization of PIC in
+  // TurboAssembler::BranchAndLink method.
+
+  static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 4 * kInstrSize;
+
   // Here we are patching the address in the LUI/ORI instruction pair.
   // These values are used in the serialization process and must be zero for
   // MIPS platform, as Code, Embedded Object or External-reference pointers
   // are split across two consecutive instructions and don't exist separately
   // in the code, so the serializer should not step forwards in memory after
   // a target is resolved and written.
+
   static constexpr int kSpecialTargetSize = 0;
 
   // Number of consecutive instructions used to store 32bit constant. This

src/mips64/assembler-mips64.cc

@@ -901,13 +901,27 @@ void Assembler::target_at_put(int pos, int target_pos, bool is_internal) {
       DCHECK(IsOri(instr_ori));
       int32_t imm = target_pos - (pos + Assembler::kLongBranchPCOffset);
       DCHECK_EQ(imm & 3, 0);
+      if (is_int16(imm + Assembler::kLongBranchPCOffset -
+                   Assembler::kBranchPCOffset)) {
+        // Optimize by converting to regular branch and link with 16-bit
+        // offset.
+        Instr instr_b = REGIMM | BGEZAL;  // Branch and link.
+        instr_b = SetBranchOffset(pos, target_pos, instr_b);
+        // Correct ra register to point to one instruction after jalr from
+        // TurboAssembler::BranchAndLinkLong.
+        Instr instr_a = DADDIU | ra.code() << kRsShift | ra.code() << kRtShift |
+                        kOptimizedBranchAndLinkLongReturnOffset;
+
+        instr_at_put(pos, instr_b);
+        instr_at_put(pos + 1 * kInstrSize, instr_a);
+      } else {
+        instr_lui &= ~kImm16Mask;
+        instr_ori &= ~kImm16Mask;
 
-      instr_lui &= ~kImm16Mask;
-      instr_ori &= ~kImm16Mask;
-
-      instr_at_put(pos + 0 * kInstrSize,
-                   instr_lui | ((imm >> kLuiShift) & kImm16Mask));
-      instr_at_put(pos + 2 * kInstrSize, instr_ori | (imm & kImm16Mask));
+        instr_at_put(pos + 0 * kInstrSize,
+                     instr_lui | ((imm >> kLuiShift) & kImm16Mask));
+        instr_at_put(pos + 2 * kInstrSize, instr_ori | (imm & kImm16Mask));
+      }
     } else {
       Instr instr_lui = instr_at(pos + 0 * kInstrSize);
       Instr instr_ori = instr_at(pos + 1 * kInstrSize);

src/mips64/assembler-mips64.h

@@ -625,6 +625,12 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   // branches
   static constexpr int kLongBranchPCOffset = 3 * kInstrSize;
 
+  // Adjust ra register in branch delay slot of bal instruction so to skip
+  // instructions not needed after optimization of PIC in
+  // TurboAssembler::BranchAndLink method.
+
+  static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 4 * kInstrSize;
+
   // Here we are patching the address in the LUI/ORI instruction pair.
   // These values are used in the serialization process and must be zero for
   // MIPS platform, as Code, Embedded Object or External-reference pointers

src/mips64/macro-assembler-mips64.cc

@@ -4291,7 +4291,7 @@ void TurboAssembler::BranchLong(Label* L, BranchDelaySlot bdslot) {
       (!L->is_bound() || is_near_r6(L))) {
     BranchShortHelperR6(0, L);
   } else {
-    // Generate position independent jong branch.
+    // Generate position independent long branch.
     BlockTrampolinePoolScope block_trampoline_pool(this);
     Label find_pc;
     int64_t imm64;
@@ -4317,6 +4317,7 @@ void TurboAssembler::BranchAndLinkLong(Label* L, BranchDelaySlot bdslot) {
       (!L->is_bound() || is_near_r6(L))) {
     BranchAndLinkShortHelperR6(0, L);
   } else {
+    // Generate position independent long branch and link.
     BlockTrampolinePoolScope block_trampoline_pool(this);
     Label find_pc;
     int64_t imm64;