disasm-mips.cc 51.2 KB
Newer Older
1
// Copyright 2012 the V8 project authors. All rights reserved.
2 3
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
4 5 6 7 8 9 10 11 12

// A Disassembler object is used to disassemble a block of code instruction by
// instruction. The default implementation of the NameConverter object can be
// overriden to modify register names or to do symbol lookup on addresses.
//
// The example below will disassemble a block of code and print it to stdout.
//
//   NameConverter converter;
//   Disassembler d(converter);
13
//   for (byte* pc = begin; pc < end;) {
14 15 16
//     v8::internal::EmbeddedVector<char, 256> buffer;
//     byte* prev_pc = pc;
//     pc += d.InstructionDecode(buffer, pc);
17 18 19 20 21 22 23 24 25 26
//     printf("%p    %08x      %s\n",
//            prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
//   }
//
// The Disassembler class also has a convenience method to disassemble a block
// of code into a FILE*, meaning that the above functionality could also be
// achieved by just calling Disassembler::Disassemble(stdout, begin, end);

#include <assert.h>
#include <stdarg.h>
27
#include <stdio.h>
28 29
#include <string.h>

30
#if V8_TARGET_ARCH_MIPS
31

32
#include "src/base/platform/platform.h"
33 34
#include "src/disasm.h"
#include "src/macro-assembler.h"
35
#include "src/mips/constants-mips.h"
36

37 38
namespace v8 {
namespace internal {
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

//------------------------------------------------------------------------------

// Decoder decodes and disassembles instructions into an output buffer.
// It uses the converter to convert register names and call destinations into
// more informative description.
class Decoder {
 public:
  Decoder(const disasm::NameConverter& converter,
          v8::internal::Vector<char> out_buffer)
    : converter_(converter),
      out_buffer_(out_buffer),
      out_buffer_pos_(0) {
    out_buffer_[out_buffer_pos_] = '\0';
  }

  ~Decoder() {}

  // Writes one disassembled instruction into 'buffer' (0-terminated).
  // Returns the length of the disassembled machine instruction in bytes.
59
  int InstructionDecode(byte* instruction);
60 61 62 63 64 65 66 67

 private:
  // Bottleneck functions to print into the out_buffer.
  void PrintChar(const char ch);
  void Print(const char* str);

  // Printing of common values.
  void PrintRegister(int reg);
68
  void PrintFPURegister(int freg);
69
  void PrintFPUStatusRegister(int freg);
70 71 72 73 74 75 76
  void PrintRs(Instruction* instr);
  void PrintRt(Instruction* instr);
  void PrintRd(Instruction* instr);
  void PrintFs(Instruction* instr);
  void PrintFt(Instruction* instr);
  void PrintFd(Instruction* instr);
  void PrintSa(Instruction* instr);
77
  void PrintLsaSa(Instruction* instr);
78
  void PrintSd(Instruction* instr);
79 80
  void PrintSs1(Instruction* instr);
  void PrintSs2(Instruction* instr);
81 82
  void PrintBc(Instruction* instr);
  void PrintCc(Instruction* instr);
83
  void PrintBp2(Instruction* instr);
84 85 86 87 88
  void PrintFunction(Instruction* instr);
  void PrintSecondaryField(Instruction* instr);
  void PrintUImm16(Instruction* instr);
  void PrintSImm16(Instruction* instr);
  void PrintXImm16(Instruction* instr);
89
  void PrintPCImm16(Instruction* instr, int delta_pc, int n_bits);
90 91 92 93
  void PrintXImm18(Instruction* instr);
  void PrintSImm18(Instruction* instr);
  void PrintXImm19(Instruction* instr);
  void PrintSImm19(Instruction* instr);
94
  void PrintXImm21(Instruction* instr);
95
  void PrintSImm21(Instruction* instr);
96
  void PrintPCImm21(Instruction* instr, int delta_pc, int n_bits);
97
  void PrintXImm26(Instruction* instr);
98
  void PrintSImm26(Instruction* instr);
99 100
  void PrintPCImm26(Instruction* instr, int delta_pc, int n_bits);
  void PrintPCImm26(Instruction* instr);
101
  void PrintCode(Instruction* instr);   // For break and trap instructions.
102
  void PrintFormat(Instruction* instr);  // For floating format postfix.
103 104 105 106 107
  // Printing of instruction name.
  void PrintInstructionName(Instruction* instr);

  // Handle formatting of instructions and their options.
  int FormatRegister(Instruction* instr, const char* option);
108
  int FormatFPURegister(Instruction* instr, const char* option);
109 110 111 112
  int FormatOption(Instruction* instr, const char* option);
  void Format(Instruction* instr, const char* format);
  void Unknown(Instruction* instr);

113

114
  // Each of these functions decodes one particular instruction type.
115 116
  bool DecodeTypeRegisterRsType(Instruction* instr);
  void DecodeTypeRegisterSRsType(Instruction* instr);
117 118
  void DecodeTypeRegisterDRsType(Instruction* instr);
  void DecodeTypeRegisterLRsType(Instruction* instr);
119
  void DecodeTypeRegisterWRsType(Instruction* instr);
120 121 122
  void DecodeTypeRegisterSPECIAL(Instruction* instr);
  void DecodeTypeRegisterSPECIAL2(Instruction* instr);
  void DecodeTypeRegisterSPECIAL3(Instruction* instr);
123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
  void DecodeTypeRegister(Instruction* instr);
  void DecodeTypeImmediate(Instruction* instr);
  void DecodeTypeJump(Instruction* instr);

  const disasm::NameConverter& converter_;
  v8::internal::Vector<char> out_buffer_;
  int out_buffer_pos_;

  DISALLOW_COPY_AND_ASSIGN(Decoder);
};


// Support for assertions in the Decoder formatting functions.
#define STRING_STARTS_WITH(string, compare_string) \
  (strncmp(string, compare_string, strlen(compare_string)) == 0)


// Append the ch to the output buffer.
void Decoder::PrintChar(const char ch) {
  out_buffer_[out_buffer_pos_++] = ch;
}


// Append the str to the output buffer.
void Decoder::Print(const char* str) {
  char cur = *str++;
  while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
    PrintChar(cur);
    cur = *str++;
  }
  out_buffer_[out_buffer_pos_] = 0;
}


// Print the register name according to the active name converter.
void Decoder::PrintRegister(int reg) {
  Print(converter_.NameOfCPURegister(reg));
}


void Decoder::PrintRs(Instruction* instr) {
164
  int reg = instr->RsValue();
165 166 167 168 169
  PrintRegister(reg);
}


void Decoder::PrintRt(Instruction* instr) {
170
  int reg = instr->RtValue();
171 172 173 174 175
  PrintRegister(reg);
}


void Decoder::PrintRd(Instruction* instr) {
176
  int reg = instr->RdValue();
177 178 179 180
  PrintRegister(reg);
}


181 182 183
// Print the FPUregister name according to the active name converter.
void Decoder::PrintFPURegister(int freg) {
  Print(converter_.NameOfXMMRegister(freg));
184 185 186
}


187 188 189 190 191 192 193 194 195 196 197
void Decoder::PrintFPUStatusRegister(int freg) {
  switch (freg) {
    case kFCSRRegister:
      Print("FCSR");
      break;
    default:
      Print(converter_.NameOfXMMRegister(freg));
  }
}


198
void Decoder::PrintFs(Instruction* instr) {
199 200
  int freg = instr->RsValue();
  PrintFPURegister(freg);
201 202 203 204
}


void Decoder::PrintFt(Instruction* instr) {
205 206
  int freg = instr->RtValue();
  PrintFPURegister(freg);
207 208 209 210
}


void Decoder::PrintFd(Instruction* instr) {
211 212
  int freg = instr->RdValue();
  PrintFPURegister(freg);
213 214 215 216 217
}


// Print the integer value of the sa field.
void Decoder::PrintSa(Instruction* instr) {
218
  int sa = instr->SaValue();
219
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
220 221 222
}


223 224 225 226 227 228 229
// Print the integer value of the sa field of a lsa instruction.
void Decoder::PrintLsaSa(Instruction* instr) {
  int sa = instr->LsaSaValue() + 1;
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
}


230
// Print the integer value of the rd field, when it is not used as reg.
231 232
void Decoder::PrintSd(Instruction* instr) {
  int sd = instr->RdValue();
233
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd);
234 235 236
}


237 238 239
// Print the integer value of the rd field, when used as 'ext' size.
void Decoder::PrintSs1(Instruction* instr) {
  int ss = instr->RdValue();
240
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss + 1);
241 242 243 244 245 246 247 248
}


// Print the integer value of the rd field, when used as 'ins' size.
void Decoder::PrintSs2(Instruction* instr) {
  int ss = instr->RdValue();
  int pos = instr->SaValue();
  out_buffer_pos_ +=
249
      SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss - pos + 1);
250 251 252
}


253 254 255
// Print the integer value of the cc field for the bc1t/f instructions.
void Decoder::PrintBc(Instruction* instr) {
  int cc = instr->FBccValue();
256
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", cc);
257 258 259 260 261 262
}


// Print the integer value of the cc field for the FP compare instructions.
void Decoder::PrintCc(Instruction* instr) {
  int cc = instr->FCccValue();
263
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc);
264 265 266
}


267 268 269 270 271 272
void Decoder::PrintBp2(Instruction* instr) {
  int bp2 = instr->Bp2Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", bp2);
}


273 274
// Print 16-bit unsigned immediate value.
void Decoder::PrintUImm16(Instruction* instr) {
275
  int32_t imm = instr->Imm16Value();
276
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
277 278 279 280 281
}


// Print 16-bit signed immediate value.
void Decoder::PrintSImm16(Instruction* instr) {
282
  int32_t imm = ((instr->Imm16Value()) << 16) >> 16;
283
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
284 285 286 287 288
}


// Print 16-bit hexa immediate value.
void Decoder::PrintXImm16(Instruction* instr) {
289
  int32_t imm = instr->Imm16Value();
290
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
291 292 293
}


294 295 296 297 298 299 300 301 302 303 304 305
// Print absoulte address for 16-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC + delta_pc + (offset << n_bits)
void Decoder::PrintPCImm16(Instruction* instr, int delta_pc, int n_bits) {
  int16_t offset = instr->Imm16Value();
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
                                        delta_pc + (offset << n_bits)));
}


306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337
// Print 18-bit signed immediate value.
void Decoder::PrintSImm18(Instruction* instr) {
  int32_t imm =
      ((instr->Imm18Value()) << (32 - kImm18Bits)) >> (32 - kImm18Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
}


// Print 18-bit hexa immediate value.
void Decoder::PrintXImm18(Instruction* instr) {
  int32_t imm = instr->Imm18Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
}


// Print 19-bit hexa immediate value.
void Decoder::PrintXImm19(Instruction* instr) {
  int32_t imm = instr->Imm19Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
}


// Print 19-bit signed immediate value.
void Decoder::PrintSImm19(Instruction* instr) {
  int32_t imm19 = instr->Imm19Value();
  // set sign
  imm19 <<= (32 - kImm19Bits);
  imm19 >>= (32 - kImm19Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19);
}


338 339 340 341 342 343 344
// Print 21-bit immediate value.
void Decoder::PrintXImm21(Instruction* instr) {
  uint32_t imm = instr->Imm21Value();
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
}


345 346 347 348 349 350 351 352 353 354
// Print 21-bit signed immediate value.
void Decoder::PrintSImm21(Instruction* instr) {
  int32_t imm21 = instr->Imm21Value();
  // set sign
  imm21 <<= (32 - kImm21Bits);
  imm21 >>= (32 - kImm21Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm21);
}


355 356 357 358 359 360 361 362 363 364 365 366 367 368 369
// Print absoulte address for 21-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC + delta_pc + (offset << n_bits)
void Decoder::PrintPCImm21(Instruction* instr, int delta_pc, int n_bits) {
  int32_t imm21 = instr->Imm21Value();
  // set sign
  imm21 <<= (32 - kImm21Bits);
  imm21 >>= (32 - kImm21Bits);
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
                                        delta_pc + (imm21 << n_bits)));
}


370
// Print 26-bit hex immediate value.
371
void Decoder::PrintXImm26(Instruction* instr) {
372 373 374 375
  uint32_t target = static_cast<uint32_t>(instr->Imm26Value())
                    << kImmFieldShift;
  target = (reinterpret_cast<uint32_t>(instr) & ~0xfffffff) | target;
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", target);
376 377 378
}


379 380 381 382 383 384 385 386 387 388
// Print 26-bit signed immediate value.
void Decoder::PrintSImm26(Instruction* instr) {
  int32_t imm26 = instr->Imm26Value();
  // set sign
  imm26 <<= (32 - kImm26Bits);
  imm26 >>= (32 - kImm26Bits);
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm26);
}


389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416
// Print absoulte address for 26-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC + delta_pc + (offset << n_bits)
void Decoder::PrintPCImm26(Instruction* instr, int delta_pc, int n_bits) {
  int32_t imm26 = instr->Imm26Value();
  // set sign
  imm26 <<= (32 - kImm26Bits);
  imm26 >>= (32 - kImm26Bits);
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
                                        delta_pc + (imm26 << n_bits)));
}


// Print absoulte address for 26-bit offset or immediate value.
// The absolute address is calculated according following expression:
//      PC[GPRLEN-1 .. 28] || instr_index26 || 00
void Decoder::PrintPCImm26(Instruction* instr) {
  int32_t imm26 = instr->Imm26Value();
  uint32_t pc_mask = ~0xfffffff;
  uint32_t pc = ((uint32_t)(instr + 1) & pc_mask) | (imm26 << 2);
  out_buffer_pos_ +=
      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
               converter_.NameOfAddress((reinterpret_cast<byte*>(pc))));
}


417 418 419 420 421 422 423
// Print 26-bit immediate value.
void Decoder::PrintCode(Instruction* instr) {
  if (instr->OpcodeFieldRaw() != SPECIAL)
    return;  // Not a break or trap instruction.
  switch (instr->FunctionFieldRaw()) {
    case BREAK: {
      int32_t code = instr->Bits(25, 6);
424 425
      out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                  "0x%05x (%d)", code, code);
426 427 428 429 430 431 432 433 434 435
      break;
                }
    case TGE:
    case TGEU:
    case TLT:
    case TLTU:
    case TEQ:
    case TNE: {
      int32_t code = instr->Bits(15, 6);
      out_buffer_pos_ +=
436
          SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code);
437 438 439 440
      break;
    }
    default:  // Not a break or trap instruction.
    break;
441
  }
442 443 444
}


445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467
void Decoder::PrintFormat(Instruction* instr) {
  char formatLetter = ' ';
  switch (instr->RsFieldRaw()) {
    case S:
      formatLetter = 's';
      break;
    case D:
      formatLetter = 'd';
      break;
    case W:
      formatLetter = 'w';
      break;
    case L:
      formatLetter = 'l';
      break;
    default:
      UNREACHABLE();
      break;
  }
  PrintChar(formatLetter);
}


468 469 470 471 472 473 474 475
// Printing of instruction name.
void Decoder::PrintInstructionName(Instruction* instr) {
}


// Handle all register based formatting in this function to reduce the
// complexity of FormatOption.
int Decoder::FormatRegister(Instruction* instr, const char* format) {
476
  DCHECK(format[0] == 'r');
477
  if (format[1] == 's') {  // 'rs: Rs register.
478
    int reg = instr->RsValue();
479 480
    PrintRegister(reg);
    return 2;
481
  } else if (format[1] == 't') {  // 'rt: rt register.
482
    int reg = instr->RtValue();
483 484
    PrintRegister(reg);
    return 2;
485
  } else if (format[1] == 'd') {  // 'rd: rd register.
486
    int reg = instr->RdValue();
487 488 489 490 491 492 493 494
    PrintRegister(reg);
    return 2;
  }
  UNREACHABLE();
  return -1;
}


495
// Handle all FPUregister based formatting in this function to reduce the
496
// complexity of FormatOption.
497
int Decoder::FormatFPURegister(Instruction* instr, const char* format) {
498
  DCHECK(format[0] == 'f');
499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534
  if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) {
    if (format[1] == 's') {  // 'fs: fs register.
      int reg = instr->FsValue();
      PrintFPUStatusRegister(reg);
      return 2;
    } else if (format[1] == 't') {  // 'ft: ft register.
      int reg = instr->FtValue();
      PrintFPUStatusRegister(reg);
      return 2;
    } else if (format[1] == 'd') {  // 'fd: fd register.
      int reg = instr->FdValue();
      PrintFPUStatusRegister(reg);
      return 2;
    } else if (format[1] == 'r') {  // 'fr: fr register.
      int reg = instr->FrValue();
      PrintFPUStatusRegister(reg);
      return 2;
    }
  } else {
    if (format[1] == 's') {  // 'fs: fs register.
      int reg = instr->FsValue();
      PrintFPURegister(reg);
      return 2;
    } else if (format[1] == 't') {  // 'ft: ft register.
      int reg = instr->FtValue();
      PrintFPURegister(reg);
      return 2;
    } else if (format[1] == 'd') {  // 'fd: fd register.
      int reg = instr->FdValue();
      PrintFPURegister(reg);
      return 2;
    } else if (format[1] == 'r') {  // 'fr: fr register.
      int reg = instr->FrValue();
      PrintFPURegister(reg);
      return 2;
    }
535 536 537 538 539 540 541 542 543 544 545 546 547
  }
  UNREACHABLE();
  return -1;
}


// FormatOption takes a formatting string and interprets it based on
// the current instructions. The format string points to the first
// character of the option string (the option escape has already been
// consumed by the caller.)  FormatOption returns the number of
// characters that were consumed from the formatting string.
int Decoder::FormatOption(Instruction* instr, const char* format) {
  switch (format[0]) {
548
    case 'c': {   // 'code for break or trap instructions.
549
      DCHECK(STRING_STARTS_WITH(format, "code"));
550 551 552
      PrintCode(instr);
      return 4;
    }
553
    case 'i': {   // 'imm16u or 'imm26.
554
      if (format[3] == '1') {
555 556 557 558 559 560 561 562 563 564 565 566 567 568 569
        if (format[4] == '6') {
          DCHECK(STRING_STARTS_WITH(format, "imm16"));
          switch (format[5]) {
            case 's':
              DCHECK(STRING_STARTS_WITH(format, "imm16s"));
              PrintSImm16(instr);
              break;
            case 'u':
              DCHECK(STRING_STARTS_WITH(format, "imm16u"));
              PrintSImm16(instr);
              break;
            case 'x':
              DCHECK(STRING_STARTS_WITH(format, "imm16x"));
              PrintXImm16(instr);
              break;
570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587
            case 'p': {  // The PC relative address.
              DCHECK(STRING_STARTS_WITH(format, "imm16p"));
              int delta_pc = 0;
              int n_bits = 0;
              switch (format[6]) {
                case '4': {
                  DCHECK(STRING_STARTS_WITH(format, "imm16p4"));
                  delta_pc = 4;
                  switch (format[8]) {
                    case '2':
                      DCHECK(STRING_STARTS_WITH(format, "imm16p4s2"));
                      n_bits = 2;
                      PrintPCImm16(instr, delta_pc, n_bits);
                      return 9;
                  }
                }
              }
            }
588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615
          }
          return 6;
        } else if (format[4] == '8') {
          DCHECK(STRING_STARTS_WITH(format, "imm18"));
          switch (format[5]) {
            case 's':
              DCHECK(STRING_STARTS_WITH(format, "imm18s"));
              PrintSImm18(instr);
              break;
            case 'x':
              DCHECK(STRING_STARTS_WITH(format, "imm18x"));
              PrintXImm18(instr);
              break;
          }
          return 6;
        } else if (format[4] == '9') {
          DCHECK(STRING_STARTS_WITH(format, "imm19"));
          switch (format[5]) {
            case 's':
              DCHECK(STRING_STARTS_WITH(format, "imm19s"));
              PrintSImm19(instr);
              break;
            case 'x':
              DCHECK(STRING_STARTS_WITH(format, "imm19x"));
              PrintXImm19(instr);
              break;
          }
          return 6;
616
        }
617
      } else if (format[3] == '2' && format[4] == '1') {
618 619 620 621 622 623 624 625 626 627
        DCHECK(STRING_STARTS_WITH(format, "imm21"));
        switch (format[5]) {
          case 's':
            DCHECK(STRING_STARTS_WITH(format, "imm21s"));
            PrintSImm21(instr);
            break;
          case 'x':
            DCHECK(STRING_STARTS_WITH(format, "imm21x"));
            PrintXImm21(instr);
            break;
628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645
          case 'p': {  // The PC relative address.
            DCHECK(STRING_STARTS_WITH(format, "imm21p"));
            int delta_pc = 0;
            int n_bits = 0;
            switch (format[6]) {
              case '4': {
                DCHECK(STRING_STARTS_WITH(format, "imm21p4"));
                delta_pc = 4;
                switch (format[8]) {
                  case '2':
                    DCHECK(STRING_STARTS_WITH(format, "imm21p4s2"));
                    n_bits = 2;
                    PrintPCImm21(instr, delta_pc, n_bits);
                    return 9;
                }
              }
            }
          }
646
        }
647 648
        return 6;
      } else if (format[3] == '2' && format[4] == '6') {
649 650 651 652 653 654 655 656 657 658
        DCHECK(STRING_STARTS_WITH(format, "imm26"));
        switch (format[5]) {
          case 's':
            DCHECK(STRING_STARTS_WITH(format, "imm26s"));
            PrintSImm26(instr);
            break;
          case 'x':
            DCHECK(STRING_STARTS_WITH(format, "imm26x"));
            PrintXImm26(instr);
            break;
659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681
          case 'p': {  // The PC relative address.
            DCHECK(STRING_STARTS_WITH(format, "imm26p"));
            int delta_pc = 0;
            int n_bits = 0;
            switch (format[6]) {
              case '4': {
                DCHECK(STRING_STARTS_WITH(format, "imm26p4"));
                delta_pc = 4;
                switch (format[8]) {
                  case '2':
                    DCHECK(STRING_STARTS_WITH(format, "imm26p4s2"));
                    n_bits = 2;
                    PrintPCImm26(instr, delta_pc, n_bits);
                    return 9;
                }
              }
            }
          }
          case 'j': {  // Absolute address for jump instructions.
            DCHECK(STRING_STARTS_WITH(format, "imm26j"));
            PrintPCImm26(instr);
            break;
          }
682
        }
683
        return 6;
684 685
      }
    }
686
    case 'r': {   // 'r: registers.
687 688
      return FormatRegister(instr, format);
    }
689
    case 'f': {   // 'f: FPUregisters.
690
      return FormatFPURegister(instr, format);
691
    }
692
    case 's': {   // 'sa.
693
      switch (format[1]) {
694 695 696 697 698 699 700 701 702 703 704
        case 'a':
          if (format[2] == '2') {
            DCHECK(STRING_STARTS_WITH(format, "sa2"));  // 'sa2
            PrintLsaSa(instr);
            return 3;
          } else {
            DCHECK(STRING_STARTS_WITH(format, "sa"));
            PrintSa(instr);
            return 2;
          }
          break;
705
        case 'd': {
706
          DCHECK(STRING_STARTS_WITH(format, "sd"));
707 708 709
          PrintSd(instr);
          return 2;
        }
710 711
        case 's': {
          if (format[2] == '1') {
712
              DCHECK(STRING_STARTS_WITH(format, "ss1"));  /* ext size */
713 714 715
              PrintSs1(instr);
              return 3;
          } else {
716
              DCHECK(STRING_STARTS_WITH(format, "ss2"));  /* ins size */
717 718 719 720
              PrintSs2(instr);
              return 3;
          }
        }
721 722
      }
    }
723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739
    case 'b': {
      switch (format[1]) {
        case 'c': {  // 'bc - Special for bc1 cc field.
          DCHECK(STRING_STARTS_WITH(format, "bc"));
          PrintBc(instr);
          return 2;
        }
        case 'p': {
          switch (format[2]) {
            case '2': {  // 'bp2
              DCHECK(STRING_STARTS_WITH(format, "bp2"));
              PrintBp2(instr);
              return 3;
            }
          }
        }
      }
740 741
    }
    case 'C': {   // 'Cc - Special for c.xx.d cc field.
742
      DCHECK(STRING_STARTS_WITH(format, "Cc"));
743
      PrintCc(instr);
744 745
      return 2;
    }
746 747 748
    case 't':
      PrintFormat(instr);
      return 1;
749
  }
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778
  UNREACHABLE();
  return -1;
}


// Format takes a formatting string for a whole instruction and prints it into
// the output buffer. All escaped options are handed to FormatOption to be
// parsed further.
void Decoder::Format(Instruction* instr, const char* format) {
  char cur = *format++;
  while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
    if (cur == '\'') {  // Single quote is used as the formatting escape.
      format += FormatOption(instr, format);
    } else {
      out_buffer_[out_buffer_pos_++] = cur;
    }
    cur = *format++;
  }
  out_buffer_[out_buffer_pos_]  = '\0';
}


// For currently unimplemented decodings the disassembler calls Unknown(instr)
// which will just print "unknown" of the instruction bits.
void Decoder::Unknown(Instruction* instr) {
  Format(instr, "unknown");
}


779
bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) {
780
  switch (instr->FunctionFieldRaw()) {
781 782 783
    case RINT:
      Format(instr, "rint.'t    'fd, 'fs");
      break;
784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804
    case MIN:
      Format(instr, "min.'t    'fd, 'fs, 'ft");
      break;
    case MAX:
      Format(instr, "max.'t    'fd, 'fs, 'ft");
      break;
    case MINA:
      Format(instr, "mina.'t   'fd, 'fs, 'ft");
      break;
    case MAXA:
      Format(instr, "maxa.'t   'fd, 'fs, 'ft");
      break;
    case SEL:
      Format(instr, "sel.'t      'fd, 'fs, 'ft");
      break;
    case SELEQZ_C:
      Format(instr, "seleqz.'t    'fd, 'fs, 'ft");
      break;
    case SELNEZ_C:
      Format(instr, "selnez.'t    'fd, 'fs, 'ft");
      break;
805 806 807 808 809 810 811 812 813 814 815 816 817
    case MOVZ_C:
      Format(instr, "movz.'t    'fd, 'fs, 'rt");
      break;
    case MOVN_C:
      Format(instr, "movn.'t    'fd, 'fs, 'rt");
      break;
    case MOVF:
      if (instr->Bit(16)) {
        Format(instr, "movt.'t    'fd, 'fs, 'Cc");
      } else {
        Format(instr, "movf.'t    'fd, 'fs, 'Cc");
      }
      break;
818
    case ADD_D:
819
      Format(instr, "add.'t   'fd, 'fs, 'ft");
820 821
      break;
    case SUB_D:
822
      Format(instr, "sub.'t   'fd, 'fs, 'ft");
823 824
      break;
    case MUL_D:
825
      Format(instr, "mul.'t   'fd, 'fs, 'ft");
826 827
      break;
    case DIV_D:
828
      Format(instr, "div.'t   'fd, 'fs, 'ft");
829 830
      break;
    case ABS_D:
831
      Format(instr, "abs.'t   'fd, 'fs");
832 833
      break;
    case MOV_D:
834
      Format(instr, "mov.'t   'fd, 'fs");
835 836
      break;
    case NEG_D:
837
      Format(instr, "neg.'t   'fd, 'fs");
838 839
      break;
    case SQRT_D:
840
      Format(instr, "sqrt.'t  'fd, 'fs");
841
      break;
842 843 844 845 846 847
    case RECIP_D:
      Format(instr, "recip.'t  'fd, 'fs");
      break;
    case RSQRT_D:
      Format(instr, "rsqrt.'t  'fd, 'fs");
      break;
848
    case CVT_W_D:
849
      Format(instr, "cvt.w.'t 'fd, 'fs");
850 851
      break;
    case CVT_L_D:
852
      Format(instr, "cvt.l.'t 'fd, 'fs");
853 854
      break;
    case TRUNC_W_D:
855
      Format(instr, "trunc.w.'t 'fd, 'fs");
856 857
      break;
    case TRUNC_L_D:
858
      Format(instr, "trunc.l.'t 'fd, 'fs");
859 860
      break;
    case ROUND_W_D:
861
      Format(instr, "round.w.'t 'fd, 'fs");
862
      break;
863 864 865
    case ROUND_L_D:
      Format(instr, "round.l.'t 'fd, 'fs");
      break;
866
    case FLOOR_W_D:
867
      Format(instr, "floor.w.'t 'fd, 'fs");
868
      break;
869 870 871
    case FLOOR_L_D:
      Format(instr, "floor.l.'t 'fd, 'fs");
      break;
872
    case CEIL_W_D:
873
      Format(instr, "ceil.w.'t 'fd, 'fs");
874
      break;
875 876 877
    case CLASS_D:
      Format(instr, "class.'t 'fd, 'fs");
      break;
878 879 880
    case CEIL_L_D:
      Format(instr, "ceil.l.'t 'fd, 'fs");
      break;
881
    case CVT_S_D:
882
      Format(instr, "cvt.s.'t 'fd, 'fs");
883 884
      break;
    case C_F_D:
885
      Format(instr, "c.f.'t   'fs, 'ft, 'Cc");
886 887
      break;
    case C_UN_D:
888
      Format(instr, "c.un.'t  'fs, 'ft, 'Cc");
889 890
      break;
    case C_EQ_D:
891
      Format(instr, "c.eq.'t  'fs, 'ft, 'Cc");
892 893
      break;
    case C_UEQ_D:
894
      Format(instr, "c.ueq.'t 'fs, 'ft, 'Cc");
895 896
      break;
    case C_OLT_D:
897
      Format(instr, "c.olt.'t 'fs, 'ft, 'Cc");
898 899
      break;
    case C_ULT_D:
900
      Format(instr, "c.ult.'t 'fs, 'ft, 'Cc");
901 902
      break;
    case C_OLE_D:
903
      Format(instr, "c.ole.'t 'fs, 'ft, 'Cc");
904 905
      break;
    case C_ULE_D:
906
      Format(instr, "c.ule.'t 'fs, 'ft, 'Cc");
907 908
      break;
    default:
909 910 911 912 913 914 915 916 917 918 919 920
      return false;
  }
  return true;
}


void Decoder::DecodeTypeRegisterSRsType(Instruction* instr) {
  if (!DecodeTypeRegisterRsType(instr)) {
    switch (instr->FunctionFieldRaw()) {
      case CVT_D_S:
        Format(instr, "cvt.d.'t 'fd, 'fs");
        break;
921 922 923 924 925 926
      case MADDF_S:
        Format(instr, "maddf.s  'fd, 'fs, 'ft");
        break;
      case MSUBF_S:
        Format(instr, "msubf.s  'fd, 'fs, 'ft");
        break;
927 928 929 930 931 932 933 934 935 936
      default:
        Format(instr, "unknown.cop1.'t");
        break;
    }
  }
}


void Decoder::DecodeTypeRegisterDRsType(Instruction* instr) {
  if (!DecodeTypeRegisterRsType(instr)) {
937 938 939 940 941 942 943 944 945 946 947
    switch (instr->FunctionFieldRaw()) {
      case MADDF_D:
        Format(instr, "maddf.d  'fd, 'fs, 'ft");
        break;
      case MSUBF_D:
        Format(instr, "msubf.d  'fd, 'fs, 'ft");
        break;
      default:
        Format(instr, "unknown.cop1.'t");
        break;
    }
948 949 950 951 952 953 954 955 956 957 958 959
  }
}


void Decoder::DecodeTypeRegisterLRsType(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case CVT_D_L:
      Format(instr, "cvt.d.l 'fd, 'fs");
      break;
    case CVT_S_L:
      Format(instr, "cvt.s.l 'fd, 'fs");
      break;
960 961 962
    case CMP_AF:
      Format(instr, "cmp.af.d  'fd,  'fs, 'ft");
      break;
963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998
    case CMP_UN:
      Format(instr, "cmp.un.d  'fd,  'fs, 'ft");
      break;
    case CMP_EQ:
      Format(instr, "cmp.eq.d  'fd,  'fs, 'ft");
      break;
    case CMP_UEQ:
      Format(instr, "cmp.ueq.d  'fd,  'fs, 'ft");
      break;
    case CMP_LT:
      Format(instr, "cmp.lt.d  'fd,  'fs, 'ft");
      break;
    case CMP_ULT:
      Format(instr, "cmp.ult.d  'fd,  'fs, 'ft");
      break;
    case CMP_LE:
      Format(instr, "cmp.le.d  'fd,  'fs, 'ft");
      break;
    case CMP_ULE:
      Format(instr, "cmp.ule.d  'fd,  'fs, 'ft");
      break;
    case CMP_OR:
      Format(instr, "cmp.or.d  'fd,  'fs, 'ft");
      break;
    case CMP_UNE:
      Format(instr, "cmp.une.d  'fd,  'fs, 'ft");
      break;
    case CMP_NE:
      Format(instr, "cmp.ne.d  'fd,  'fs, 'ft");
      break;
    default:
      UNREACHABLE();
  }
}


999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045
void Decoder::DecodeTypeRegisterWRsType(Instruction* instr) {
  switch (instr->FunctionValue()) {
    case CVT_S_W:  // Convert word to float (single).
      Format(instr, "cvt.s.w 'fd, 'fs");
      break;
    case CVT_D_W:  // Convert word to double.
      Format(instr, "cvt.d.w 'fd, 'fs");
      break;
    case CMP_AF:
      Format(instr, "cmp.af.s    'fd, 'fs, 'ft");
      break;
    case CMP_UN:
      Format(instr, "cmp.un.s    'fd, 'fs, 'ft");
      break;
    case CMP_EQ:
      Format(instr, "cmp.eq.s    'fd, 'fs, 'ft");
      break;
    case CMP_UEQ:
      Format(instr, "cmp.ueq.s   'fd, 'fs, 'ft");
      break;
    case CMP_LT:
      Format(instr, "cmp.lt.s    'fd, 'fs, 'ft");
      break;
    case CMP_ULT:
      Format(instr, "cmp.ult.s   'fd, 'fs, 'ft");
      break;
    case CMP_LE:
      Format(instr, "cmp.le.s    'fd, 'fs, 'ft");
      break;
    case CMP_ULE:
      Format(instr, "cmp.ule.s   'fd, 'fs, 'ft");
      break;
    case CMP_OR:
      Format(instr, "cmp.or.s    'fd, 'fs, 'ft");
      break;
    case CMP_UNE:
      Format(instr, "cmp.une.s   'fd, 'fs, 'ft");
      break;
    case CMP_NE:
      Format(instr, "cmp.ne.s    'fd, 'fs, 'ft");
      break;
    default:
      UNREACHABLE();
  }
}


1046 1047 1048 1049 1050 1051
void Decoder::DecodeTypeRegisterSPECIAL(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case JR:
      Format(instr, "jr      'rs");
      break;
    case JALR:
1052
      Format(instr, "jalr    'rs, 'rd");
1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
      break;
    case SLL:
      if (0x0 == static_cast<int>(instr->InstructionBits()))
        Format(instr, "nop");
      else
        Format(instr, "sll     'rd, 'rt, 'sa");
      break;
    case SRL:
      if (instr->RsValue() == 0) {
        Format(instr, "srl     'rd, 'rt, 'sa");
      } else {
        if (IsMipsArchVariant(kMips32r2)) {
          Format(instr, "rotr    'rd, 'rt, 'sa");
        } else {
          Unknown(instr);
        }
      }
      break;
    case SRA:
      Format(instr, "sra     'rd, 'rt, 'sa");
      break;
    case SLLV:
      Format(instr, "sllv    'rd, 'rt, 'rs");
      break;
    case SRLV:
      if (instr->SaValue() == 0) {
        Format(instr, "srlv    'rd, 'rt, 'rs");
      } else {
        if (IsMipsArchVariant(kMips32r2)) {
          Format(instr, "rotrv   'rd, 'rt, 'rs");
        } else {
          Unknown(instr);
        }
      }
      break;
    case SRAV:
      Format(instr, "srav    'rd, 'rt, 'rs");
      break;
1091 1092 1093
    case LSA:
      Format(instr, "lsa     'rd, 'rt, 'rs, 'sa2");
      break;
1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
    case MFHI:
      if (instr->Bits(25, 16) == 0) {
        Format(instr, "mfhi    'rd");
      } else {
        if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) {
          Format(instr, "clz     'rd, 'rs");
        } else if ((instr->FunctionFieldRaw() == CLO_R6) &&
                   (instr->FdValue() == 1)) {
          Format(instr, "clo     'rd, 'rs");
        }
      }
      break;
    case MFLO:
      Format(instr, "mflo    'rd");
      break;
    case MULT:  // @Mips32r6 == MUL_MUH.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "mult    'rs, 'rt");
      } else {
        if (instr->SaValue() == MUL_OP) {
          Format(instr, "mul    'rd, 'rs, 'rt");
        } else {
          Format(instr, "muh    'rd, 'rs, 'rt");
        }
      }
      break;
    case MULTU:  // @Mips32r6 == MUL_MUH_U.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "multu   'rs, 'rt");
      } else {
        if (instr->SaValue() == MUL_OP) {
          Format(instr, "mulu   'rd, 'rs, 'rt");
        } else {
          Format(instr, "muhu   'rd, 'rs, 'rt");
        }
      }
      break;
    case DIV:  // @Mips32r6 == DIV_MOD.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "div     'rs, 'rt");
      } else {
        if (instr->SaValue() == DIV_OP) {
          Format(instr, "div    'rd, 'rs, 'rt");
        } else {
          Format(instr, "mod    'rd, 'rs, 'rt");
        }
      }
      break;
    case DIVU:  // @Mips32r6 == DIV_MOD_U.
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "divu    'rs, 'rt");
      } else {
        if (instr->SaValue() == DIV_OP) {
          Format(instr, "divu   'rd, 'rs, 'rt");
        } else {
          Format(instr, "modu   'rd, 'rs, 'rt");
        }
      }
      break;
    case ADD:
      Format(instr, "add     'rd, 'rs, 'rt");
      break;
    case ADDU:
      Format(instr, "addu    'rd, 'rs, 'rt");
      break;
    case SUB:
      Format(instr, "sub     'rd, 'rs, 'rt");
      break;
    case SUBU:
      Format(instr, "subu    'rd, 'rs, 'rt");
      break;
    case AND:
      Format(instr, "and     'rd, 'rs, 'rt");
      break;
    case OR:
      if (0 == instr->RsValue()) {
        Format(instr, "mov     'rd, 'rt");
      } else if (0 == instr->RtValue()) {
        Format(instr, "mov     'rd, 'rs");
      } else {
        Format(instr, "or      'rd, 'rs, 'rt");
      }
      break;
    case XOR:
      Format(instr, "xor     'rd, 'rs, 'rt");
      break;
    case NOR:
      Format(instr, "nor     'rd, 'rs, 'rt");
      break;
    case SLT:
      Format(instr, "slt     'rd, 'rs, 'rt");
      break;
    case SLTU:
      Format(instr, "sltu    'rd, 'rs, 'rt");
      break;
    case BREAK:
      Format(instr, "break, code: 'code");
      break;
    case TGE:
      Format(instr, "tge     'rs, 'rt, code: 'code");
      break;
    case TGEU:
      Format(instr, "tgeu    'rs, 'rt, code: 'code");
      break;
    case TLT:
      Format(instr, "tlt     'rs, 'rt, code: 'code");
      break;
    case TLTU:
      Format(instr, "tltu    'rs, 'rt, code: 'code");
      break;
    case TEQ:
      Format(instr, "teq     'rs, 'rt, code: 'code");
      break;
    case TNE:
      Format(instr, "tne     'rs, 'rt, code: 'code");
      break;
1210 1211 1212
    case SYNC:
      Format(instr, "sync");
      break;
1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226
    case MOVZ:
      Format(instr, "movz    'rd, 'rs, 'rt");
      break;
    case MOVN:
      Format(instr, "movn    'rd, 'rs, 'rt");
      break;
    case MOVCI:
      if (instr->Bit(16)) {
        Format(instr, "movt    'rd, 'rs, 'bc");
      } else {
        Format(instr, "movf    'rd, 'rs, 'bc");
      }
      break;
    case SELEQZ_S:
1227
      Format(instr, "seleqz    'rd, 'rs, 'rt");
1228 1229
      break;
    case SELNEZ_S:
1230
      Format(instr, "selnez    'rd, 'rs, 'rt");
1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256
      break;
    default:
      UNREACHABLE();
  }
}


void Decoder::DecodeTypeRegisterSPECIAL2(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case MUL:
      Format(instr, "mul     'rd, 'rs, 'rt");
      break;
    case CLZ:
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "clz     'rd, 'rs");
      }
      break;
    default:
      UNREACHABLE();
  }
}


void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
  switch (instr->FunctionFieldRaw()) {
    case INS: {
1257
      if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1258 1259 1260 1261 1262 1263 1264
        Format(instr, "ins     'rt, 'rs, 'sa, 'ss2");
      } else {
        Unknown(instr);
      }
      break;
    }
    case EXT: {
1265
      if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
1266 1267 1268 1269 1270 1271
        Format(instr, "ext     'rt, 'rs, 'sa, 'ss1");
      } else {
        Unknown(instr);
      }
      break;
    }
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282
    case BSHFL: {
      int sa = instr->SaFieldRaw() >> kSaShift;
      switch (sa) {
        case BITSWAP: {
          if (IsMipsArchVariant(kMips32r6)) {
            Format(instr, "bitswap 'rd, 'rt");
          } else {
            Unknown(instr);
          }
          break;
        }
1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
        case SEB: {
          if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
            Format(instr, "seb     'rd, 'rt");
          } else {
            Unknown(instr);
          }
          break;
        }
        case SEH: {
          if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
            Format(instr, "seh     'rd, 'rt");
          } else {
            Unknown(instr);
          }
1297
          break;
1298 1299 1300 1301 1302 1303 1304 1305 1306
        }
        case WSBH: {
          if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
            Format(instr, "wsbh    'rd, 'rt");
          } else {
            Unknown(instr);
          }
          break;
        }
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322
        default: {
          sa >>= kBp2Bits;
          switch (sa) {
            case ALIGN: {
              if (IsMipsArchVariant(kMips32r6)) {
                Format(instr, "align  'rd, 'rs, 'rt, 'bp2");
              } else {
                Unknown(instr);
              }
              break;
            }
            default:
              UNREACHABLE();
              break;
          }
        }
1323 1324 1325
      }
      break;
    }
1326 1327 1328 1329 1330 1331
    default:
      UNREACHABLE();
  }
}


1332 1333
void Decoder::DecodeTypeRegister(Instruction* instr) {
  switch (instr->OpcodeFieldRaw()) {
1334
    case COP1:    // Coprocessor instructions.
1335
      switch (instr->RsFieldRaw()) {
1336
        case BC1:   // bc1 handled in DecodeTypeImmediate.
1337 1338 1339
          UNREACHABLE();
          break;
        case MFC1:
1340
          Format(instr, "mfc1    'rt, 'fs");
1341 1342
          break;
        case MFHC1:
1343
          Format(instr, "mfhc1   'rt, 'fs");
1344 1345
          break;
        case MTC1:
1346
          Format(instr, "mtc1    'rt, 'fs");
1347 1348 1349
          break;
        // These are called "fs" too, although they are not FPU registers.
        case CTC1:
1350
          Format(instr, "ctc1    'rt, 'fs");
1351 1352
          break;
        case CFC1:
1353
          Format(instr, "cfc1    'rt, 'fs");
1354 1355
          break;
        case MTHC1:
1356
          Format(instr, "mthc1   'rt, 'fs");
1357
          break;
1358 1359 1360
        case S:
          DecodeTypeRegisterSRsType(instr);
          break;
1361
        case D:
1362
          DecodeTypeRegisterDRsType(instr);
1363
          break;
1364
        case L:
1365
          DecodeTypeRegisterLRsType(instr);
1366
          break;
1367 1368 1369
        case W:
          DecodeTypeRegisterWRsType(instr);
          break;
1370 1371 1372 1373 1374
        case PS:
          UNIMPLEMENTED_MIPS();
          break;
        default:
          UNREACHABLE();
1375
      }
1376
      break;
1377 1378
    case COP1X:
      switch (instr->FunctionFieldRaw()) {
1379 1380 1381
        case MADD_S:
          Format(instr, "madd.s  'fd, 'fr, 'fs, 'ft");
          break;
1382 1383 1384
        case MADD_D:
          Format(instr, "madd.d  'fd, 'fr, 'fs, 'ft");
          break;
1385 1386 1387 1388 1389 1390
        case MSUB_S:
          Format(instr, "msub.s  'fd, 'fr, 'fs, 'ft");
          break;
        case MSUB_D:
          Format(instr, "msub.d  'fd, 'fr, 'fs, 'ft");
          break;
1391 1392
        default:
          UNREACHABLE();
1393
      }
1394
      break;
1395
    case SPECIAL:
1396
      DecodeTypeRegisterSPECIAL(instr);
1397 1398
      break;
    case SPECIAL2:
1399
      DecodeTypeRegisterSPECIAL2(instr);
1400 1401
      break;
    case SPECIAL3:
1402
      DecodeTypeRegisterSPECIAL3(instr);
1403 1404 1405
      break;
    default:
      UNREACHABLE();
1406
  }
1407 1408 1409 1410 1411
}


void Decoder::DecodeTypeImmediate(Instruction* instr) {
  switch (instr->OpcodeFieldRaw()) {
1412 1413 1414 1415
    case COP1:
      switch (instr->RsFieldRaw()) {
        case BC1:
          if (instr->FBtrueValue()) {
1416
            Format(instr, "bc1t    'bc, 'imm16u -> 'imm16p4s2");
1417
          } else {
1418
            Format(instr, "bc1f    'bc, 'imm16u -> 'imm16p4s2");
1419 1420
          }
          break;
1421
        case BC1EQZ:
1422
          Format(instr, "bc1eqz    'ft, 'imm16u -> 'imm16p4s2");
1423 1424
          break;
        case BC1NEZ:
1425
          Format(instr, "bc1nez    'ft, 'imm16u -> 'imm16p4s2");
1426
          break;
1427 1428
        default:
          UNREACHABLE();
1429
      }
1430

1431
      break;  // Case COP1.
1432
    // ------------- REGIMM class.
1433 1434 1435
    case REGIMM:
      switch (instr->RtFieldRaw()) {
        case BLTZ:
1436
          Format(instr, "bltz    'rs, 'imm16u -> 'imm16p4s2");
1437 1438
          break;
        case BLTZAL:
1439
          Format(instr, "bltzal  'rs, 'imm16u -> 'imm16p4s2");
1440 1441
          break;
        case BGEZ:
1442
          Format(instr, "bgez    'rs, 'imm16u -> 'imm16p4s2");
1443
          break;
1444 1445 1446 1447 1448
        case BGEZAL: {
          if (instr->RsValue() == 0)
            Format(instr, "bal     'imm16s -> 'imm16p4s2");
          else
            Format(instr, "bgezal  'rs, 'imm16u -> 'imm16p4s2");
1449
          break;
1450
        }
1451
        case BGEZALL:
1452
          Format(instr, "bgezall 'rs, 'imm16u -> 'imm16p4s2");
1453
          break;
1454 1455
        default:
          UNREACHABLE();
1456 1457
      }
    break;  // Case REGIMM.
1458 1459
    // ------------- Branch instructions.
    case BEQ:
1460
      Format(instr, "beq     'rs, 'rt, 'imm16u -> 'imm16p4s2");
1461
      break;
1462
    case BC:
1463
      Format(instr, "bc      'imm26s -> 'imm26p4s2");
1464 1465
      break;
    case BALC:
1466
      Format(instr, "balc    'imm26s -> 'imm26p4s2");
1467
      break;
1468
    case BNE:
1469
      Format(instr, "bne     'rs, 'rt, 'imm16u -> 'imm16p4s2");
1470 1471
      break;
    case BLEZ:
1472 1473 1474 1475
      if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
        Format(instr, "blez    'rs, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
1476
        Format(instr, "bgeuc   'rs, 'rt, 'imm16u -> 'imm16p4s2");
1477 1478
      } else if ((instr->RtValue() == instr->RsValue()) &&
                 (instr->RtValue() != 0)) {
1479
        Format(instr, "bgezalc 'rs, 'imm16u -> 'imm16p4s2");
1480
      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
1481
        Format(instr, "blezalc 'rt, 'imm16u -> 'imm16p4s2");
1482 1483 1484
      } else {
        UNREACHABLE();
      }
1485 1486
      break;
    case BGTZ:
1487 1488 1489 1490 1491 1492 1493 1494 1495 1496
      if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
        Format(instr, "bgtz    'rs, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
        Format(instr, "bltuc   'rs, 'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() == instr->RsValue()) &&
                 (instr->RtValue() != 0)) {
        Format(instr, "bltzalc 'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
        Format(instr, "bgtzalc 'rt, 'imm16u -> 'imm16p4s2");
1497 1498 1499 1500 1501
      } else {
        UNREACHABLE();
      }
      break;
    case BLEZL:
1502 1503 1504 1505 1506 1507 1508
      if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
        Format(instr, "bgezc    'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
        Format(instr, "bgec     'rs, 'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
        Format(instr, "blezc    'rt, 'imm16u -> 'imm16p4s2");
1509 1510 1511 1512 1513
      } else {
        UNREACHABLE();
      }
      break;
    case BGTZL:
1514 1515 1516 1517
      if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
        Format(instr, "bltzc    'rt, 'imm16u -> 'imm16p4s2");
      } else if ((instr->RtValue() != instr->RsValue()) &&
                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
1518
        Format(instr, "bltc    'rs, 'rt, 'imm16u -> 'imm16p4s2");
1519 1520
      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
        Format(instr, "bgtzc    'rt, 'imm16u -> 'imm16p4s2");
1521 1522 1523 1524
      } else {
        UNREACHABLE();
      }
      break;
1525 1526 1527 1528
    case POP66:
      if (instr->RsValue() == JIC) {
        Format(instr, "jic     'rt, 'imm16s");
      } else {
1529
        Format(instr, "beqzc   'rs, 'imm21s -> 'imm21p4s2");
1530 1531
      }
      break;
1532 1533
    case POP76:
      if (instr->RsValue() == JIALC) {
1534
        Format(instr, "jialc   'rt, 'imm16s");
1535
      } else {
1536
        Format(instr, "bnezc   'rs, 'imm21s -> 'imm21p4s2");
1537
      }
1538 1539 1540
      break;
    // ------------- Arithmetic instructions.
    case ADDI:
1541 1542 1543
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "addi    'rt, 'rs, 'imm16s");
      } else {
1544 1545 1546 1547
        int rs_reg = instr->RsValue();
        int rt_reg = instr->RtValue();
        // Check if BOVC, BEQZALC or BEQC instruction.
        if (rs_reg >= rt_reg) {
1548
          Format(instr, "bovc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
1549
        } else {
1550
          DCHECK(rt_reg > 0);
1551 1552 1553 1554 1555
          if (rs_reg == 0) {
            Format(instr, "beqzalc 'rt, 'imm16s -> 'imm16p4s2");
          } else {
            Format(instr, "beqc    'rs, 'rt, 'imm16s -> 'imm16p4s2");
          }
1556 1557 1558 1559 1560
        }
      }
      break;
    case DADDI:
      if (IsMipsArchVariant(kMips32r6)) {
1561 1562 1563 1564
        int rs_reg = instr->RsValue();
        int rt_reg = instr->RtValue();
        // Check if BNVC, BNEZALC or BNEC instruction.
        if (rs_reg >= rt_reg) {
1565
          Format(instr, "bnvc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
1566
        } else {
1567
          DCHECK(rt_reg > 0);
1568 1569 1570 1571 1572
          if (rs_reg == 0) {
            Format(instr, "bnezalc 'rt, 'imm16s -> 'imm16p4s2");
          } else {
            Format(instr, "bnec  'rs, 'rt, 'imm16s -> 'imm16p4s2");
          }
1573 1574
        }
      }
1575 1576
      break;
    case ADDIU:
1577
      Format(instr, "addiu   'rt, 'rs, 'imm16s");
1578 1579
      break;
    case SLTI:
1580
      Format(instr, "slti    'rt, 'rs, 'imm16s");
1581 1582
      break;
    case SLTIU:
1583
      Format(instr, "sltiu   'rt, 'rs, 'imm16u");
1584 1585
      break;
    case ANDI:
1586
      Format(instr, "andi    'rt, 'rs, 'imm16x");
1587 1588
      break;
    case ORI:
1589
      Format(instr, "ori     'rt, 'rs, 'imm16x");
1590 1591
      break;
    case XORI:
1592
      Format(instr, "xori    'rt, 'rs, 'imm16x");
1593 1594
      break;
    case LUI:
1595 1596 1597 1598
      if (!IsMipsArchVariant(kMips32r6)) {
        Format(instr, "lui     'rt, 'imm16x");
      } else {
        if (instr->RsValue() != 0) {
1599
          Format(instr, "aui     'rt, 'rs, 'imm16x");
1600 1601 1602 1603
        } else {
          Format(instr, "lui     'rt, 'imm16x");
        }
      }
1604 1605 1606
      break;
    // ------------- Memory instructions.
    case LB:
1607
      Format(instr, "lb      'rt, 'imm16s('rs)");
1608
      break;
1609
    case LH:
1610
      Format(instr, "lh      'rt, 'imm16s('rs)");
1611 1612
      break;
    case LWL:
1613
      Format(instr, "lwl     'rt, 'imm16s('rs)");
1614
      break;
1615
    case LW:
1616
      Format(instr, "lw      'rt, 'imm16s('rs)");
1617 1618
      break;
    case LBU:
1619
      Format(instr, "lbu     'rt, 'imm16s('rs)");
1620
      break;
1621
    case LHU:
1622
      Format(instr, "lhu     'rt, 'imm16s('rs)");
1623 1624
      break;
    case LWR:
1625
      Format(instr, "lwr     'rt, 'imm16s('rs)");
1626
      break;
plind44@gmail.com's avatar
plind44@gmail.com committed
1627 1628 1629
    case PREF:
      Format(instr, "pref    'rt, 'imm16s('rs)");
      break;
1630
    case SB:
1631
      Format(instr, "sb      'rt, 'imm16s('rs)");
1632
      break;
1633
    case SH:
1634
      Format(instr, "sh      'rt, 'imm16s('rs)");
1635 1636
      break;
    case SWL:
1637
      Format(instr, "swl     'rt, 'imm16s('rs)");
1638
      break;
1639
    case SW:
1640
      Format(instr, "sw      'rt, 'imm16s('rs)");
1641
      break;
1642
    case SWR:
1643
      Format(instr, "swr     'rt, 'imm16s('rs)");
1644
      break;
1645
    case LWC1:
1646
      Format(instr, "lwc1    'ft, 'imm16s('rs)");
1647 1648
      break;
    case LDC1:
1649
      Format(instr, "ldc1    'ft, 'imm16s('rs)");
1650 1651
      break;
    case SWC1:
1652
      Format(instr, "swc1    'ft, 'imm16s('rs)");
1653 1654
      break;
    case SDC1:
1655
      Format(instr, "sdc1    'ft, 'imm16s('rs)");
1656
      break;
1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685
    case PCREL: {
      int32_t imm21 = instr->Imm21Value();
      // rt field: 5-bits checking
      uint8_t rt = (imm21 >> kImm16Bits);
      switch (rt) {
        case ALUIPC:
          Format(instr, "aluipc  'rs, 'imm16s");
          break;
        case AUIPC:
          Format(instr, "auipc   'rs, 'imm16s");
          break;
        default: {
          // rt field: checking of the most significant 2-bits
          rt = (imm21 >> kImm19Bits);
          switch (rt) {
            case LWPC:
              Format(instr, "lwpc    'rs, 'imm19s");
              break;
            case ADDIUPC:
              Format(instr, "addiupc 'rs, 'imm19s");
              break;
            default:
              UNREACHABLE();
              break;
          }
        }
      }
      break;
    }
1686
    default:
1687
      printf("a 0x%x \n", instr->OpcodeFieldRaw());
1688 1689
      UNREACHABLE();
      break;
1690
  }
1691 1692 1693 1694 1695 1696
}


void Decoder::DecodeTypeJump(Instruction* instr) {
  switch (instr->OpcodeFieldRaw()) {
    case J:
1697
      Format(instr, "j       'imm26x -> 'imm26j");
1698 1699
      break;
    case JAL:
1700
      Format(instr, "jal     'imm26x -> 'imm26j");
1701 1702 1703 1704 1705 1706 1707 1708
      break;
    default:
      UNREACHABLE();
  }
}


// Disassemble the instruction at *instr_ptr into the output buffer.
1709
int Decoder::InstructionDecode(byte* instr_ptr) {
1710 1711
  Instruction* instr = Instruction::At(instr_ptr);
  // Print raw instruction bytes.
1712 1713 1714
  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                   "%08x       ",
                                   instr->InstructionBits());
1715
  switch (instr->InstructionType()) {
1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728
    case Instruction::kRegisterType: {
      DecodeTypeRegister(instr);
      break;
    }
    case Instruction::kImmediateType: {
      DecodeTypeImmediate(instr);
      break;
    }
    case Instruction::kJumpType: {
      DecodeTypeJump(instr);
      break;
    }
    default: {
1729
      Format(instr, "UNSUPPORTED");
1730 1731 1732
      UNSUPPORTED_MIPS();
    }
  }
1733
  return Instruction::kInstrSize;
1734 1735 1736
}


1737 1738
}  // namespace internal
}  // namespace v8
1739 1740 1741 1742 1743 1744


//------------------------------------------------------------------------------

namespace disasm {

1745
const char* NameConverter::NameOfAddress(byte* addr) const {
1746
  v8::internal::SNPrintF(tmp_buffer_, "%p", static_cast<void*>(addr));
1747
  return tmp_buffer_.start();
1748 1749 1750
}


1751
const char* NameConverter::NameOfConstant(byte* addr) const {
1752 1753 1754 1755 1756
  return NameOfAddress(addr);
}


const char* NameConverter::NameOfCPURegister(int reg) const {
1757
  return v8::internal::Registers::Name(reg);
1758 1759 1760 1761
}


const char* NameConverter::NameOfXMMRegister(int reg) const {
1762
  return v8::internal::FPURegisters::Name(reg);
1763 1764 1765 1766
}


const char* NameConverter::NameOfByteCPURegister(int reg) const {
1767
  UNREACHABLE();  // MIPS does not have the concept of a byte register.
1768 1769 1770 1771
  return "nobytereg";
}


1772
const char* NameConverter::NameInCode(byte* addr) const {
1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788
  // The default name converter is called for unknown code. So we will not try
  // to access any memory.
  return "";
}


//------------------------------------------------------------------------------

Disassembler::Disassembler(const NameConverter& converter)
    : converter_(converter) {}


Disassembler::~Disassembler() {}


int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
1789
                                    byte* instruction) {
1790
  v8::internal::Decoder d(converter_, buffer);
1791 1792 1793 1794
  return d.InstructionDecode(instruction);
}


1795
// The MIPS assembler does not currently use constant pools.
1796
int Disassembler::ConstantPoolSizeAt(byte* instruction) {
1797 1798 1799 1800
  return -1;
}


1801
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
1802 1803
  NameConverter converter;
  Disassembler d(converter);
1804
  for (byte* pc = begin; pc < end;) {
1805 1806
    v8::internal::EmbeddedVector<char, 128> buffer;
    buffer[0] = '\0';
1807
    byte* prev_pc = pc;
1808
    pc += d.InstructionDecode(buffer, pc);
1809 1810
    v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                         *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1811 1812 1813
  }
}

1814

1815 1816 1817 1818
#undef UNSUPPORTED

}  // namespace disasm

1819
#endif  // V8_TARGET_ARCH_MIPS