disasm-ia32.cc 87.1 KB
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// Copyright 2011 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
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#include <assert.h>
#include <stdarg.h>
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#include <stdio.h>
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#if V8_TARGET_ARCH_IA32
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#include "src/base/compiler-specific.h"
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#include "src/disasm.h"
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#include "src/ia32/sse-instr.h"
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namespace disasm {

enum OperandOrder {
  UNSET_OP_ORDER = 0,
  REG_OPER_OP_ORDER,
  OPER_REG_OP_ORDER
};


//------------------------------------------------------------------
// Tables
//------------------------------------------------------------------
struct ByteMnemonic {
  int b;  // -1 terminates, otherwise must be in range (0..255)
  const char* mnem;
  OperandOrder op_order_;
};

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static const ByteMnemonic two_operands_instr[] = {
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    {0x01, "add", OPER_REG_OP_ORDER},  {0x03, "add", REG_OPER_OP_ORDER},
    {0x09, "or", OPER_REG_OP_ORDER},   {0x0B, "or", REG_OPER_OP_ORDER},
    {0x13, "adc", REG_OPER_OP_ORDER},  {0x1B, "sbb", REG_OPER_OP_ORDER},
    {0x21, "and", OPER_REG_OP_ORDER},  {0x23, "and", REG_OPER_OP_ORDER},
    {0x29, "sub", OPER_REG_OP_ORDER},  {0x2A, "subb", REG_OPER_OP_ORDER},
    {0x2B, "sub", REG_OPER_OP_ORDER},  {0x31, "xor", OPER_REG_OP_ORDER},
    {0x33, "xor", REG_OPER_OP_ORDER},  {0x38, "cmpb", OPER_REG_OP_ORDER},
    {0x39, "cmp", OPER_REG_OP_ORDER},  {0x3A, "cmpb", REG_OPER_OP_ORDER},
    {0x3B, "cmp", REG_OPER_OP_ORDER},  {0x84, "test_b", REG_OPER_OP_ORDER},
    {0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER},
    {0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER},
    {0x8B, "mov", REG_OPER_OP_ORDER},  {0x8D, "lea", REG_OPER_OP_ORDER},
    {-1, "", UNSET_OP_ORDER}};
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static const ByteMnemonic zero_operands_instr[] = {
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  {0xC3, "ret", UNSET_OP_ORDER},
  {0xC9, "leave", UNSET_OP_ORDER},
  {0x90, "nop", UNSET_OP_ORDER},
  {0xF4, "hlt", UNSET_OP_ORDER},
  {0xCC, "int3", UNSET_OP_ORDER},
  {0x60, "pushad", UNSET_OP_ORDER},
  {0x61, "popad", UNSET_OP_ORDER},
  {0x9C, "pushfd", UNSET_OP_ORDER},
  {0x9D, "popfd", UNSET_OP_ORDER},
  {0x9E, "sahf", UNSET_OP_ORDER},
  {0x99, "cdq", UNSET_OP_ORDER},
  {0x9B, "fwait", UNSET_OP_ORDER},
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  {0xFC, "cld", UNSET_OP_ORDER},
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  {0xAB, "stos", UNSET_OP_ORDER},
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  {-1, "", UNSET_OP_ORDER}
};


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static const ByteMnemonic call_jump_instr[] = {
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  {0xE8, "call", UNSET_OP_ORDER},
  {0xE9, "jmp", UNSET_OP_ORDER},
  {-1, "", UNSET_OP_ORDER}
};


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static const ByteMnemonic short_immediate_instr[] = {
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  {0x05, "add", UNSET_OP_ORDER},
  {0x0D, "or", UNSET_OP_ORDER},
  {0x15, "adc", UNSET_OP_ORDER},
  {0x25, "and", UNSET_OP_ORDER},
  {0x2D, "sub", UNSET_OP_ORDER},
  {0x35, "xor", UNSET_OP_ORDER},
  {0x3D, "cmp", UNSET_OP_ORDER},
  {-1, "", UNSET_OP_ORDER}
};


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// Generally we don't want to generate these because they are subject to partial
// register stalls.  They are included for completeness and because the cmp
// variant is used by the RecordWrite stub.  Because it does not update the
// register it is not subject to partial register stalls.
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static ByteMnemonic byte_immediate_instr[] = {{0x0C, "or", UNSET_OP_ORDER},
                                              {0x24, "and", UNSET_OP_ORDER},
                                              {0x34, "xor", UNSET_OP_ORDER},
                                              {0x3C, "cmp", UNSET_OP_ORDER},
                                              {-1, "", UNSET_OP_ORDER}};
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static const char* const jump_conditional_mnem[] = {
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  /*0*/ "jo", "jno", "jc", "jnc",
  /*4*/ "jz", "jnz", "jna", "ja",
  /*8*/ "js", "jns", "jpe", "jpo",
  /*12*/ "jl", "jnl", "jng", "jg"
};


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static const char* const set_conditional_mnem[] = {
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  /*0*/ "seto", "setno", "setc", "setnc",
  /*4*/ "setz", "setnz", "setna", "seta",
  /*8*/ "sets", "setns", "setpe", "setpo",
  /*12*/ "setl", "setnl", "setng", "setg"
};


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static const char* const conditional_move_mnem[] = {
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  /*0*/ "cmovo", "cmovno", "cmovc", "cmovnc",
  /*4*/ "cmovz", "cmovnz", "cmovna", "cmova",
  /*8*/ "cmovs", "cmovns", "cmovpe", "cmovpo",
  /*12*/ "cmovl", "cmovnl", "cmovng", "cmovg"
};


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enum InstructionType {
  NO_INSTR,
  ZERO_OPERANDS_INSTR,
  TWO_OPERANDS_INSTR,
  JUMP_CONDITIONAL_SHORT_INSTR,
  REGISTER_INSTR,
  MOVE_REG_INSTR,
  CALL_JUMP_INSTR,
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  SHORT_IMMEDIATE_INSTR,
  BYTE_IMMEDIATE_INSTR
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};


struct InstructionDesc {
  const char* mnem;
  InstructionType type;
  OperandOrder op_order_;
};


class InstructionTable {
 public:
  InstructionTable();
  const InstructionDesc& Get(byte x) const { return instructions_[x]; }
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  static InstructionTable* get_instance() {
    static InstructionTable table;
    return &table;
  }
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 private:
  InstructionDesc instructions_[256];
  void Clear();
  void Init();
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  void CopyTable(const ByteMnemonic bm[], InstructionType type);
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  void SetTableRange(InstructionType type,
                     byte start,
                     byte end,
                     const char* mnem);
  void AddJumpConditionalShort();
};


InstructionTable::InstructionTable() {
  Clear();
  Init();
}


void InstructionTable::Clear() {
  for (int i = 0; i < 256; i++) {
    instructions_[i].mnem = "";
    instructions_[i].type = NO_INSTR;
    instructions_[i].op_order_ = UNSET_OP_ORDER;
  }
}


void InstructionTable::Init() {
  CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
  CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
  CopyTable(call_jump_instr, CALL_JUMP_INSTR);
  CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
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  CopyTable(byte_immediate_instr, BYTE_IMMEDIATE_INSTR);
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  AddJumpConditionalShort();
  SetTableRange(REGISTER_INSTR, 0x40, 0x47, "inc");
  SetTableRange(REGISTER_INSTR, 0x48, 0x4F, "dec");
  SetTableRange(REGISTER_INSTR, 0x50, 0x57, "push");
  SetTableRange(REGISTER_INSTR, 0x58, 0x5F, "pop");
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  SetTableRange(REGISTER_INSTR, 0x91, 0x97, "xchg eax,");  // 0x90 is nop.
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  SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, "mov");
}


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void InstructionTable::CopyTable(const ByteMnemonic bm[],
                                 InstructionType type) {
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  for (int i = 0; bm[i].b >= 0; i++) {
    InstructionDesc* id = &instructions_[bm[i].b];
    id->mnem = bm[i].mnem;
    id->op_order_ = bm[i].op_order_;
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered.
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    id->type = type;
  }
}


void InstructionTable::SetTableRange(InstructionType type,
                                     byte start,
                                     byte end,
                                     const char* mnem) {
  for (byte b = start; b <= end; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered.
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    id->mnem = mnem;
    id->type = type;
  }
}


void InstructionTable::AddJumpConditionalShort() {
  for (byte b = 0x70; b <= 0x7F; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered.
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    id->mnem = jump_conditional_mnem[b & 0x0F];
    id->type = JUMP_CONDITIONAL_SHORT_INSTR;
  }
}


// The IA32 disassembler implementation.
class DisassemblerIA32 {
 public:
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  DisassemblerIA32(
      const NameConverter& converter,
      Disassembler::UnimplementedOpcodeAction unimplemented_opcode_action)
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      : converter_(converter),
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        vex_byte0_(0),
        vex_byte1_(0),
        vex_byte2_(0),
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        instruction_table_(InstructionTable::get_instance()),
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        tmp_buffer_pos_(0),
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        unimplemented_opcode_action_(unimplemented_opcode_action) {
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    tmp_buffer_[0] = '\0';
  }

  virtual ~DisassemblerIA32() {}

  // Writes one disassembled instruction into 'buffer' (0-terminated).
  // Returns the length of the disassembled machine instruction in bytes.
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  int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
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 private:
  const NameConverter& converter_;
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  byte vex_byte0_;  // 0xC4 or 0xC5
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  byte vex_byte1_;
  byte vex_byte2_;  // only for 3 bytes vex prefix
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  InstructionTable* instruction_table_;
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  v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
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  unsigned int tmp_buffer_pos_;
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  Disassembler::UnimplementedOpcodeAction unimplemented_opcode_action_;
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  enum {
    eax = 0,
    ecx = 1,
    edx = 2,
    ebx = 3,
    esp = 4,
    ebp = 5,
    esi = 6,
    edi = 7
  };


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  enum ShiftOpcodeExtension {
    kROL = 0,
    kROR = 1,
    kRCL = 2,
    kRCR = 3,
    kSHL = 4,
    KSHR = 5,
    kSAR = 7
  };

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  bool vex_128() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 4) == 0;
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  }

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  bool vex_none() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 0;
  }

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  bool vex_66() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 1;
  }

  bool vex_f3() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 2;
  }

  bool vex_f2() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
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    return (checked & 3) == 3;
  }

  bool vex_w() {
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    if (vex_byte0_ == 0xC5) return false;
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    return (vex_byte2_ & 0x80) != 0;
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  }

  bool vex_0f() {
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    if (vex_byte0_ == 0xC5) return true;
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    return (vex_byte1_ & 3) == 1;
  }

  bool vex_0f38() {
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    if (vex_byte0_ == 0xC5) return false;
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    return (vex_byte1_ & 3) == 2;
  }

  bool vex_0f3a() {
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    if (vex_byte0_ == 0xC5) return false;
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    return (vex_byte1_ & 3) == 3;
  }

  int vex_vreg() {
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    DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
    byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
    return ~(checked >> 3) & 0xF;
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  }

  char float_size_code() { return "sd"[vex_w()]; }
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  const char* NameOfCPURegister(int reg) const {
    return converter_.NameOfCPURegister(reg);
  }


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  const char* NameOfByteCPURegister(int reg) const {
    return converter_.NameOfByteCPURegister(reg);
  }


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  const char* NameOfXMMRegister(int reg) const {
    return converter_.NameOfXMMRegister(reg);
  }


  const char* NameOfAddress(byte* addr) const {
    return converter_.NameOfAddress(addr);
  }


  // Disassembler helper functions.
  static void get_modrm(byte data, int* mod, int* regop, int* rm) {
    *mod = (data >> 6) & 3;
    *regop = (data & 0x38) >> 3;
    *rm = data & 7;
  }


  static void get_sib(byte data, int* scale, int* index, int* base) {
    *scale = (data >> 6) & 3;
    *index = (data >> 3) & 7;
    *base = data & 7;
  }

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  typedef const char* (DisassemblerIA32::*RegisterNameMapping)(int reg) const;
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  int PrintRightOperandHelper(byte* modrmp, RegisterNameMapping register_name);
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  int PrintRightOperand(byte* modrmp);
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  int PrintRightByteOperand(byte* modrmp);
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  int PrintRightXMMOperand(byte* modrmp);
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  int PrintOperands(const char* mnem, OperandOrder op_order, byte* data);
  int PrintImmediateOp(byte* data);
  int F7Instruction(byte* data);
  int D1D3C1Instruction(byte* data);
  int JumpShort(byte* data);
  int JumpConditional(byte* data, const char* comment);
  int JumpConditionalShort(byte* data, const char* comment);
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  int SetCC(byte* data);
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  int CMov(byte* data);
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  int FPUInstruction(byte* data);
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  int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
  int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
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  int AVXInstruction(byte* data);
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  PRINTF_FORMAT(2, 3) void AppendToBuffer(const char* format, ...);
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  void UnimplementedInstruction() {
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    if (unimplemented_opcode_action_ ==
        Disassembler::kAbortOnUnimplementedOpcode) {
      FATAL("Unimplemented instruction in disassembler");
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    } else {
      AppendToBuffer("'Unimplemented Instruction'");
    }
  }
};


void DisassemblerIA32::AppendToBuffer(const char* format, ...) {
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  v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
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  va_list args;
  va_start(args, format);
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  int result = v8::internal::VSNPrintF(buf, format, args);
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  va_end(args);
  tmp_buffer_pos_ += result;
}

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int DisassemblerIA32::PrintRightOperandHelper(
    byte* modrmp,
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    RegisterNameMapping direct_register_name) {
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  int mod, regop, rm;
  get_modrm(*modrmp, &mod, &regop, &rm);
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  RegisterNameMapping register_name = (mod == 3) ? direct_register_name :
      &DisassemblerIA32::NameOfCPURegister;
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  switch (mod) {
    case 0:
      if (rm == ebp) {
        int32_t disp = *reinterpret_cast<int32_t*>(modrmp+1);
        AppendToBuffer("[0x%x]", disp);
        return 5;
      } else if (rm == esp) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        if (index == esp && base == esp && scale == 0 /*times_1*/) {
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          AppendToBuffer("[%s]", (this->*register_name)(rm));
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          return 2;
        } else if (base == ebp) {
          int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
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          AppendToBuffer("[%s*%d%s0x%x]",
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                         (this->*register_name)(index),
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                         1 << scale,
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                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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          return 6;
        } else if (index != esp && base != ebp) {
          // [base+index*scale]
          AppendToBuffer("[%s+%s*%d]",
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                         (this->*register_name)(base),
                         (this->*register_name)(index),
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                         1 << scale);
          return 2;
        } else {
          UnimplementedInstruction();
          return 1;
        }
      } else {
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        AppendToBuffer("[%s]", (this->*register_name)(rm));
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        return 1;
      }
      break;
    case 1:  // fall through
    case 2:
      if (rm == esp) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
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        int disp = mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 2)
                            : *reinterpret_cast<int8_t*>(modrmp + 2);
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        if (index == base && index == rm /*esp*/ && scale == 0 /*times_1*/) {
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          AppendToBuffer("[%s%s0x%x]",
                         (this->*register_name)(rm),
                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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        } else {
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          AppendToBuffer("[%s+%s*%d%s0x%x]",
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                         (this->*register_name)(base),
                         (this->*register_name)(index),
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                         1 << scale,
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                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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        }
        return mod == 2 ? 6 : 3;
      } else {
        // No sib.
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        int disp = mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 1)
                            : *reinterpret_cast<int8_t*>(modrmp + 1);
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        AppendToBuffer("[%s%s0x%x]",
                       (this->*register_name)(rm),
                       disp < 0 ? "-" : "+",
                       disp < 0 ? -disp : disp);
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        return mod == 2 ? 5 : 2;
      }
      break;
    case 3:
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      AppendToBuffer("%s", (this->*register_name)(rm));
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      return 1;
    default:
      UnimplementedInstruction();
      return 1;
  }
  UNREACHABLE();
}


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int DisassemblerIA32::PrintRightOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfCPURegister);
}


int DisassemblerIA32::PrintRightByteOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerIA32::NameOfByteCPURegister);
}


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int DisassemblerIA32::PrintRightXMMOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerIA32::NameOfXMMRegister);
}


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// Returns number of bytes used including the current *data.
// Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
int DisassemblerIA32::PrintOperands(const char* mnem,
                                    OperandOrder op_order,
                                    byte* data) {
  byte modrm = *data;
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int advance = 0;
  switch (op_order) {
    case REG_OPER_OP_ORDER: {
      AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
      advance = PrintRightOperand(data);
      break;
    }
    case OPER_REG_OP_ORDER: {
      AppendToBuffer("%s ", mnem);
      advance = PrintRightOperand(data);
      AppendToBuffer(",%s", NameOfCPURegister(regop));
      break;
    }
    default:
      UNREACHABLE();
      break;
  }
  return advance;
}


// Returns number of bytes used by machine instruction, including *data byte.
// Writes immediate instructions to 'tmp_buffer_'.
int DisassemblerIA32::PrintImmediateOp(byte* data) {
  bool sign_extension_bit = (*data & 0x02) != 0;
  byte modrm = *(data+1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  const char* mnem = "Imm???";
  switch (regop) {
    case 0: mnem = "add"; break;
    case 1: mnem = "or"; break;
    case 2: mnem = "adc"; break;
    case 4: mnem = "and"; break;
    case 5: mnem = "sub"; break;
    case 6: mnem = "xor"; break;
    case 7: mnem = "cmp"; break;
    default: UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(data+1);
  if (sign_extension_bit) {
    AppendToBuffer(",0x%x", *(data + 1 + count));
    return 1 + count + 1 /*int8*/;
  } else {
    AppendToBuffer(",0x%x", *reinterpret_cast<int32_t*>(data + 1 + count));
    return 1 + count + 4 /*int32_t*/;
  }
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::F7Instruction(byte* data) {
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  DCHECK_EQ(0xF7, *data);
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  byte modrm = *++data;
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  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
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  const char* mnem = nullptr;
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  switch (regop) {
    case 0:
      mnem = "test";
      break;
    case 2:
      mnem = "not";
      break;
    case 3:
      mnem = "neg";
      break;
    case 4:
      mnem = "mul";
      break;
    case 5:
      mnem = "imul";
      break;
    case 6:
      mnem = "div";
      break;
    case 7:
      mnem = "idiv";
      break;
    default:
      UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(data);
  if (regop == 0) {
    AppendToBuffer(",0x%x", *reinterpret_cast<int32_t*>(data + count));
    count += 4;
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  }
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  return 1 + count;
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}

620

621 622
int DisassemblerIA32::D1D3C1Instruction(byte* data) {
  byte op = *data;
623
  DCHECK(op == 0xD1 || op == 0xD3 || op == 0xC1);
624
  byte modrm = *++data;
625 626 627
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int imm8 = -1;
628
  const char* mnem = nullptr;
629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658
  switch (regop) {
    case kROL:
      mnem = "rol";
      break;
    case kROR:
      mnem = "ror";
      break;
    case kRCL:
      mnem = "rcl";
      break;
    case kRCR:
      mnem = "rcr";
      break;
    case kSHL:
      mnem = "shl";
      break;
    case KSHR:
      mnem = "shr";
      break;
    case kSAR:
      mnem = "sar";
      break;
    default:
      UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(data);
  if (op == 0xD1) {
    imm8 = 1;
  } else if (op == 0xC1) {
659
    imm8 = *(data + 1);
660 661 662 663 664 665
    count++;
  } else if (op == 0xD3) {
    // Shift/rotate by cl.
  }
  if (imm8 >= 0) {
    AppendToBuffer(",%d", imm8);
666
  } else {
667
    AppendToBuffer(",cl");
668
  }
669
  return 1 + count;
670 671 672 673 674
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpShort(byte* data) {
675
  DCHECK_EQ(0xEB, *data);
676 677 678 679 680 681 682 683 684
  byte b = *(data+1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  AppendToBuffer("jmp %s", NameOfAddress(dest));
  return 2;
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditional(byte* data, const char* comment) {
685
  DCHECK_EQ(0x0F, *data);
686 687 688 689
  byte cond = *(data+1) & 0x0F;
  byte* dest = data + *reinterpret_cast<int32_t*>(data+2) + 6;
  const char* mnem = jump_conditional_mnem[cond];
  AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
690
  if (comment != nullptr) {
691 692 693 694 695 696 697 698 699 700 701 702 703
    AppendToBuffer(", %s", comment);
  }
  return 6;  // includes 0x0F
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditionalShort(byte* data, const char* comment) {
  byte cond = *data & 0x0F;
  byte b = *(data+1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  const char* mnem = jump_conditional_mnem[cond];
  AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
704
  if (comment != nullptr) {
705 706 707 708 709 710
    AppendToBuffer(", %s", comment);
  }
  return 2;
}


711 712
// Returns number of bytes used, including *data.
int DisassemblerIA32::SetCC(byte* data) {
713
  DCHECK_EQ(0x0F, *data);
714 715 716 717
  byte cond = *(data+1) & 0x0F;
  const char* mnem = set_conditional_mnem[cond];
  AppendToBuffer("%s ", mnem);
  PrintRightByteOperand(data+2);
718
  return 3;  // Includes 0x0F.
719 720 721
}


722 723
// Returns number of bytes used, including *data.
int DisassemblerIA32::CMov(byte* data) {
724
  DCHECK_EQ(0x0F, *data);
725 726 727 728 729 730
  byte cond = *(data + 1) & 0x0F;
  const char* mnem = conditional_move_mnem[cond];
  int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2);
  return 2 + op_size;  // includes 0x0F
}

731
const char* sf_str[4] = {"", "rl", "ra", "ll"};
732

733 734 735
int DisassemblerIA32::AVXInstruction(byte* data) {
  byte opcode = *data;
  byte* current = data + 1;
736 737 738 739 740 741 742 743 744
  if (vex_66() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x99:
        AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
745
      case 0xA9:
746 747 748 749
        AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
750
      case 0xB9:
751 752 753 754
        AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
755
      case 0x9B:
756 757 758 759
        AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
760
      case 0xAB:
761 762 763 764
        AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
765
      case 0xBB:
766 767 768 769
        AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
770
      case 0x9D:
771 772 773 774
        AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
775
      case 0xAD:
776 777 778 779
        AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
780
      case 0xBD:
781 782 783 784
        AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
785
      case 0x9F:
786 787 788 789
        AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
790
      case 0xAF:
791 792 793 794
        AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
795
      case 0xBF:
796 797 798 799
        AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
800
      case 0xF7:
801 802 803 804
        AppendToBuffer("shlx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
805 806 807 808 809 810 811 812 813
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, \
                                 opcode)                                    \
  case 0x##opcode: {                                                        \
    AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop),    \
                   NameOfXMMRegister(vvvv));                                \
    current += PrintRightXMMOperand(current);                               \
    break;                                                                  \
  }

814
        SSSE3_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
815 816
        SSE4_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
#undef DECLARE_SSE_AVX_DIS_CASE
817 818 819 820 821 822 823 824 825 826
#define DECLARE_SSE_AVX_RM_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, \
                                    opcode)                                    \
  case 0x##opcode: {                                                           \
    AppendToBuffer("v" #instruction " %s,", NameOfXMMRegister(regop));         \
    current += PrintRightXMMOperand(current);                                  \
    break;                                                                     \
  }

        SSE4_RM_INSTRUCTION_LIST(DECLARE_SSE_AVX_RM_DIS_CASE)
#undef DECLARE_SSE_AVX_RM_DIS_CASE
827 828 829
      default:
        UnimplementedInstruction();
    }
830 831 832 833
  } else if (vex_66() && vex_0f3a()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
834 835 836 837 838 839 840
      case 0x0E:
        AppendToBuffer("vpblendw %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<uint8_t*>(current));
        current++;
        break;
841 842 843 844 845 846 847
      case 0x0F:
        AppendToBuffer("vpalignr %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<uint8_t*>(current));
        current++;
        break;
848 849 850 851 852 853 854 855 856 857 858 859 860 861
      case 0x14:
        AppendToBuffer("vpextrb ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
                       *reinterpret_cast<int8_t*>(current));
        current++;
        break;
      case 0x15:
        AppendToBuffer("vpextrw ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
                       *reinterpret_cast<int8_t*>(current));
        current++;
        break;
862 863 864 865 866 867 868
      case 0x16:
        AppendToBuffer("vpextrd ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
                       *reinterpret_cast<int8_t*>(current));
        current++;
        break;
869 870 871 872 873 874 875
      case 0x20:
        AppendToBuffer("vpinsrb %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
        current++;
        break;
876 877 878 879 880 881 882
      case 0x21:
        AppendToBuffer("vinsertps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
        current++;
        break;
883 884 885 886 887 888 889 890 891 892
      case 0x22:
        AppendToBuffer("vpinsrd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
        current++;
        break;
      default:
        UnimplementedInstruction();
    }
893
  } else if (vex_f2() && vex_0f()) {
894 895 896
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
897 898 899 900 901
      case 0x51:
        AppendToBuffer("vsqrtsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
902 903 904 905 906 907 908 909 910 911
      case 0x58:
        AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
912
      case 0x5C:
913 914 915 916
        AppendToBuffer("vsubsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
917
      case 0x5D:
918 919 920 921
        AppendToBuffer("vminsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
922
      case 0x5E:
923 924 925 926
        AppendToBuffer("vdivsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
927
      case 0x5F:
928 929 930 931
        AppendToBuffer("vmaxsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
932 933 934 935 936 937
      case 0x70:
        AppendToBuffer("vpshuflw %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
        current++;
        break;
938 939 940 941 942
      case 0x7C:
        AppendToBuffer("vhaddps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
943 944 945
      default:
        UnimplementedInstruction();
    }
946 947 948 949
  } else if (vex_f3() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
950 951 952 953 954
      case 0x51:
        AppendToBuffer("vsqrtss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
955 956 957 958 959 960 961 962 963 964
      case 0x58:
        AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
965
      case 0x5B:
966 967 968
        AppendToBuffer("vcvttps2dq %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
969
      case 0x5C:
970 971 972 973
        AppendToBuffer("vsubss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
974
      case 0x5D:
975 976 977 978
        AppendToBuffer("vminss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
979
      case 0x5E:
980 981 982 983
        AppendToBuffer("vdivss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
984
      case 0x5F:
985 986 987 988
        AppendToBuffer("vmaxss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
989 990 991 992
      case 0x6f:
        AppendToBuffer("vmovdqu %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        break;
993 994 995 996 997 998
      case 0x70:
        AppendToBuffer("vpshufhw %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
        current++;
        break;
999 1000 1001 1002 1003
      case 0x7f:
        AppendToBuffer("vmovdqu ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
1004 1005 1006
      default:
        UnimplementedInstruction();
    }
1007 1008 1009 1010 1011
  } else if (vex_none() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    const char* mnem = "?";
    switch (opcode) {
1012
      case 0xF2:
1013 1014 1015 1016
        AppendToBuffer("andn %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1017
      case 0xF5:
1018 1019 1020 1021
        AppendToBuffer("bzhi %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
1022
      case 0xF7:
1023 1024 1025 1026
        AppendToBuffer("bextr %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
1027
      case 0xF3:
1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
        switch (regop) {
          case 1:
            mnem = "blsr";
            break;
          case 2:
            mnem = "blsmsk";
            break;
          case 3:
            mnem = "blsi";
            break;
          default:
            UnimplementedInstruction();
        }
        AppendToBuffer("%s %s,", mnem, NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        mnem = "?";
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1052
      case 0xF5:
1053 1054 1055 1056
        AppendToBuffer("pdep %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1057
      case 0xF6:
1058 1059 1060 1061
        AppendToBuffer("mulx %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1062
      case 0xF7:
1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
        AppendToBuffer("shrx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f3() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1074
      case 0xF5:
1075 1076 1077 1078
        AppendToBuffer("pext %s,%s,", NameOfCPURegister(regop),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
1079
      case 0xF7:
1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
        AppendToBuffer("sarx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f3a()) {
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1091
      case 0xF0:
1092 1093
        AppendToBuffer("rorx %s,", NameOfCPURegister(regop));
        current += PrintRightOperand(current);
1094
        AppendToBuffer(",%d", *current & 0x1F);
1095 1096 1097 1098 1099
        current += 1;
        break;
      default:
        UnimplementedInstruction();
    }
1100 1101 1102 1103
  } else if (vex_none() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
1104 1105 1106 1107
      case 0x28:
        AppendToBuffer("vmovaps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1108 1109 1110 1111 1112 1113 1114 1115
      case 0x52:
        AppendToBuffer("vrsqrtps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x53:
        AppendToBuffer("vrcpps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1116 1117 1118 1119 1120 1121 1122 1123 1124 1125
      case 0x54:
        AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x57:
        AppendToBuffer("vxorps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1126 1127 1128 1129 1130 1131 1132 1133 1134 1135
      case 0x58:
        AppendToBuffer("vaddps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1136 1137 1138 1139
      case 0x5B:
        AppendToBuffer("vcvtdq2ps %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159
      case 0x5C:
        AppendToBuffer("vsubps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5D:
        AppendToBuffer("vminps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5E:
        AppendToBuffer("vdivps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5F:
        AppendToBuffer("vmaxps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1160 1161 1162 1163 1164 1165 1166 1167 1168 1169
      case 0xC2: {
        const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                         "neq", "nlt", "nle", "ord"};
        AppendToBuffer("vcmpps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(", (%s)", pseudo_op[*current]);
        current++;
        break;
      }
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      case 0xC6:
        AppendToBuffer("vshufps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(", %d", (*current) & 3);
        current += 1;
        break;
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      default:
        UnimplementedInstruction();
    }
  } else if (vex_66() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x54:
        AppendToBuffer("vandpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x57:
        AppendToBuffer("vxorpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
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      case 0x58:
        AppendToBuffer("vaddpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5C:
        AppendToBuffer("vsubpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5D:
        AppendToBuffer("vminpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5E:
        AppendToBuffer("vdivpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5F:
        AppendToBuffer("vmaxpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
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      case 0x6E:
        AppendToBuffer("vmovd %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        break;
      case 0x70:
        AppendToBuffer("vpshufd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
        current++;
        break;
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      case 0x71:
        AppendToBuffer("vps%sw %s,%s", sf_str[regop / 2],
                       NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
        current++;
        AppendToBuffer(",%u", *current++);
        break;
      case 0x72:
        AppendToBuffer("vps%sd %s,%s", sf_str[regop / 2],
                       NameOfXMMRegister(vvvv), NameOfXMMRegister(rm));
        current++;
        AppendToBuffer(",%u", *current++);
        break;
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      case 0x7E:
        AppendToBuffer("vmovd ");
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
        break;
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      case 0xC4:
        AppendToBuffer("vpinsrw %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightOperand(current);
        AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(current));
        current++;
        break;
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#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, opcode) \
  case 0x##opcode: {                                                      \
    AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop),  \
                   NameOfXMMRegister(vvvv));                              \
    current += PrintRightXMMOperand(current);                             \
    break;                                                                \
  }

        SSE2_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
#undef DECLARE_SSE_AVX_DIS_CASE
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      default:
        UnimplementedInstruction();
    }
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  } else {
    UnimplementedInstruction();
  }

  return static_cast<int>(current - data);
}


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// Returns number of bytes used, including *data.
int DisassemblerIA32::FPUInstruction(byte* data) {
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  byte escape_opcode = *data;
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  DCHECK_EQ(0xD8, escape_opcode & 0xF8);
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  byte modrm_byte = *(data+1);

  if (modrm_byte >= 0xC0) {
    return RegisterFPUInstruction(escape_opcode, modrm_byte);
  } else {
    return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
  }
}

int DisassemblerIA32::MemoryFPUInstruction(int escape_opcode,
                                           int modrm_byte,
                                           byte* modrm_start) {
  const char* mnem = "?";
  int regop = (modrm_byte >> 3) & 0x7;  // reg/op field of modrm byte.
  switch (escape_opcode) {
    case 0xD9: switch (regop) {
        case 0: mnem = "fld_s"; break;
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        case 2: mnem = "fst_s"; break;
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        case 3: mnem = "fstp_s"; break;
        case 7: mnem = "fstcw"; break;
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        default: UnimplementedInstruction();
      }
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      break;

    case 0xDB: switch (regop) {
        case 0: mnem = "fild_s"; break;
        case 1: mnem = "fisttp_s"; break;
        case 2: mnem = "fist_s"; break;
        case 3: mnem = "fistp_s"; break;
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        default: UnimplementedInstruction();
      }
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      break;

    case 0xDD: switch (regop) {
        case 0: mnem = "fld_d"; break;
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        case 1: mnem = "fisttp_d"; break;
        case 2: mnem = "fst_d"; break;
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        case 3: mnem = "fstp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDF: switch (regop) {
        case 5: mnem = "fild_d"; break;
        case 7: mnem = "fistp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    default: UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(modrm_start);
  return count + 1;
}

int DisassemblerIA32::RegisterFPUInstruction(int escape_opcode,
                                             byte modrm_byte) {
  bool has_register = false;  // Is the FPU register encoded in modrm_byte?
  const char* mnem = "?";

  switch (escape_opcode) {
    case 0xD8:
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      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "fadd_i"; break;
        case 0xE0: mnem = "fsub_i"; break;
        case 0xC8: mnem = "fmul_i"; break;
        case 0xF0: mnem = "fdiv_i"; break;
        default: UnimplementedInstruction();
      }
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      break;

    case 0xD9:
      switch (modrm_byte & 0xF8) {
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        case 0xC0:
          mnem = "fld";
          has_register = true;
          break;
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        case 0xC8:
          mnem = "fxch";
          has_register = true;
          break;
        default:
          switch (modrm_byte) {
            case 0xE0: mnem = "fchs"; break;
            case 0xE1: mnem = "fabs"; break;
            case 0xE4: mnem = "ftst"; break;
            case 0xE8: mnem = "fld1"; break;
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            case 0xEB: mnem = "fldpi"; break;
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            case 0xED: mnem = "fldln2"; break;
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            case 0xEE: mnem = "fldz"; break;
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            case 0xF0: mnem = "f2xm1"; break;
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            case 0xF1: mnem = "fyl2x"; break;
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            case 0xF4: mnem = "fxtract"; break;
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            case 0xF5: mnem = "fprem1"; break;
            case 0xF7: mnem = "fincstp"; break;
            case 0xF8: mnem = "fprem"; break;
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            case 0xFC: mnem = "frndint"; break;
            case 0xFD: mnem = "fscale"; break;
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            case 0xFE: mnem = "fsin"; break;
            case 0xFF: mnem = "fcos"; break;
            default: UnimplementedInstruction();
          }
      }
      break;

    case 0xDA:
      if (modrm_byte == 0xE9) {
        mnem = "fucompp";
      } else {
        UnimplementedInstruction();
      }
      break;

    case 0xDB:
      if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomi";
        has_register = true;
      } else if (modrm_byte  == 0xE2) {
        mnem = "fclex";
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      } else if (modrm_byte == 0xE3) {
        mnem = "fninit";
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      } else {
        UnimplementedInstruction();
      }
      break;

    case 0xDC:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "fadd"; break;
        case 0xE8: mnem = "fsub"; break;
        case 0xC8: mnem = "fmul"; break;
        case 0xF8: mnem = "fdiv"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDD:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "ffree"; break;
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        case 0xD0: mnem = "fst"; break;
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        case 0xD8: mnem = "fstp"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDE:
      if (modrm_byte  == 0xD9) {
        mnem = "fcompp";
      } else {
        has_register = true;
        switch (modrm_byte & 0xF8) {
          case 0xC0: mnem = "faddp"; break;
          case 0xE8: mnem = "fsubp"; break;
          case 0xC8: mnem = "fmulp"; break;
          case 0xF8: mnem = "fdivp"; break;
          default: UnimplementedInstruction();
        }
      }
      break;

    case 0xDF:
      if (modrm_byte == 0xE0) {
        mnem = "fnstsw_ax";
      } else if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomip";
        has_register = true;
      }
      break;

    default: UnimplementedInstruction();
  }

  if (has_register) {
    AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
  } else {
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    AppendToBuffer("%s", mnem);
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  }
  return 2;
}

// Mnemonics for instructions 0xF0 byte.
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// Returns nullptr if the instruction is not handled here.
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static const char* F0Mnem(byte f0byte) {
  switch (f0byte) {
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    case 0x0B:
      return "ud2";
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    case 0x18:
      return "prefetch";
    case 0xA2:
      return "cpuid";
    case 0xBE:
      return "movsx_b";
    case 0xBF:
      return "movsx_w";
    case 0xB6:
      return "movzx_b";
    case 0xB7:
      return "movzx_w";
    case 0xAF:
      return "imul";
    case 0xA4:
      return "shld";
    case 0xA5:
      return "shld";
    case 0xAD:
      return "shrd";
    case 0xAC:
      return "shrd";  // 3-operand version.
    case 0xAB:
      return "bts";
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    case 0xB0:
      return "cmpxchg_b";
    case 0xB1:
      return "cmpxchg";
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    case 0xBC:
      return "bsf";
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    case 0xBD:
      return "bsr";
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    case 0xC7:
      return "cmpxchg8b";
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    default:
      return nullptr;
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  }
}


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// Disassembled instruction '*instr' and writes it into 'out_buffer'.
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int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
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                                        byte* instr) {
  tmp_buffer_pos_ = 0;  // starting to write as position 0
  byte* data = instr;
  // Check for hints.
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  const char* branch_hint = nullptr;
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  // We use these two prefixes only with branch prediction
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  if (*data == 0x3E /*ds*/) {
    branch_hint = "predicted taken";
    data++;
  } else if (*data == 0x2E /*cs*/) {
    branch_hint = "predicted not taken";
    data++;
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  } else if (*data == 0xC4 && *(data + 1) >= 0xC0) {
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    vex_byte0_ = *data;
    vex_byte1_ = *(data + 1);
    vex_byte2_ = *(data + 2);
    data += 3;
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  } else if (*data == 0xC5 && *(data + 1) >= 0xC0) {
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    vex_byte0_ = *data;
    vex_byte1_ = *(data + 1);
    data += 2;
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  } else if (*data == 0xF0 /*lock*/) {
    AppendToBuffer("lock ");
    data++;
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  }
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  bool processed = true;  // Will be set to false if the current instruction
                          // is not in 'instructions' table.
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  // Decode AVX instructions.
  if (vex_byte0_ != 0) {
    data += AVXInstruction(data);
  } else {
    const InstructionDesc& idesc = instruction_table_->Get(*data);
    switch (idesc.type) {
      case ZERO_OPERANDS_INSTR:
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        AppendToBuffer("%s", idesc.mnem);
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        data++;
        break;
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      case TWO_OPERANDS_INSTR:
        data++;
        data += PrintOperands(idesc.mnem, idesc.op_order_, data);
        break;
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      case JUMP_CONDITIONAL_SHORT_INSTR:
        data += JumpConditionalShort(data, branch_hint);
        break;
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      case REGISTER_INSTR:
        AppendToBuffer("%s %s", idesc.mnem, NameOfCPURegister(*data & 0x07));
        data++;
        break;
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      case MOVE_REG_INSTR: {
        byte* addr =
            reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data + 1));
        AppendToBuffer("mov %s,%s", NameOfCPURegister(*data & 0x07),
                       NameOfAddress(addr));
        data += 5;
        break;
      }
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      case CALL_JUMP_INSTR: {
        byte* addr = data + *reinterpret_cast<int32_t*>(data + 1) + 5;
        AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
        data += 5;
        break;
      }
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      case SHORT_IMMEDIATE_INSTR: {
        byte* addr =
            reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data + 1));
        AppendToBuffer("%s eax,%s", idesc.mnem, NameOfAddress(addr));
        data += 5;
        break;
      }
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      case BYTE_IMMEDIATE_INSTR: {
        AppendToBuffer("%s al,0x%x", idesc.mnem, data[1]);
        data += 2;
        break;
      }
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      case NO_INSTR:
        processed = false;
        break;
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      default:
        UNIMPLEMENTED();  // This type is not implemented.
    }
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  }
  //----------------------------
  if (!processed) {
    switch (*data) {
      case 0xC2:
        AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data+1));
        data += 3;
        break;

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      case 0x6B: {
        data++;
        data += PrintOperands("imul", REG_OPER_OP_ORDER, data);
        AppendToBuffer(",%d", *data);
        data++;
      } break;

      case 0x69: {
        data++;
        data += PrintOperands("imul", REG_OPER_OP_ORDER, data);
        AppendToBuffer(",%d", *reinterpret_cast<int32_t*>(data));
        data += 4;
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        }
        break;

      case 0xF6:
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        { data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          if (regop == eax) {
            AppendToBuffer("test_b ");
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            data += PrintRightByteOperand(data);
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            int32_t imm = *data;
            AppendToBuffer(",0x%x", imm);
            data++;
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          } else {
            UnimplementedInstruction();
          }
        }
        break;

      case 0x81:  // fall through
      case 0x83:  // 0x81 with sign extension bit set
        data += PrintImmediateOp(data);
        break;

      case 0x0F:
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        { byte f0byte = data[1];
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          const char* f0mnem = F0Mnem(f0byte);
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          if (f0byte == 0x18) {
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            data += 2;
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            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            const char* suffix[] = {"nta", "1", "2", "3"};
            AppendToBuffer("%s%s ", f0mnem, suffix[regop & 0x03]);
            data += PrintRightOperand(data);
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          } else if (f0byte == 0x1F && data[2] == 0) {
            AppendToBuffer("nop");  // 3 byte nop.
            data += 3;
          } else if (f0byte == 0x1F && data[2] == 0x40 && data[3] == 0) {
            AppendToBuffer("nop");  // 4 byte nop.
            data += 4;
          } else if (f0byte == 0x1F && data[2] == 0x44 && data[3] == 0 &&
                     data[4] == 0) {
            AppendToBuffer("nop");  // 5 byte nop.
            data += 5;
          } else if (f0byte == 0x1F && data[2] == 0x80 && data[3] == 0 &&
                     data[4] == 0 && data[5] == 0 && data[6] == 0) {
            AppendToBuffer("nop");  // 7 byte nop.
            data += 7;
          } else if (f0byte == 0x1F && data[2] == 0x84 && data[3] == 0 &&
                     data[4] == 0 && data[5] == 0 && data[6] == 0 &&
                     data[7] == 0) {
            AppendToBuffer("nop");  // 8 byte nop.
            data += 8;
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          } else if (f0byte == 0x0B || f0byte == 0xA2 || f0byte == 0x31) {
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            AppendToBuffer("%s", f0mnem);
            data += 2;
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          } else if (f0byte == 0x28) {
            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movaps %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
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          } else if (f0byte == 0x10 || f0byte == 0x11) {
            data += 2;
            // movups xmm, xmm/m128
            // movups xmm/m128, xmm
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movups ");
            if (f0byte == 0x11) {
              data += PrintRightXMMOperand(data);
              AppendToBuffer(",%s", NameOfXMMRegister(regop));
            } else {
              AppendToBuffer("%s,", NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
            }
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          } else if (f0byte == 0x2E) {
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            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("ucomiss %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
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          } else if (f0byte >= 0x52 && f0byte <= 0x5F) {
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            const char* const pseudo_op[] = {
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                "rsqrtps", "rcpps", "andps", "andnps",   "orps",
                "xorps",   "addps", "mulps", "cvtps2pd", "cvtdq2ps",
                "subps",   "minps", "divps", "maxps",
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            };
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            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            AppendToBuffer("%s %s,", pseudo_op[f0byte - 0x52],
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                           NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
          } else if (f0byte == 0x50) {
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            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            AppendToBuffer("movmskps %s,%s",
                           NameOfCPURegister(regop),
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                           NameOfXMMRegister(rm));
            data++;
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          } else if (f0byte == 0xC2) {
            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            const char* const pseudo_op[] = {"eq",  "lt",  "le",  "unord",
                                             "neq", "nlt", "nle", "ord"};
            AppendToBuffer("cmpps %s, ", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
            AppendToBuffer(", (%s)", pseudo_op[*data]);
            data++;
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          } else if (f0byte== 0xC6) {
            // shufps xmm, xmm/m128, imm8
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            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            int8_t imm8 = static_cast<int8_t>(data[1]);
            AppendToBuffer("shufps %s,%s,%d",
                            NameOfXMMRegister(rm),
                            NameOfXMMRegister(regop),
                            static_cast<int>(imm8));
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            data += 2;
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          } else if (f0byte >= 0xC8 && f0byte <= 0xCF) {
            // bswap
            data += 2;
            int reg = f0byte - 0xC8;
            AppendToBuffer("bswap %s", NameOfCPURegister(reg));
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          } else if ((f0byte & 0xF0) == 0x80) {
            data += JumpConditional(data, branch_hint);
          } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 ||
                     f0byte == 0xB7 || f0byte == 0xAF) {
            data += 2;
            data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data);
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          } else if ((f0byte & 0xF0) == 0x90) {
            data += SetCC(data);
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          } else if ((f0byte & 0xF0) == 0x40) {
            data += CMov(data);
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          } else if (f0byte == 0xA4 || f0byte == 0xAC) {
            // shld, shrd
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            data += 2;
            AppendToBuffer("%s ", f0mnem);
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            int8_t imm8 = static_cast<int8_t>(data[1]);
            data += 2;
            AppendToBuffer("%s,%s,%d", NameOfCPURegister(rm),
                           NameOfCPURegister(regop), static_cast<int>(imm8));
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          } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
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            // shrd_cl, shld_cl, bts
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            data += 2;
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            AppendToBuffer("%s ", f0mnem);
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightOperand(data);
            if (f0byte == 0xAB) {
              AppendToBuffer(",%s", NameOfCPURegister(regop));
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            } else {
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              AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
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            }
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          } else if (f0byte == 0xB0) {
            // cmpxchg_b
            data += 2;
            AppendToBuffer("%s ", f0mnem);
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightOperand(data);
            AppendToBuffer(",%s", NameOfByteCPURegister(regop));
          } else if (f0byte == 0xB1) {
            // cmpxchg
            data += 2;
            data += PrintOperands(f0mnem, OPER_REG_OP_ORDER, data);
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          } else if (f0byte == 0xBC) {
            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("%s %s,", f0mnem, NameOfCPURegister(regop));
            data += PrintRightOperand(data);
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          } else if (f0byte == 0xBD) {
            data += 2;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("%s %s,", f0mnem, NameOfCPURegister(regop));
            data += PrintRightOperand(data);
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          } else if (f0byte == 0xC7) {
            // cmpxchg8b
            data += 2;
            AppendToBuffer("%s ", f0mnem);
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightOperand(data);
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          } else if (f0byte == 0xAE && (data[2] & 0xF8) == 0xE8) {
            AppendToBuffer("lfence");
            data += 3;
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          } else {
            UnimplementedInstruction();
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          }
        }
        break;

      case 0x8F:
        { data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          if (regop == eax) {
            AppendToBuffer("pop ");
            data += PrintRightOperand(data);
          }
        }
        break;

      case 0xFF:
        { data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
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          const char* mnem = nullptr;
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          switch (regop) {
            case esi: mnem = "push"; break;
            case eax: mnem = "inc"; break;
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            case ecx: mnem = "dec"; break;
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            case edx: mnem = "call"; break;
            case esp: mnem = "jmp"; break;
            default: mnem = "???";
          }
          AppendToBuffer("%s ", mnem);
          data += PrintRightOperand(data);
        }
        break;

      case 0xC7:  // imm32, fall through
      case 0xC6:  // imm8
        { bool is_byte = *data == 0xC6;
          data++;
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          if (is_byte) {
            AppendToBuffer("%s ", "mov_b");
            data += PrintRightByteOperand(data);
            int32_t imm = *data;
            AppendToBuffer(",0x%x", imm);
            data++;
          } else {
            AppendToBuffer("%s ", "mov");
            data += PrintRightOperand(data);
            int32_t imm = *reinterpret_cast<int32_t*>(data);
            AppendToBuffer(",0x%x", imm);
            data += 4;
          }
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        }
        break;

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      case 0x80:
        { data++;
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          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
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          const char* mnem = nullptr;
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          switch (regop) {
            case 5:  mnem = "subb"; break;
            case 7:  mnem = "cmpb"; break;
            default: UnimplementedInstruction();
          }
          AppendToBuffer("%s ", mnem);
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          data += PrintRightByteOperand(data);
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          int32_t imm = *data;
          AppendToBuffer(",0x%x", imm);
          data++;
        }
        break;

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      case 0x88:  // 8bit, fall through
      case 0x89:  // 32bit
        { bool is_byte = *data == 0x88;
          int mod, regop, rm;
          data++;
          get_modrm(*data, &mod, &regop, &rm);
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          if (is_byte) {
            AppendToBuffer("%s ", "mov_b");
            data += PrintRightByteOperand(data);
            AppendToBuffer(",%s", NameOfByteCPURegister(regop));
          } else {
            AppendToBuffer("%s ", "mov");
            data += PrintRightOperand(data);
            AppendToBuffer(",%s", NameOfCPURegister(regop));
          }
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        }
        break;

      case 0x66:  // prefix
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        while (*data == 0x66) data++;
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        if (*data == 0xF && data[1] == 0x1F) {
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          AppendToBuffer("nop");  // 0x66 prefix
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        } else if (*data == 0x39) {
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          data++;
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          data += PrintOperands("cmpw", OPER_REG_OP_ORDER, data);
        } else if (*data == 0x3B) {
          data++;
          data += PrintOperands("cmpw", REG_OPER_OP_ORDER, data);
        } else if (*data == 0x81) {
          data++;
          AppendToBuffer("cmpw ");
          data += PrintRightOperand(data);
          int imm = *reinterpret_cast<int16_t*>(data);
          AppendToBuffer(",0x%x", imm);
          data += 2;
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        } else if (*data == 0x87) {
          data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
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          AppendToBuffer("xchg_w %s,", NameOfCPURegister(regop));
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          data += PrintRightOperand(data);
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        } else if (*data == 0x89) {
          data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          AppendToBuffer("mov_w ");
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfCPURegister(regop));
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        } else if (*data == 0x8B) {
          data++;
          data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data);
        } else if (*data == 0x90) {
          AppendToBuffer("nop");  // 0x66 prefix
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        } else if (*data == 0xC7) {
          data++;
          AppendToBuffer("%s ", "mov_w");
          data += PrintRightOperand(data);
          int imm = *reinterpret_cast<int16_t*>(data);
          AppendToBuffer(",0x%x", imm);
          data += 2;
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        } else if (*data == 0xF7) {
          data++;
          AppendToBuffer("%s ", "test_w");
          data += PrintRightOperand(data);
          int imm = *reinterpret_cast<int16_t*>(data);
          AppendToBuffer(",0x%x", imm);
          data += 2;
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        } else if (*data == 0x0F) {
          data++;
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          if (*data == 0x38) {
            data++;
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            byte op = *data;
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            switch (op) {
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#define SSE34_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, opcode) \
  case 0x##opcode: {                                                      \
    AppendToBuffer(#instruction " %s,", NameOfXMMRegister(regop));        \
    data += PrintRightXMMOperand(data);                                   \
    break;                                                                \
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  }

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                SSSE3_INSTRUCTION_LIST(SSE34_DIS_CASE)
                SSE4_INSTRUCTION_LIST(SSE34_DIS_CASE)
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                SSE4_RM_INSTRUCTION_LIST(SSE34_DIS_CASE)
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#undef SSE34_DIS_CASE
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              default:
                UnimplementedInstruction();
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            }
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          } else if (*data == 0x3A) {
            data++;
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            if (*data == 0x0A) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              int8_t imm8 = static_cast<int8_t>(data[1]);
              AppendToBuffer("roundss %s,%s,%d", NameOfXMMRegister(regop),
                             NameOfXMMRegister(rm), static_cast<int>(imm8));
              data += 2;
            } else if (*data == 0x0B) {
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              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              int8_t imm8 = static_cast<int8_t>(data[1]);
              AppendToBuffer("roundsd %s,%s,%d",
                             NameOfXMMRegister(regop),
                             NameOfXMMRegister(rm),
                             static_cast<int>(imm8));
              data += 2;
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            } else if (*data == 0x0E) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pblendw %s,", NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
              AppendToBuffer(",%d", *reinterpret_cast<uint8_t*>(data));
              data++;
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            } else if (*data == 0x0F) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("palignr %s,", NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
              AppendToBuffer(",%d", *reinterpret_cast<uint8_t*>(data));
              data++;
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            } else if (*data == 0x14) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pextrb ");
              data += PrintRightOperand(data);
              AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
                             *reinterpret_cast<int8_t*>(data));
              data++;
            } else if (*data == 0x15) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pextrw ");
              data += PrintRightOperand(data);
              AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
                             *reinterpret_cast<int8_t*>(data));
              data++;
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            } else if (*data == 0x16) {
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              data++;
              int mod, regop, rm;
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              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pextrd ");
              data += PrintRightOperand(data);
              AppendToBuffer(",%s,%d", NameOfXMMRegister(regop),
                             *reinterpret_cast<int8_t*>(data));
              data++;
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            } else if (*data == 0x17) {
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              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              int8_t imm8 = static_cast<int8_t>(data[1]);
              AppendToBuffer("extractps %s,%s,%d",
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                             NameOfCPURegister(rm),
                             NameOfXMMRegister(regop),
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                             static_cast<int>(imm8));
              data += 2;
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            } else if (*data == 0x20) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("pinsrb %s,", NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
              AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
              data++;
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            } else if (*data == 0x21) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              AppendToBuffer("insertps %s,", NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
              AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
              data++;
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            } else if (*data == 0x22) {
              data++;
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
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              AppendToBuffer("pinsrd %s,", NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
              AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
              data++;
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            } else {
              UnimplementedInstruction();
            }
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          } else if (*data == 0x2E || *data == 0x2F) {
            const char* mnem = (*data == 0x2E) ? "ucomisd" : "comisd";
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            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            if (mod == 0x3) {
              AppendToBuffer("%s %s,%s", mnem,
                             NameOfXMMRegister(regop),
                             NameOfXMMRegister(rm));
              data++;
            } else {
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
            }
          } else if (*data == 0x50) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movmskpd %s,%s",
                           NameOfCPURegister(regop),
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                           NameOfXMMRegister(rm));
            data++;
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          } else if (*data == 0x54) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("andpd %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
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          } else if (*data == 0x56) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("orpd %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
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          } else if (*data == 0x57) {
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            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("xorpd %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
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          } else if (*data == 0x6E) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movd %s,", NameOfXMMRegister(regop));
            data += PrintRightOperand(data);
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          } else if (*data == 0x6F) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movdqa %s,", NameOfXMMRegister(regop));
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            data += PrintRightXMMOperand(data);
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          } else if (*data == 0x70) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            AppendToBuffer("pshufd %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
            AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
            data++;
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          } else if (*data == 0x90) {
            data++;
            AppendToBuffer("nop");  // 2 byte nop.
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          } else if (*data == 0xF3) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("psllq %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
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          } else if (*data == 0x71) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            int8_t imm8 = static_cast<int8_t>(data[1]);
            AppendToBuffer("ps%sw %s,%d", sf_str[regop / 2],
                           NameOfXMMRegister(rm), static_cast<int>(imm8));
            data += 2;
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          } else if (*data == 0x72) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            int8_t imm8 = static_cast<int8_t>(data[1]);
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            AppendToBuffer("ps%sd %s,%d", sf_str[regop / 2],
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                           NameOfXMMRegister(rm), static_cast<int>(imm8));
            data += 2;
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          } else if (*data == 0x73) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            int8_t imm8 = static_cast<int8_t>(data[1]);
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            DCHECK(regop == esi || regop == edx);
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            AppendToBuffer("ps%sq %s,%d", sf_str[regop / 2],
                           NameOfXMMRegister(rm), static_cast<int>(imm8));
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            data += 2;
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          } else if (*data == 0xD3) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("psrlq %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
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          } else if (*data == 0x7F) {
            AppendToBuffer("movdqa ");
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            data += PrintRightXMMOperand(data);
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            AppendToBuffer(",%s", NameOfXMMRegister(regop));
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          } else if (*data == 0x7E) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movd ");
            data += PrintRightOperand(data);
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
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          } else if (*data == 0xC4) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("pinsrw %s,", NameOfXMMRegister(regop));
            data += PrintRightOperand(data);
            AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
            data++;
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          } else if (*data == 0xE7) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
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            if (mod == 3) {
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              // movntdq
              UnimplementedInstruction();
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            } else {
              UnimplementedInstruction();
            }
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          } else if (*data == 0xB1) {
            data++;
            data += PrintOperands("cmpxchg_w", OPER_REG_OP_ORDER, data);
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          } else {
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            byte op = *data;
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            switch (op) {
#define SSE2_DIS_CASE(instruction, notUsed1, notUsed2, opcode)     \
  case 0x##opcode: {                                               \
    AppendToBuffer(#instruction " %s,", NameOfXMMRegister(regop)); \
    data += PrintRightXMMOperand(data);                            \
    break;                                                         \
  }

              SSE2_INSTRUCTION_LIST(SSE2_DIS_CASE)
#undef SSE2_DIS_CASE
              default:
                UnimplementedInstruction();
            }
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          }
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        } else {
          UnimplementedInstruction();
        }
        break;

      case 0xFE:
        { data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
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          if (regop == ecx) {
            AppendToBuffer("dec_b ");
            data += PrintRightOperand(data);
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          } else {
            UnimplementedInstruction();
          }
        }
        break;

      case 0x68:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data+1));
        data += 5;
        break;

      case 0x6A:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
        data += 2;
        break;

      case 0xA8:
        AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data+1));
        data += 2;
        break;

      case 0xA9:
        AppendToBuffer("test eax,0x%x", *reinterpret_cast<int32_t*>(data+1));
        data += 5;
        break;

      case 0xD1:  // fall through
      case 0xD3:  // fall through
      case 0xC1:
        data += D1D3C1Instruction(data);
        break;

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      case 0xD8:  // fall through
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      case 0xD9:  // fall through
2296
      case 0xDA:  // fall through
2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316
      case 0xDB:  // fall through
      case 0xDC:  // fall through
      case 0xDD:  // fall through
      case 0xDE:  // fall through
      case 0xDF:
        data += FPUInstruction(data);
        break;

      case 0xEB:
        data += JumpShort(data);
        break;

      case 0xF2:
        if (*(data+1) == 0x0F) {
          byte b2 = *(data+2);
          if (b2 == 0x11) {
            AppendToBuffer("movsd ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2317
            data += PrintRightXMMOperand(data);
2318 2319 2320 2321 2322 2323
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
          } else if (b2 == 0x10) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movsd %s,", NameOfXMMRegister(regop));
2324
            data += PrintRightXMMOperand(data);
2325 2326 2327 2328 2329 2330
          } else  if (b2 == 0x5A) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("cvtsd2ss %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
2331 2332 2333 2334 2335 2336 2337 2338
          } else if (b2 == 0x70) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("pshuflw %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
            AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
            data++;
2339 2340 2341
          } else {
            const char* mnem = "?";
            switch (b2) {
2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362
              case 0x2A:
                mnem = "cvtsi2sd";
                break;
              case 0x2C:
                mnem = "cvttsd2si";
                break;
              case 0x2D:
                mnem = "cvtsd2si";
                break;
              case 0x51:
                mnem = "sqrtsd";
                break;
              case 0x58:
                mnem = "addsd";
                break;
              case 0x59:
                mnem = "mulsd";
                break;
              case 0x5C:
                mnem = "subsd";
                break;
2363 2364 2365
              case 0x5D:
                mnem = "minsd";
                break;
2366 2367 2368
              case 0x5E:
                mnem = "divsd";
                break;
2369 2370 2371
              case 0x5F:
                mnem = "maxsd";
                break;
2372 2373 2374
              case 0x7C:
                mnem = "haddps";
                break;
2375 2376 2377 2378 2379
            }
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            if (b2 == 0x2A) {
2380 2381
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
2382
            } else if (b2 == 0x2C || b2 == 0x2D) {
2383 2384
              AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
              data += PrintRightXMMOperand(data);
2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
            } else if (b2 == 0xC2) {
              // Intel manual 2A, Table 3-18.
              const char* const pseudo_op[] = {
                "cmpeqsd",
                "cmpltsd",
                "cmplesd",
                "cmpunordsd",
                "cmpneqsd",
                "cmpnltsd",
                "cmpnlesd",
                "cmpordsd"
              };
              AppendToBuffer("%s %s,%s",
                             pseudo_op[data[1]],
                             NameOfXMMRegister(regop),
                             NameOfXMMRegister(rm));
              data += 2;
2402
            } else {
2403 2404
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
2405 2406 2407 2408 2409 2410 2411 2412
            }
          }
        } else {
          UnimplementedInstruction();
        }
        break;

      case 0xF3:
2413
        if (*(data+1) == 0x0F) {
2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428
          byte b2 = *(data+2);
          if (b2 == 0x11) {
            AppendToBuffer("movss ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightXMMOperand(data);
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
          } else if (b2 == 0x10) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movss %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
          } else if (b2 == 0x5A) {
2429 2430 2431
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2432 2433
            AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
2434
          } else if (b2 == 0x6F) {
2435 2436 2437 2438
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop));
2439
            data += PrintRightXMMOperand(data);
2440 2441 2442 2443 2444 2445 2446 2447
          } else if (b2 == 0x70) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("pshufhw %s,", NameOfXMMRegister(regop));
            data += PrintRightXMMOperand(data);
            AppendToBuffer(",%d", *reinterpret_cast<int8_t*>(data));
            data++;
2448
          } else if (b2 == 0x7F) {
2449 2450 2451 2452
            AppendToBuffer("movdqu ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
2453
            data += PrintRightXMMOperand(data);
2454
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472
          } else if (b2 == 0xB8) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("popcnt %s,", NameOfCPURegister(regop));
            data += PrintRightOperand(data);
          } else if (b2 == 0xBC) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("tzcnt %s,", NameOfCPURegister(regop));
            data += PrintRightOperand(data);
          } else if (b2 == 0xBD) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("lzcnt %s,", NameOfCPURegister(regop));
            data += PrintRightOperand(data);
2473
          } else {
2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493
            const char* mnem = "?";
            switch (b2) {
              case 0x2A:
                mnem = "cvtsi2ss";
                break;
              case 0x2C:
                mnem = "cvttss2si";
                break;
              case 0x2D:
                mnem = "cvtss2si";
                break;
              case 0x51:
                mnem = "sqrtss";
                break;
              case 0x58:
                mnem = "addss";
                break;
              case 0x59:
                mnem = "mulss";
                break;
2494 2495 2496
              case 0x5B:
                mnem = "cvttps2dq";
                break;
2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508
              case 0x5C:
                mnem = "subss";
                break;
              case 0x5D:
                mnem = "minss";
                break;
              case 0x5E:
                mnem = "divss";
                break;
              case 0x5F:
                mnem = "maxss";
                break;
2509 2510 2511
              case 0x7E:
                mnem = "movq";
                break;
2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533
            }
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            if (b2 == 0x2A) {
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
            } else if (b2 == 0x2C || b2 == 0x2D) {
              AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
              data += PrintRightXMMOperand(data);
            } else if (b2 == 0xC2) {
              // Intel manual 2A, Table 3-18.
              const char* const pseudo_op[] = {
                  "cmpeqss",  "cmpltss",  "cmpless",  "cmpunordss",
                  "cmpneqss", "cmpnltss", "cmpnless", "cmpordss"};
              AppendToBuffer("%s %s,%s", pseudo_op[data[1]],
                             NameOfXMMRegister(regop), NameOfXMMRegister(rm));
              data += 2;
            } else {
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightXMMOperand(data);
            }
2534 2535 2536 2537
          }
        } else if (*(data+1) == 0xA5) {
          data += 2;
          AppendToBuffer("rep_movs");
2538 2539 2540
        } else if (*(data+1) == 0xAB) {
          data += 2;
          AppendToBuffer("rep_stos");
2541 2542 2543
        } else if (*(data + 1) == 0x90) {
          data += 2;
          AppendToBuffer("pause");
2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562
        } else {
          UnimplementedInstruction();
        }
        break;

      case 0xF7:
        data += F7Instruction(data);
        break;

      default:
        UnimplementedInstruction();
    }
  }

  if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
    tmp_buffer_[tmp_buffer_pos_] = '\0';
  }

  int instr_len = data - instr;
2563 2564 2565
  if (instr_len == 0) {
    printf("%02x", *data);
  }
2566
  DCHECK_GT(instr_len, 0);  // Ensure progress.
2567 2568 2569 2570

  int outp = 0;
  // Instruction bytes.
  for (byte* bp = instr; bp < data; bp++) {
2571 2572 2573
    outp += v8::internal::SNPrintF(out_buffer + outp,
                                   "%02x",
                                   *bp);
2574 2575
  }
  for (int i = 6 - instr_len; i >= 0; i--) {
2576
    outp += v8::internal::SNPrintF(out_buffer + outp, "  ");
2577 2578
  }

2579 2580 2581
  outp += v8::internal::SNPrintF(out_buffer + outp,
                                 " %s",
                                 tmp_buffer_.start());
2582
  return instr_len;
2583
}  // NOLINT (function is too long)
2584 2585 2586 2587 2588


//------------------------------------------------------------------------------


2589
static const char* const cpu_regs[8] = {
2590 2591 2592 2593
  "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"
};


2594
static const char* const byte_cpu_regs[8] = {
2595
  "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
2596 2597 2598
};


2599
static const char* const xmm_regs[8] = {
2600
  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"
2601 2602 2603 2604
};


const char* NameConverter::NameOfAddress(byte* addr) const {
2605
  v8::internal::SNPrintF(tmp_buffer_, "%p", static_cast<void*>(addr));
2606
  return tmp_buffer_.start();
2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620
}


const char* NameConverter::NameOfConstant(byte* addr) const {
  return NameOfAddress(addr);
}


const char* NameConverter::NameOfCPURegister(int reg) const {
  if (0 <= reg && reg < 8) return cpu_regs[reg];
  return "noreg";
}


2621 2622 2623 2624 2625 2626
const char* NameConverter::NameOfByteCPURegister(int reg) const {
  if (0 <= reg && reg < 8) return byte_cpu_regs[reg];
  return "noreg";
}


2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640
const char* NameConverter::NameOfXMMRegister(int reg) const {
  if (0 <= reg && reg < 8) return xmm_regs[reg];
  return "noxmmreg";
}


const char* NameConverter::NameInCode(byte* addr) const {
  // IA32 does not embed debug strings at the moment.
  UNREACHABLE();
}


//------------------------------------------------------------------------------

2641
int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
2642
                                    byte* instruction) {
2643
  DisassemblerIA32 d(converter_, unimplemented_opcode_action());
2644 2645
  return d.InstructionDecode(buffer, instruction);
}
2646

2647 2648 2649
// The IA-32 assembler does not currently use constant pools.
int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; }

2650 2651 2652
// static
void Disassembler::Disassemble(FILE* f, byte* begin, byte* end,
                               UnimplementedOpcodeAction unimplemented_action) {
2653
  NameConverter converter;
2654
  Disassembler d(converter, unimplemented_action);
2655
  for (byte* pc = begin; pc < end;) {
2656
    v8::internal::EmbeddedVector<char, 128> buffer;
2657 2658
    buffer[0] = '\0';
    byte* prev_pc = pc;
2659
    pc += d.InstructionDecode(buffer, pc);
2660
    fprintf(f, "%p", static_cast<void*>(prev_pc));
2661 2662 2663 2664 2665 2666 2667 2668
    fprintf(f, "    ");

    for (byte* bp = prev_pc; bp < pc; bp++) {
      fprintf(f, "%02x",  *bp);
    }
    for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
      fprintf(f, "  ");
    }
2669
    fprintf(f, "  %s\n", buffer.start());
2670 2671 2672 2673 2674
  }
}


}  // namespace disasm
2675 2676

#endif  // V8_TARGET_ARCH_IA32