- 14 Sep, 2016 1 commit
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Ilija.Pavlovic authored
Implementation MADD.S. MSUB.fmt, MADDF.fmt, MSUBF.fmt and corresponding tests for assembler and disassembler. TEST=cctest/test-assembler-mips[64], cctest/test-disasm-mips[64] BUG= Review-Url: https://codereview.chromium.org/2313623002 Cr-Commit-Position: refs/heads/master@{#39415}
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- 18 Jul, 2016 1 commit
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bmeurer authored
So far TurboFan wasn't adding the deoptimization reasons for eager/soft deoptimization exits that can be used by either the DevTools profiler or the --trace-deopt flag. This adds basic support for deopt reasons on Deoptimize, DeoptimizeIf and DeoptimizeUnless nodes and threads through the reasons to the code generation. Also moves the DeoptReason to it's own file (to resolve include cycles) and drops unused reasons. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/2161543002 Cr-Commit-Position: refs/heads/master@{#37823}
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- 30 Jun, 2016 1 commit
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bbudge authored
-Defines SIMD128_REGISTERS for all platforms. -Adds Simd128 register information to RegisterConfiguration, and implements aliasing calculations. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2092103004 Cr-Commit-Position: refs/heads/master@{#37437}
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- 29 Jun, 2016 1 commit
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yangguo authored
R=mstarzinger@chromium.org BUG=v8:5117 Review-Url: https://codereview.chromium.org/2109613004 Cr-Commit-Position: refs/heads/master@{#37397}
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- 27 Jun, 2016 3 commits
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bbudge authored
Replaces ArchDefault method with Crankshaft and Turbofan getters. Eliminates IsAllocated method on Register, FloatRegister, DoubleRegister. Eliminates ToString method too. Changes call sites to access appropriate arch default RegisterConfiguration. LOG=N BUG= Review-Url: https://codereview.chromium.org/2092413002 Cr-Commit-Position: refs/heads/master@{#37297}
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ivica.bogosavljevic authored
BUG= Review-Url: https://codereview.chromium.org/2069933003 Cr-Commit-Position: refs/heads/master@{#37295}
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bbudge authored
- Add a const bool kSimpleFPAliasing variable for each platform so it's easier for the compiler to eliminate dead code. - Modify RegisterAllocator to use it. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2101473002 Cr-Commit-Position: refs/heads/master@{#37288}
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- 24 Jun, 2016 1 commit
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balazs.kilvady authored
Port fc59eb8a Original commit message: Moves between operands with different representations shouldn't happen, so don't test them. This makes it easier to modify canonicalization to differentiate between floating point types, which is needed to support floating point register aliasing for ARM and MIPS. This change also expands tests to include explicit FP moves (both register and stack slot). LOG=N BUG=v8:4124 BUG=chromium:622619 Review-Url: https://codereview.chromium.org/2090993002 Cr-Commit-Position: refs/heads/master@{#37241}
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- 13 May, 2016 1 commit
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mstarzinger authored
This makes the profiler reconstruct inlined function frames at eager deopt points from the deoptimization data. The main goal of this is to remove the last side-channel where Crankshaft communicates directly to the profiler. This is the last preparatory step towards deprecating the side-channel in question. R=yangguo@chromium.org Review-Url: https://codereview.chromium.org/1973993002 Cr-Commit-Position: refs/heads/master@{#36229}
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- 11 May, 2016 1 commit
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mstarzinger authored
This passes the inlining_id of deoptimization points via the relocation info instead of via a side-channel to the CPU profiler. This is one step towards deprecating the side-channel in question and avoid the need for performing a lookup of the return address of the deopt point. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/1956693002 Cr-Commit-Position: refs/heads/master@{#36177}
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- 09 May, 2016 1 commit
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bbudge authored
Changes some platform specific class names and uses typedefs to define FloatRegister, DoubleRegister, etc. This will be needed to do register allocation on ARM/MIPS where registers combine to form larger registers. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/1954953002 Cr-Commit-Position: refs/heads/master@{#36117}
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- 28 Apr, 2016 2 commits
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ivica.bogosavljevic authored
Implement unaligned access instructions, and tests for corresponding instruction BUG= Review-Url: https://codereview.chromium.org/1902743002 Cr-Commit-Position: refs/heads/master@{#35873}
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balazs.kilvady authored
TEST=mjsunit/asm/embenchen/zlib BUG= Review-Url: https://codereview.chromium.org/1925543003 Cr-Commit-Position: refs/heads/master@{#35854}
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- 19 Apr, 2016 1 commit
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akos.palfi authored
Port d412cfa2 BUG= Review URL: https://codereview.chromium.org/1899783003 Cr-Commit-Position: refs/heads/master@{#35613}
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- 30 Mar, 2016 1 commit
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Miran.Karic authored
Port of changes that replace JR and JALR instructions with JIC and JIALC for mips64r6. Macroassembler Jump and Call functions now use JIC and JIALC if branch delay slot is not used. Code patching is adjusted to work with new changes. Jr and Jalr macroassembler functions are removed. Other changes where mips32r6 uses jr/jalr are not done because mips64r6 uses j/jal instructions. BUG= Review URL: https://codereview.chromium.org/1830133002 Cr-Commit-Position: refs/heads/master@{#35141}
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- 10 Mar, 2016 1 commit
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balazs.kilvady authored
Make the low level assembler implementation exact and protected to disallow explicit usage. BUG= Review URL: https://codereview.chromium.org/1749263002 Cr-Commit-Position: refs/heads/master@{#34673}
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- 09 Mar, 2016 1 commit
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alan.li authored
Port 9d0cf920 Bug Descriptions: 1. We are missing drotr32 instruction 2. Ror Macro should also handle values less than zero or bigger than 31, as WASM instruction kExprI32Rol will generate shifting operands beyond [0 .. 31] range. 3. Same as Dror. 4. drotrv instruction in simulator is incorrect. BUG= TEST=cctest/test-run-wasm/Run_WasmInt32Binops,cctest/test-run-wasm/Run_WasmInt64Binops Review URL: https://codereview.chromium.org/1776623002 Cr-Commit-Position: refs/heads/master@{#34632}
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- 02 Mar, 2016 1 commit
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rmcilroy authored
Add support to log source position offsets to the profiler. As part of this change PositionsRecorder is split into two, with the subset needed by log.cc moved into log.h and the remainder kept in assembler.h as AssemblerPositionsRecorder. The interpreter's source position table builder is updated to log positions when the profiler is active. BUG=v8:4766 LOG=N Review URL: https://codereview.chromium.org/1737043002 Cr-Commit-Position: refs/heads/master@{#34416}
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- 17 Feb, 2016 1 commit
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bbudge authored
Adds kSimd128 to MachineRepresentation. Adds a Simd128Register concept that's platform independent. Adds UntaggedSimd128 to types.h. LOG=N BUG=v8:4124 Review URL: https://codereview.chromium.org/1693963004 Cr-Commit-Position: refs/heads/master@{#34089}
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- 18 Jan, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1593713002 Cr-Commit-Position: refs/heads/master@{#33361}
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- 15 Jan, 2016 1 commit
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mstarzinger authored
This splits out the SourcePosition class into a separate header file. Reason for this refactoring is that said class is mostly used by the Crankshaft compiler and not needed for all compilers. Also having the assembler depend on the class creates a dependency cycle. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1581083009 Cr-Commit-Position: refs/heads/master@{#33325}
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- 12 Jan, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1573953002 Cr-Commit-Position: refs/heads/master@{#33249}
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- 06 Jan, 2016 2 commits
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dusan.m.milosavljevic authored
Utilise Dextu, Dextm on mips64 for widths and positions larger than 32. TEST= BUG= Review URL: https://codereview.chromium.org/1552483002 Cr-Commit-Position: refs/heads/master@{#33138}
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ivica.bogosavljevic authored
Several ports to enable r6 compact branch optimizations on MIPS64 Port 3573d3cb Original commit message: MIPS: r6 compact branch optimization. Port bddf8c9e Original commit message: MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort() Port 6993cd0d Original commit message: MIPS: Fix 'MIPS:r6 compact branch optimization.' Jic and jialc compact branch ops are fixed as they does not have 'forbidden slot' restriction. Also COP1 branches (CTI instructions) added to IsForbiddenAfterBranchInstr(). Port bb332195 Original commit message: MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort() Port c91bcf71 Original commit message: MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort() for r6. BUG= Review URL: https://codereview.chromium.org/1534183002 Cr-Commit-Position: refs/heads/master@{#33136}
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- 05 Jan, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1545013002 Cr-Commit-Position: refs/heads/master@{#33127}
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- 02 Dec, 2015 1 commit
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yangguo authored
The new step-in implementation no longer tries to predict the step-in target, so we don't need the arguments count nor call type anymore. R=verwaest@chromium.org Review URL: https://codereview.chromium.org/1484893003 Cr-Commit-Position: refs/heads/master@{#32516}
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- 01 Dec, 2015 1 commit
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dusan.m.milosavljevic authored
TEST=unittests/InstructionSelectorTest.Word(32|64)AndToClearBits BUG= Review URL: https://codereview.chromium.org/1485023004 Cr-Commit-Position: refs/heads/master@{#32479}
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- 30 Nov, 2015 1 commit
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alan.li authored
BUG= Review URL: https://codereview.chromium.org/1481493002 Cr-Commit-Position: refs/heads/master@{#32417}
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- 27 Nov, 2015 1 commit
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jochen authored
Requires passing an explicit Isolate* to a bunch of static Assembler methods. BUG=v8:2487 R=yangguo@chromium.org,jkummerow@chromium.org LOG=n Review URL: https://codereview.chromium.org/1474323002 Cr-Commit-Position: refs/heads/master@{#32376}
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- 06 Nov, 2015 1 commit
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ahaas authored
R=titzer@chromium.org Review URL: https://codereview.chromium.org/1413463009 Cr-Commit-Position: refs/heads/master@{#31858}
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- 04 Nov, 2015 1 commit
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dusan.m.milosavljevic authored
TEST=cctest/test-run-machops/Float(64|32)MaxP, Float(64|32)MinP, unittests/InstructionSelectorTest.Float64Min|Max BUG=v8:4206 LOG=N Review URL: https://codereview.chromium.org/1419753008 Cr-Commit-Position: refs/heads/master@{#31806}
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- 07 Oct, 2015 1 commit
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mstarzinger authored
This removes the include of compiler.h from all our assemblers, which was only needed for the SourcePosition class. R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/1397493002 Cr-Commit-Position: refs/heads/master@{#31157}
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- 02 Oct, 2015 3 commits
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf Cr-Commit-Position: refs/heads/master@{#31075} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31087}
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danno authored
Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on MIPS Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} > > Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf > Cr-Commit-Position: refs/heads/master@{#31075} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1380863004 Cr-Commit-Position: refs/heads/master@{#31083}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31075}
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- 30 Sep, 2015 1 commit
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mstarzinger authored
This enables linter checking for "readability/namespace" violations during presubmit and instead marks the few known exceptions that we allow explicitly. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1371083003 Cr-Commit-Position: refs/heads/master@{#31019}
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- 29 Sep, 2015 1 commit
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dusan.m.milosavljevic authored
TEST= BUG= Review URL: https://codereview.chromium.org/1334793004 Cr-Commit-Position: refs/heads/master@{#31011}
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- 24 Sep, 2015 2 commits
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danno authored
Revert of Remove register index/code indirection (patchset #17 id:320001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on greedy RegAlloc, Fuzzer Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1365073002 Cr-Commit-Position: refs/heads/master@{#30914}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#30913}
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- 16 Sep, 2015 1 commit
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ivica.bogosavljevic authored
Fixing floating point register clobbering for MIPSr6 (32 and 64) due to using of f31 floating point register as double compare register, without saving the value of the register before using it. TEST=cctest/test-debug/* BUG= Review URL: https://codereview.chromium.org/1346623002 Cr-Commit-Position: refs/heads/master@{#30765}
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