Commit 4ec5a1e3 authored by alan.li's avatar alan.li Committed by Commit bot

MIPS: Fix '[wasm] add rotate opcodes'

Port 9d0cf920

Bug Descriptions:
1. We are missing drotr32 instruction
2. Ror Macro should also handle values less than zero or bigger than 31, as WASM instruction kExprI32Rol will generate shifting operands beyond [0 .. 31] range.
3. Same as Dror.
4. drotrv instruction in simulator is incorrect.

BUG=
TEST=cctest/test-run-wasm/Run_WasmInt32Binops,cctest/test-run-wasm/Run_WasmInt64Binops

Review URL: https://codereview.chromium.org/1776623002

Cr-Commit-Position: refs/heads/master@{#34632}
parent 8447072d
......@@ -1863,6 +1863,12 @@ void Assembler::drotr(Register rd, Register rt, uint16_t sa) {
emit(instr);
}
void Assembler::drotr32(Register rd, Register rt, uint16_t sa) {
DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
(rd.code() << kRdShift) | (sa << kSaShift) | DSRL32;
emit(instr);
}
void Assembler::drotrv(Register rd, Register rt, Register rs) {
DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
......
......@@ -783,6 +783,7 @@ class Assembler : public AssemblerBase {
void dsrl(Register rd, Register rt, uint16_t sa);
void dsrlv(Register rd, Register rt, Register rs);
void drotr(Register rd, Register rt, uint16_t sa);
void drotr32(Register rd, Register rt, uint16_t sa);
void drotrv(Register rd, Register rt, Register rs);
void dsra(Register rt, Register rd, uint16_t sa);
void dsrav(Register rd, Register rt, Register rs);
......
......@@ -1263,7 +1263,11 @@ void MacroAssembler::Ror(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
rotrv(rd, rs, rt.rm());
} else {
rotr(rd, rs, rt.imm64_);
int64_t ror_value = rt.imm64_ % 32;
if (ror_value < 0) {
ror_value += 32;
}
rotr(rd, rs, ror_value);
}
}
......@@ -1272,7 +1276,13 @@ void MacroAssembler::Dror(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
drotrv(rd, rs, rt.rm());
} else {
drotr(rd, rs, rt.imm64_);
int64_t dror_value = rt.imm64_ % 64;
if (dror_value < 0) dror_value += 64;
if (dror_value <= 31) {
drotr(rd, rs, dror_value);
} else {
drotr32(rd, rs, dror_value - 32);
}
}
}
......
......@@ -3478,9 +3478,7 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
// Logical right-rotate of a word by a variable number of bits.
// This is special case od SRLV instruction, added in MIPS32
// Release 2. SA field is equal to 00001.
alu_out =
base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()),
static_cast<const uint32_t>(rs_u()));
alu_out = base::bits::RotateRight64(rt_u(), rs_u());
}
SetResult(rd_reg(), alu_out);
break;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment