- 21 Jun, 2018 1 commit
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Ben L. Titzer authored
This completes the transition to Assembler::Options, which reduces the assemblers's dependency on isolates, and there is now only one way to create an Assembler, which is to use the options. Note that some operations on assemblers still need an isolate, such as GetCode(), and in these cases, the isolate is an additional argument to the method. R=jgruber@chromium.org CC=mstarzinger@chromium.org Change-Id: I413209d816c63a7c3640f1c226764693dcad1e7f Reviewed-on: https://chromium-review.googlesource.com/1106169 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#53925}
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- 23 Apr, 2018 1 commit
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Pierre Langlois authored
The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
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- 21 Feb, 2018 1 commit
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Martyn Capewell authored
Add support for CSDB in the 32-bit assembler, disassembler and simulator. Change-Id: I0e5432e4d219dd4699d5f9b7f911791acc87114c Reviewed-on: https://chromium-review.googlesource.com/928522Reviewed-by: Ross McIlroy <rmcilroy@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#51425}
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- 10 Jan, 2018 1 commit
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Pierre Langlois authored
Disallow using the PC as a base in LDR and instead provide a dedicated assembler method for pc-relative loads. The reason for this is that the generic `Assembler::ldr` method may decide to generate more instructions if the offset is out of range, and if the PC was the base, we would get surprising results. For example: ~~~ ldr r0, [pc, #0xcabba9e] ~~~ is not equivalent to: ~~~ movw ip, #0xba9e movt ip, #0xcab ldr r0, [pc, ip] ~~~ since the reference to the PC has moved down two instructions! We could teach the assembler to handle those cases correctly, but pc-relative loads are used in specific cases only so that's not necessary. As a drive-by, remove a reference to code aging. Bug: Change-Id: I586d83a418db52cf28d3b524f889bf40f077998a Reviewed-on: https://chromium-review.googlesource.com/847008Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#50475}
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- 02 Dec, 2017 1 commit
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Mathias Bynens authored
This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
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- 12 Oct, 2017 1 commit
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Pierre Langlois authored
When an immediate does not fit an add instruction we use a temporary register to hold the value, using movw/movt to encode it. However, in order to remove a use of r9 in TurboFan's code generator, we need to cope with no scratch registers being available. That is to say that the destination and source registers are the same, and `ip` is not available to use. In this case, we can split an add instruction into a sequence of additions: ``` UseScratchRegisterScope temps(...); Register my_scratch = temps.Acquire(); __ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd // add r0, r0, #0xab00 ``` As a drive-by fix, make the disassembler test fail if we expected a different number of instructions generated. Bug: v8:6553 Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf Reviewed-on: https://chromium-review.googlesource.com/685014Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#48491}
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- 01 Sep, 2017 1 commit
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Michael Starzinger authored
R=jkummerow@chromium.org Change-Id: I8937933e9ec5b4bd150f5a044700716db458f365 Reviewed-on: https://chromium-review.googlesource.com/645691Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47758}
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- 03 Aug, 2017 1 commit
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Ben L. Titzer authored
Since frames.h no longer defines basic register types like RegList, it is no longer necessary to include it in the macro assemblers. Next step: split out frame-constants.h from frames.h so that it will be possible to get frame constants without include the stackwalking logic, which needs objects.h. R=mstarzinger@chromium.org Bug: Change-Id: Ia12d3c8a8d46a73106c3c90bcb4b470c85f1eaa7 Reviewed-on: https://chromium-review.googlesource.com/597788 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47114}
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- 20 Jul, 2017 1 commit
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Andreas Haas authored
Apparently the name float.h causes problems on Windows when V8 is compiled with Visual Studio, see the bug description. R=clemensh@chromium.org Bug: v8:6588 Change-Id: Iaa9c1e93e62509a779f1a8ddecbb03a53981cf8a Reviewed-on: https://chromium-review.googlesource.com/578029Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Clemens Hammacher <clemensh@chromium.org> Commit-Queue: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#46791}
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- 13 Jul, 2017 1 commit
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Pierre Langlois authored
When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
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- 07 Jul, 2017 1 commit
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Andreas Haas authored
This CL changes for floats what https://chromium-review.googlesource.com/c/558964/ changed for doubles. Original message: On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. New in this CL: Although src/double.h existed already, src/float.h did not exist yet. I created the file in this CL, and moved the classes Float32 and Float64 there, which already existed in src/deoptimizer.h. R=titzer@chromium.org, martyn.capewell@arm.com, v8-arm-ports@googlegroups.com BUG=v8:6564 Change-Id: I6a3f1f154af9c8cd4bb8e7e856235d3eee5e9edd Reviewed-on: https://chromium-review.googlesource.com/561009 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Reviewed-by: Ben Titzer <titzer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46473}
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- 06 Jul, 2017 1 commit
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Pierre Langlois authored
Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
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- 05 Jul, 2017 1 commit
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Andreas Haas authored
On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. BUG=v8:6564 Change-Id: I062559f9a7ba8b0f560628e5c39621ca578c3e7d Reviewed-on: https://chromium-review.googlesource.com/558964 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#46418}
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- 16 May, 2017 1 commit
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bbudge authored
- Adds vdup.<size> Dd/Qd, Dm[i] instruction. - Adds vsli, vsri instructions. - Changes VMovExtended to use these to avoid moves to core registers. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2868603002 Cr-Commit-Position: refs/heads/master@{#45351}
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- 15 May, 2017 1 commit
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georgia.kouveli authored
BUG= Review-Url: https://codereview.chromium.org/2871863003 Cr-Commit-Position: refs/heads/master@{#45297}
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- 24 Apr, 2017 1 commit
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bbudge authored
- Adds new F32x4AddHoriz, I32x4AddHoriz, etc. to WASM opcodes. - Implements them for ARM. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2804883008 Cr-Commit-Position: refs/heads/master@{#44812}
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- 10 Apr, 2017 3 commits
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Original-Commit-Position: refs/heads/master@{#44536} Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44540}
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bbudge authored
Revert of [ARM] Implement D-register versions of vzip, vuzp, and vtrn. (patchset #4 id:60001 of https://codereview.chromium.org/2797923006/ ) Reason for revert: Breaks: http://builders/V8%20Arm%20-%20debug/builds/2751 Original issue's description: > [ARM] Implement D-register versions of vzip, vuzp, and vtrn. > > LOG=N > BUG=v8:6020 > > Review-Url: https://codereview.chromium.org/2797923006 > Cr-Commit-Position: refs/heads/master@{#44536} > Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 TBR=martyn.capewell@arm.com,bmeurer@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=v8:6020 Review-Url: https://codereview.chromium.org/2810703003 Cr-Commit-Position: refs/heads/master@{#44537}
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44536}
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- 27 Mar, 2017 1 commit
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bbudge authored
- Fixes vmovl for widening 16 to 32, 32 to 64. - Adds vqmovn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2773303002 Cr-Commit-Position: refs/heads/master@{#44156}
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- 14 Mar, 2017 1 commit
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bbudge authored
- Implements vuzp, vtrn instructions for q-registers. - Refactors vmvn, vswp to use common unary op helper fn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2739033002 Cr-Commit-Position: refs/heads/master@{#43795}
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- 02 Mar, 2017 1 commit
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bbudge authored
- Implements Select instructions using a single ARM vbsl instruction. - Renames boolean machine operators to match renamed S1xN machine types. - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM. - Implements S1xN AnyTrue, AllTrue ops for ARM. - Eliminates unused SIMD op categories in opcodes.h. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2711863002 Cr-Commit-Position: refs/heads/master@{#43556}
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- 28 Feb, 2017 1 commit
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Marja Hölttä authored
The x64 side is included in https://chromium-review.googlesource.com/c/444226/ BUG=v8:5294 Change-Id: Ie255604c5e38c72e3c2b76e1ca3557a5fde108ee Reviewed-on: https://chromium-review.googlesource.com/446394Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/master@{#43481}
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- 01 Feb, 2017 1 commit
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bbudge authored
- Adds vqadd.s/u, vqsub.s/u for all integer lane sizes. - Refactors disassembler and simulator, using switches instead of long if-else chains. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2649323012 Cr-Commit-Position: refs/heads/master@{#42865}
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- 23 Jan, 2017 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2629223005 Cr-Commit-Position: refs/heads/master@{#42610}
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- 16 Jan, 2017 1 commit
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bbudge authored
- Adds vmin, vmax for FP and integer vectors, both signed and unsigned. - Regularizes switching logic in disasm and simulator for special codes 4 and 6. - Factors vrecpe, vrsqrte, vrecps, vrsqrts into helper fns. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2623993006 Cr-Commit-Position: refs/heads/master@{#42385}
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- 12 Jan, 2017 2 commits
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2620343002 Cr-Commit-Position: refs/heads/master@{#42273}
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bbudge authored
- Floating point, signed, and unsigned. - Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2602293002 Cr-Commit-Position: refs/heads/master@{#42262}
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- 10 Jan, 2017 1 commit
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bbudge authored
- Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2600153002 Cr-Commit-Position: refs/heads/master@{#42176}
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- 20 Dec, 2016 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2593443002 Cr-Commit-Position: refs/heads/master@{#41859}
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- 17 Dec, 2016 1 commit
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bbudge authored
- Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
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- 15 Dec, 2016 1 commit
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bbudge authored
- Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
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- 25 Nov, 2016 1 commit
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bbudge authored
- Adds vmov, vswp instructions for QwNeonRegisters. - Refactors existing vswp implementation, moves non-Neon adaption to MacroAssembler. - Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2523933002 Cr-Commit-Position: refs/heads/master@{#41291}
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- 23 Sep, 2016 1 commit
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jacob.bramley authored
CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
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- 08 Sep, 2016 1 commit
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martyn.capewell authored
Reason for revert: Breaks g++ build. Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} BUG= Review-Url: https://codereview.chromium.org/2314043002 Cr-Commit-Position: refs/heads/master@{#39264}
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- 06 Sep, 2016 4 commits
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machenbach authored
Revert of [turbofan] ARM: Implement vswp and use in gap resolver (patchset #2 id:20001 of https://codereview.chromium.org/2313803003/ ) Reason for revert: Breaks arm compilation: https://build.chromium.org/p/client.v8.ports/builders/V8%20Arm%20-%20builder/builds/3549 Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} TBR=bmeurer@chromium.org,epertoso@chromium.org,martyn.capewell@arm.com # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review-Url: https://codereview.chromium.org/2314003003 Cr-Commit-Position: refs/heads/master@{#39210}
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martyn.capewell authored
Use vswp to switch double-precision registers in the gap resolver, with fall back temp register-based code if NEON is not available. BUG= Review-Url: https://codereview.chromium.org/2313803003 Cr-Commit-Position: refs/heads/master@{#39209}
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jacob.bramley authored
ARMv6 has the same basic barriers as ARMv7+, but they are accessed using the CP15 coprocessor. This patch allows the assembler to select the appropriate instruction. This also fixes TurboFan's atomic loads and stores for ARMv6 platforms. BUG= Review-Url: https://codereview.chromium.org/2318553002 Cr-Commit-Position: refs/heads/master@{#39203}
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jacob.bramley authored
These are ARMv8 instructions that will be used in a follow-up patch. BUG= Review-Url: https://codereview.chromium.org/2273003002 Cr-Commit-Position: refs/heads/master@{#39193}
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- 19 May, 2016 1 commit
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binji authored
R=jarin@chromium.org,bmeurer@chromium.org Review-Url: https://codereview.chromium.org/1993033002 Cr-Commit-Position: refs/heads/master@{#36380}
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