1. 21 Jun, 2018 1 commit
    • Ben L. Titzer's avatar
      [asm] Remove Assembler(isolate...) constructor · ea2f33c6
      Ben L. Titzer authored
      This completes the transition to Assembler::Options, which reduces
      the assemblers's dependency on isolates, and there is now only one
      way to create an Assembler, which is to use the options.
      Note that some operations on assemblers still need an isolate, such
      as GetCode(), and in these cases, the isolate is an additional
      argument to the method.
      
      R=jgruber@chromium.org
      CC=mstarzinger@chromium.org
      
      Change-Id: I413209d816c63a7c3640f1c226764693dcad1e7f
      Reviewed-on: https://chromium-review.googlesource.com/1106169
      Commit-Queue: Ben Titzer <titzer@chromium.org>
      Reviewed-by: 's avatarJakob Gruber <jgruber@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#53925}
      ea2f33c6
  2. 23 Apr, 2018 1 commit
  3. 21 Feb, 2018 1 commit
  4. 10 Jan, 2018 1 commit
    • Pierre Langlois's avatar
      [arm] Restrict usage of pc-relative LDR. · 5361c57b
      Pierre Langlois authored
      Disallow using the PC as a base in LDR and instead provide a dedicated assembler
      method for pc-relative loads. The reason for this is that the generic
      `Assembler::ldr` method may decide to generate more instructions if the offset
      is out of range, and if the PC was the base, we would get surprising
      results. For example:
      
      ~~~
      ldr r0, [pc, #0xcabba9e]
      ~~~
      
      is not equivalent to:
      
      ~~~
      movw ip, #0xba9e
      movt ip, #0xcab
      ldr r0, [pc, ip]
      ~~~
      
      since the reference to the PC has moved down two instructions!
      
      We could teach the assembler to handle those cases correctly, but pc-relative
      loads are used in specific cases only so that's not necessary.
      
      As a drive-by, remove a reference to code aging.
      
      Bug: 
      Change-Id: I586d83a418db52cf28d3b524f889bf40f077998a
      Reviewed-on: https://chromium-review.googlesource.com/847008Reviewed-by: 's avatarJaroslav Sevcik <jarin@chromium.org>
      Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
      Cr-Commit-Position: refs/heads/master@{#50475}
      5361c57b
  5. 02 Dec, 2017 1 commit
    • Mathias Bynens's avatar
      Normalize casing of hexadecimal digits · 822be9b2
      Mathias Bynens authored
      This patch normalizes the casing of hexadecimal digits in escape
      sequences of the form `\xNN` and integer literals of the form
      `0xNNNN`.
      
      Previously, the V8 code base used an inconsistent mixture of uppercase
      and lowercase.
      
      Google’s C++ style guide uses uppercase in its examples:
      https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters
      
      Moreover, uppercase letters more clearly stand out from the lowercase
      `x` (or `u`) characters at the start, as well as lowercase letters
      elsewhere in strings.
      
      BUG=v8:7109
      TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org
      NOPRESUBMIT=true
      
      Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng
      Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6
      Reviewed-on: https://chromium-review.googlesource.com/804294
      Commit-Queue: Mathias Bynens <mathias@chromium.org>
      Reviewed-by: 's avatarJakob Kummerow <jkummerow@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#49810}
      822be9b2
  6. 12 Oct, 2017 1 commit
    • Pierre Langlois's avatar
      [arm] Support splitting add with immediate instructions · d5b29f43
      Pierre Langlois authored
      When an immediate does not fit an add instruction we use a temporary register to
      hold the value, using movw/movt to encode it. However, in order to remove a use
      of r9 in TurboFan's code generator, we need to cope with no scratch registers
      being available. That is to say that the destination and source registers are
      the same, and `ip` is not available to use.
      
      In this case, we can split an add instruction into a sequence of additions:
      ```
      UseScratchRegisterScope temps(...);
      Register my_scratch = temps.Acquire();
      __ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd
                                      // add r0, r0, #0xab00
      ```
      
      As a drive-by fix, make the disassembler test fail if we expected a different
      number of instructions generated.
      
      Bug: v8:6553
      Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf
      Reviewed-on: https://chromium-review.googlesource.com/685014Reviewed-by: 's avatarBenedikt Meurer <bmeurer@chromium.org>
      Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
      Cr-Commit-Position: refs/heads/master@{#48491}
      d5b29f43
  7. 01 Sep, 2017 1 commit
  8. 03 Aug, 2017 1 commit
  9. 20 Jul, 2017 1 commit
  10. 13 Jul, 2017 1 commit
  11. 07 Jul, 2017 1 commit
    • Andreas Haas's avatar
      [arm] Pass float immediates to vmov as uint32_t · 08688b39
      Andreas Haas authored
      This CL changes for floats what https://chromium-review.googlesource.com/c/558964/
      changed for doubles.
      
      Original message:
      On x86, signalling NaNs get converted to quiet NaNs when they get push
      on the stack and popped again. This happens in the code generation for
      arm, specifically for the vmov instruction with the immediate parameter.
      This CL replaces the vmov function in assembler-arm to take the
      immediate as a uint64_t instead of a double, to guarantee that the bit
      pattern does not change even if the parameter is a signalling NaN.
      
      New in this CL:
      Although src/double.h existed already, src/float.h did not exist yet.
      I created the file in this CL, and moved the classes Float32 and
      Float64 there, which already existed in src/deoptimizer.h.
      
      R=titzer@chromium.org, martyn.capewell@arm.com, v8-arm-ports@googlegroups.com
      
      BUG=v8:6564
      
      Change-Id: I6a3f1f154af9c8cd4bb8e7e856235d3eee5e9edd
      Reviewed-on: https://chromium-review.googlesource.com/561009
      Commit-Queue: Andreas Haas <ahaas@chromium.org>
      Reviewed-by: 's avatarMartyn Capewell <martyn.capewell@arm.com>
      Reviewed-by: 's avatarBen Titzer <titzer@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#46473}
      08688b39
  12. 06 Jul, 2017 1 commit
    • Pierre Langlois's avatar
      [arm] Introduce UseScratchRegisterScope · 8e84b715
      Pierre Langlois authored
      Introduce a stripped down version of UseScratchRegisterScope for ARM and use it
      inside the assembler and macro-assembler. At the exception of the Call
      instructions, we now use this scope instead of using the ip register
      directly. This is inspired from how the ARM64 backend works.
      
      In general, the benefit of doing this is we can catch cases where ip is being
      used both by the caller and by the assembler. But more specifically, TurboFan
      reserves r9 as an extra scratch register because ip can already be used by the
      assembler. With this utility, we can isolate the cases in the code generator
      which need an extra register and potentially fix them, allowing us to give r9
      back to the register allocator.
      
      This patch uncovered places in the assembler where we were using ip
      unconditionally when we could have re-used the destination register instead.
      
      Bug: v8:6553
      Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78
      Reviewed-on: https://chromium-review.googlesource.com/544956
      Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
      Reviewed-by: 's avatarBenedikt Meurer <bmeurer@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#46425}
      8e84b715
  13. 05 Jul, 2017 1 commit
  14. 16 May, 2017 1 commit
  15. 15 May, 2017 1 commit
  16. 24 Apr, 2017 1 commit
  17. 10 Apr, 2017 3 commits
  18. 27 Mar, 2017 1 commit
  19. 14 Mar, 2017 1 commit
  20. 02 Mar, 2017 1 commit
    • bbudge's avatar
      Implement remaining Boolean SIMD operations on ARM. · 386e5a11
      bbudge authored
      - Implements Select instructions using a single ARM vbsl instruction.
      - Renames boolean machine operators to match renamed S1xN machine types.
      - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM.
      - Implements S1xN AnyTrue, AllTrue ops for ARM.
      - Eliminates unused SIMD op categories in opcodes.h.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2711863002
      Cr-Commit-Position: refs/heads/master@{#43556}
      386e5a11
  21. 28 Feb, 2017 1 commit
  22. 01 Feb, 2017 1 commit
  23. 23 Jan, 2017 1 commit
  24. 16 Jan, 2017 1 commit
  25. 12 Jan, 2017 2 commits
  26. 10 Jan, 2017 1 commit
  27. 20 Dec, 2016 1 commit
  28. 17 Dec, 2016 1 commit
  29. 15 Dec, 2016 1 commit
  30. 25 Nov, 2016 1 commit
  31. 23 Sep, 2016 1 commit
    • jacob.bramley's avatar
      [arm] Clean up use of IsSupported and IsEnabled. · 73518a90
      jacob.bramley authored
      CpuFeatures::IsSupported(feature) indicates that the feature is
      available on the target. AssemblerBase::IsEnabled(feature) indicates
      that we've checked for support (using CpuFeatureScope). The main benefit
      is that we can test on (for example) ARMv8, but have some assurance that
      we won't generate ARMv8 instructions on ARMv7 targets.
      
      This patch simply cleans up the usage, which had become inconsistent.
      The instruction emission functions now check not only that their
      dependent features are supported, but also that we've verified that
      using CpuFeatureScope.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2360243002
      Cr-Commit-Position: refs/heads/master@{#39676}
      73518a90
  32. 08 Sep, 2016 1 commit
  33. 06 Sep, 2016 4 commits
  34. 19 May, 2016 1 commit