BUG=v8:3007
LOG=N
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/88303003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18097 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

It is replaced by a mov_label_offset(Register, Label*) instruction.

BUG=none
TEST=test/cctest/test-assembler-arm.cc
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/23515007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16676 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Add support for a few NEON and ARM SIMD instructions and use them for various
memcpy operations.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/17858002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/14188016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14325 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: https://codereview.chromium.org/14208011

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14291 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This patch defines new makefile command line paramaters to better control the
ARM specific options. The new paramters are
 * armfpu      = vfp, vfpv3-d16, vfpv3, neon.
 * armfloatabi = softfp, hard
 * armneon     = on
 * armthumb    = on, off
 * armtest     = on
One existing paratemer has been modified:
 * armv7       = true, false
A number of parameters have been deprecated (but are still working):
 * hardfp      = on, off
 * vfp2        = off
 * vfp3        = off

the armtest paratmer when set to "on" will lock the options used during compile
time at runtime. This allows for example to easily test the ARMv6 build on an
ARMv7 platform without having to worry about features detected at runtime. When
not specified the compiler default will be used meaning it is not necessary
anymore to specify hardfp=on when natively building on an hardfp platform.

The shell help now prints the target options and features detected.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/14263018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14288 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=none
TEST=Default NaN tests added to test-assembler-arm.

Review URL: https://codereview.chromium.org/14109010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: https://chromiumcodereview.appspot.com/11428137
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This requires constant blinding before it can be enabled. There are other interesting optimizations that can be added later, detailed in a TODO.

BUG=optimization
R=ulan@chromium.org,mstarzinger@chromium.org, hwennborg@google.com

Review URL: https://chromiumcodereview.appspot.com/11191029
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13286 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The previously-used instruction isn't guaranteed to always be undefined,
and the encoding used was conditional (failing the condition on an
undefined instruction is itself undefined and not guaranteed to
fault!). I would have like to use a more clever encoding (see bug 2963),
but we need the extra bits to encode the size of the constant pool.

BUG=security
R=ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11242002
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12791 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11116011
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12737 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=mstarzinger@chromium.org,jfb@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11087047

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12735 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=
TEST=Compiling for ARMv5TEJ

Review URL: https://chromiumcodereview.appspot.com/10784013
Patch from Remi Duraffort <remi.duraffort@st.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12140 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/9231009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10407 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This shaves 416+ KB, just under 1% off the size of the debug d8 executable
on Linux (mostly because the CheckHelper functions for assertions were
getting separate copies for each compilation unit).  The difference in
release builds is negligible---a size reduction of 0.1%.

Also, change namespace-level 'static const' variables to remove the static
storage class as it's the default.

R=danno@chromium.org
BUG=
TEST=

Review URL: http://codereview.chromium.org/8680013

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10083 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The support for the old ABI is known to be broken and has been deprecated for some time now. Removed the instructions for loading and storing co-processor registers as they where only used to support the old ABI.

R=karlklose@chromium.org

BUG=v8:1316
TEST=

Review URL: http://codereview.chromium.org//6822025

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7565 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This patch
- removes the unimplemented code crash when rendering invalid/unknown instructions and prints "unknown" instead.
- prints the beginning of the constant pool marker.
- adds "da" as a shortcut for "disasm".
- print hexadecimal representation of double and single registers. This makes it easier to debug move/conversion code that uses temporary int32 values in floating point registers.
- annotates the stack with short prints of the values (HeapObjects and smis),
- makes disasm take an address or a register as second argument without a third argument, which defaults to printing ten instructions.

Review URL: http://codereview.chromium.org/6676042

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7279 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

TEST=none
BUG=none

Patch by Rodolph Perfetta from ARM Ltd.

Review URL: http://codereview.chromium.org/6594009


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7014 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Change the comparison in the full code generator to use CompareIC instead of the CompareStub to record the types. This also implements the patching in the full code generator where the inlined smi code is de-activated by default to call the CompareIC once and then activating the inlined smi code by patching the code.

Fixed the smi comparison in the ICCompareStub.

Fixed ToBooleanStub to ensure that the scratch register used is not the input. Use r9 as default as that will never be input with Crankshaft.

Implemented lithium instruction CmpTAndBranch.

Make sure that the lithium instruction CmpID have operands in registrers as the current optimized code expects that.
Review URL: http://codereview.chromium.org/6461017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6704 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

fix the simulator behaviour.

BUG=none
TEST=added to cctest/test-assembler-arm.cc

Patch by Rodolph Perfetta from ARM Ltd.

Review URL: http://codereview.chromium.org/6368053


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6629 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

First stab at a general ARM cleanup patch. It merges ARM constants so that they can be used across simulator, assembler and disassembler, and tidies up some syntax and ambiguities.

BUG=none
TEST=none

Review URL: http://codereview.chromium.org/6274009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6483 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=none
TEST=none

Review URL: http://codereview.chromium.org/6346009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6405 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

ARM: The Simulator will now handle different VFP rounding modes. RZ and RM are implemented.  This is a commit of 
http://codereview.chromium.org/4295003/show for Alexander Rames of ARM.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5790 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Fix the ARM simulator, the ARM disassembler and extend the stop feature. 
The stop feature in the simulator now support enabling, disabling and 
counting. 

BUG=None 
TEST=None 

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5723 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr.  This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Zhang Kun.  For now we only emit movw and movt in places where no
relocation is needed.  Small performance boost (around 0.5%).
Also adds support for turning ALU operations (eor etc.) with
large immediates into mvn or movw followed by a register-based
ALU operation.
Review URL: http://codereview.chromium.org/2821014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Support building with or without unaligned accesses by using scons flag simulatorunalignedaccesses.

$ scons simulator=arm simulatorunalignedaccesses=off
$ scons simulator=arm simulatorunalignedaccesses=on

If simulatorunalignedaccesses is not specified (or specified as default) the default is to use unaligned accesses.
Review URL: http://codereview.chromium.org/2218003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4737 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The build process must add -DCAN_USE_UNALIGNED_ACCESSES=1 to the
C++ flags to activate the support.  This is a commit for
Subrato of CodeAurora.  See http://codereview.chromium.org/1731013
Small edits by Erik Corry to activate unaligned accesses by
default on the simulator and testing Android builds.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4604 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel.

Moved the handling of the miscellaneous instructions to a separate part.

Review URL: http://codereview.chromium.org/1576026


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/993002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

available. Using blx will allow the CPU to predict the return address
fo the function, resulting in better overall performamce.
This is a copy of http://codereview.chromium.org/1113002 by
rodolph.perfetta@googlemail.com

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4198 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/545155

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3687 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

used by gcc to indicate ARM architectures.
Review URL: http://codereview.chromium.org/440017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3359 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

indicates ARMv6.
Review URL: http://codereview.chromium.org/437056

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3356 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Also move a function into the macro assembler.
Fix some *& placement errors that had accumulated.
Review URL: http://codereview.chromium.org/385069

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3293 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/348019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3292 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Ensure that we use ARMv5 instructions on ARMv6 and ARMv7 CPUs.
Review URL: http://codereview.chromium.org/206012

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2898 ce2b1a6d-e550-0410-aec6-3dcde31c8c00