Fix the ARM simulator, the ARM disassembler and extend the stop feature. 
The stop feature in the simulator now support enabling, disabling and 
counting. 

BUG=None 
TEST=None 

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5723 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

I noticed we sometimes had extra spaces before and after the "const"
keyword.  Probably the result of a search and replace gone wrong.

This is a whitespace only change.

Review URL: http://codereview.chromium.org/3427021

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5519 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr.  This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Add support for vstr for single precision VFP register.  This is a commit of http://codereview.chromium.org/3064045 for Rodolph Perfetta

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5281 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Upgraded the CodeGenerator::ToBoolean() function in the ARM backend to use complete JIT code generation and not make runtime calls to ToBool (when VFP is enabled). 

This change also includes the vcmp VFP instruction that supports a constant 0.0 as the second operand. 

Patch by Subrato K De <subratokde@codeaurora.org>



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5267 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/2878043

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5116 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each.
Review URL: http://codereview.chromium.org/2885002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

A potential issue with this change is creating lots of maps when
objects flip between fast/slow elements modes.  We could add special
transitions to avoid this.  Yet testing this on our benchmarks, gmail,
and wave seems to indicate that this is not a real problem.

Review URL: http://codereview.chromium.org/2870018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4941 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Align deferred code blocks to 16-byte address boundaries.

Review URL: http://codereview.chromium.org/2855018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4914 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Zhang Kun.  For now we only emit movw and movt in places where no
relocation is needed.  Small performance boost (around 0.5%).
Also adds support for turning ALU operations (eor etc.) with
large immediates into mvn or movw followed by a register-based
ALU operation.
Review URL: http://codereview.chromium.org/2821014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

assembler*.h files to make clang happy. There was no reason for having
the definition in the -inl.h files in the first place.

Review URL: http://codereview.chromium.org/2825008

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4888 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

don't fit in the instruction.  Use ubfx and sbfx more.
Review URL: http://codereview.chromium.org/2826001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Added support for more precise break points when debugging and stepping. To achieve that additional nop instructions are inserted where breaking would otherwise be impossible. The number of nop instructions inserted are sufficient to make place for patching with a call to a debug break code stub. On Intel that is 5 nop's for 32-bit and 13 for 64-bit. Om ARM 3 nop instructions (12 bytes) are required.

In order to avoid inserting nop's in to many places a simple ast checker have been added to check whether there are breakable code in a statement or expression. If it is possible to break in an expression no additional break enabeling code is inserted.

Added break locations to the true and false part of a conditional expression.

Added stepping tests to cover more constructs.

These changes are only in the full compiler.

Changed the default value for the option --debugger in teh d8 shell from true to false. The reason for this is that with --debugger turned on the full compiler will be used for all code in when running d8, which can be unexpeceted.

Review URL: http://codereview.chromium.org/2693002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4820 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The generic keyed load stub was missing converting string keys to numberign keys and lookup in the keyed lookup cache. This is now added together with an additional counter on all platforms.
Review URL: http://codereview.chromium.org/2441002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4773 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This is a commit of http://codereview.chromium.org/2124022
for Rodolph Perfetta.  I changed the test in
test-assembler-arm.cc so it only runs if ARMv7 is supported.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/2122021

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4724 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

of http://codereview.chromium.org/2064012/show for Rodolph Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4694 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

When ldrd is not available two ldr instructions are generated. This fixes these in the case where the register used in the memory operand is the same as the first register in the register pair receiving the values.

All tests now run on ARM with the flag --special-command="@ --noenable-vfp3". Running without VFP3 support in the simulator causes more ldrd instructions to be used, and the default build configuration does not utilize ldrd, but generated tow ldr instructions.
Review URL: http://codereview.chromium.org/2078013

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

under one flag.  Also other cosmetic changes to peephole
optimization.
Review URL: http://codereview.chromium.org/2104006

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4663 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

http://codereview.chromium.org/2004006 for Subrato De.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4662 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

commit for zhangk@codeaurora.org.  See
http://codereview.chromium.org/568029 and
http://codereview.chromium.org/2019003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4618 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The generation of the deferred code for named property load where the load was inlined did a constant pool blocking for the whole deferred code. Having large numbers of this type of deferred code generated one ofter the other effectively blocked the constant pool for all the deferred code causing 

Removed the BeforeGenerate/AfterGenerate for the deferred code and made macro assembler StartBlockConstPool/EndBlockConstPool non-public. Re-introduced BlockConstPoolFor instead to use with BlockConstPoolScope to block some more instructions cross function calls.

Also handle the use of native code counters for inlined named property load.
Review URL: http://codereview.chromium.org/1787005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4507 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Instaed of having a nop after all non-inlined calls to load IC use a different nop (mov r1, r1 instead of mov r0, r0) to detect an inlined load IC.

Added more infrastructure to the deferred code handling to make it possbile to block constant pool emitting in a deferred code block, including the branch instruction ending the deferred code block.

Addressed a couple of comments to http://codereview.chromium.org/1715003, including adding an assert to make sure that the patching of an ldr instruction is always possible.
Review URL: http://codereview.chromium.org/1758003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4480 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Generate inlined named property load for in-object properties. This uses the same mechanism as on the Intel platforms with the map check and load instruction of the inlined code being	patched by the inline cache code. The map check is patched through the normal constant pool patching and the load instruction is patched in place.
Review URL: http://codereview.chromium.org/1715003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4468 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

TBR=erik.corry@gmail.com
Review URL: http://codereview.chromium.org/1749002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4458 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Instead of indicating for how many instructions the constant pool needs to be blocked the constant pool is now blocked while at least one instance of ScopedConstPoolBlocker exists.
Review URL: http://codereview.chromium.org/1673006

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4456 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Whether this was a typo or a deliberate decision at some point I don't know. Anyway it was wrong.

TBR=erik.corry@gmail.com
Review URL: http://codereview.chromium.org/1752001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4452 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/993002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

available. Using blx will allow the CPU to predict the return address
fo the function, resulting in better overall performamce.
This is a copy of http://codereview.chromium.org/1113002 by
rodolph.perfetta@googlemail.com

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4198 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/660256

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3983 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Patch from Kun Zhang <zhangk@codeaurora.org>, see http://codereview.chromium.org/569015.
Review URL: http://codereview.chromium.org/573027

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3804 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/574009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3801 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/552186

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3793 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/563008

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3767 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/545155

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3687 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/464016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3435 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The constant for the return sequence length (JSReturnSequenceLength) was
defined in debug.h. Since this constant are also needed outside the debugger code
I moved them into assembler-xxx.h. Otherwise compiling with debuggersupport=off
would fail on ARM.

BUG=http://code.google.com/p/v8/issues/detail?id=533

Review URL: http://codereview.chromium.org/456001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3383 ce2b1a6d-e550-0410-aec6-3dcde31c8c00