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Commit 3752fdbb authored by erik.corry@gmail.com's avatar erik.corry@gmail.com
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ARM cleanup: Remove lea, swap, swapb instrutions. This is a commit 

of http://codereview.chromium.org/2064012/show for Rodolph Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4694 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent f6a2ccf6
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Showing with 1 addition and 114 deletions
src/arm/assembler-arm.cc
View file @ 3752fdbb
......@@ -1429,26 +1429,6 @@ void Assembler::stm(BlockAddrMode am,
}
// Semaphore instructions.
void Assembler::swp(Register dst, Register src, Register base, Condition cond) {
ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc));
ASSERT(!dst.is(base) && !src.is(base));
emit(cond | P | base.code()*B16 | dst.code()*B12 |
B7 | B4 | src.code());
}
void Assembler::swpb(Register dst,
Register src,
Register base,
Condition cond) {
ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc));
ASSERT(!dst.is(base) && !src.is(base));
emit(cond | P | B | base.code()*B16 | dst.code()*B12 |
B7 | B4 | src.code());
}
// Exception-generating instructions and debugging support.
void Assembler::stop(const char* msg) {
#ifndef __arm__
......@@ -1992,34 +1972,6 @@ void Assembler::nop(int type) {
}
void Assembler::lea(Register dst,
const MemOperand& x,
SBit s,
Condition cond) {
int am = x.am_;
if (!x.rm_.is_valid()) {
// Immediate offset.
if ((am & P) == 0) // post indexing
mov(dst, Operand(x.rn_), s, cond);
else if ((am & U) == 0) // negative indexing
sub(dst, x.rn_, Operand(x.offset_), s, cond);
else
add(dst, x.rn_, Operand(x.offset_), s, cond);
} else {
// Register offset (shift_imm_ and shift_op_ are 0) or scaled
// register offset the constructors make sure than both shift_imm_
// and shift_op_ are initialized.
ASSERT(!x.rm_.is(pc));
if ((am & P) == 0) // post indexing
mov(dst, Operand(x.rn_), s, cond);
else if ((am & U) == 0) // negative indexing
sub(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
else
add(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
}
}
bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
uint32_t dummy1;
uint32_t dummy2;
......
src/arm/assembler-arm.h
View file @ 3752fdbb
......@@ -780,10 +780,6 @@ class Assembler : public Malloced {
void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al);
void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
// Semaphore instructions
void swp(Register dst, Register src, Register base, Condition cond = al);
void swpb(Register dst, Register src, Register base, Condition cond = al);
// Exception-generating instructions and debugging support
void stop(const char* msg);
......@@ -930,10 +926,6 @@ class Assembler : public Malloced {
add(sp, sp, Operand(kPointerSize));
}
// Load effective address of memory operand x into register dst
void lea(Register dst, const MemOperand& x,
SBit s = LeaveCC, Condition cond = al);
// Jump unconditionally to given label.
void jmp(Label* L) { b(L, al); }
......
src/arm/assembler-thumb2.cc
View file @ 3752fdbb
......@@ -1205,26 +1205,6 @@ void Assembler::stm(BlockAddrMode am,
}
// Semaphore instructions.
void Assembler::swp(Register dst, Register src, Register base, Condition cond) {
ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc));
ASSERT(!dst.is(base) && !src.is(base));
emit(cond | P | base.code()*B16 | dst.code()*B12 |
B7 | B4 | src.code());
}
void Assembler::swpb(Register dst,
Register src,
Register base,
Condition cond) {
ASSERT(!dst.is(pc) && !src.is(pc) && !base.is(pc));
ASSERT(!dst.is(base) && !src.is(base));
emit(cond | P | B | base.code()*B16 | dst.code()*B12 |
B7 | B4 | src.code());
}
// Exception-generating instructions and debugging support.
void Assembler::stop(const char* msg) {
#if !defined(__arm__)
......@@ -1599,35 +1579,6 @@ void Assembler::vmrs(Register dst, Condition cond) {
}
// Pseudo instructions.
void Assembler::lea(Register dst,
const MemOperand& x,
SBit s,
Condition cond) {
int am = x.am_;
if (!x.rm_.is_valid()) {
// Immediate offset.
if ((am & P) == 0) // post indexing
mov(dst, Operand(x.rn_), s, cond);
else if ((am & U) == 0) // negative indexing
sub(dst, x.rn_, Operand(x.offset_), s, cond);
else
add(dst, x.rn_, Operand(x.offset_), s, cond);
} else {
// Register offset (shift_imm_ and shift_op_ are 0) or scaled
// register offset the constructors make sure than both shift_imm_
// and shift_op_ are initialized.
ASSERT(!x.rm_.is(pc));
if ((am & P) == 0) // post indexing
mov(dst, Operand(x.rn_), s, cond);
else if ((am & U) == 0) // negative indexing
sub(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
else
add(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
}
}
bool Assembler::ImmediateFitsAddrMode1Instruction(int32_t imm32) {
uint32_t dummy1;
uint32_t dummy2;
......
src/arm/assembler-thumb2.h
View file @ 3752fdbb
......@@ -735,10 +735,6 @@ class Assembler : public Malloced {
void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al);
void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al);
// Semaphore instructions
void swp(Register dst, Register src, Register base, Condition cond = al);
void swpb(Register dst, Register src, Register base, Condition cond = al);
// Exception-generating instructions and debugging support
void stop(const char* msg);
......@@ -864,10 +860,6 @@ class Assembler : public Malloced {
add(sp, sp, Operand(kPointerSize));
}
// Load effective address of memory operand x into register dst
void lea(Register dst, const MemOperand& x,
SBit s = LeaveCC, Condition cond = al);
// Jump unconditionally to given label.
void jmp(Label* L) { b(L, al); }
......
src/arm/builtins-arm.cc
View file @ 3752fdbb
......@@ -132,7 +132,7 @@ static void AllocateEmptyJSArray(MacroAssembler* masm,
// of the JSArray.
// result: JSObject
// scratch2: start of next object
__ lea(scratch1, MemOperand(result, JSArray::kSize));
__ add(scratch1, result, Operand(JSArray::kSize));
__ str(scratch1, FieldMemOperand(result, JSArray::kElementsOffset));
// Clear the heap tag on the elements array.
......
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