- 01 Jul, 2021 1 commit
-
-
Peter Kasting authored
There are still a few cases remaining that seem more controversial; I'll upload those separately. Bug: chromium:1066980 Change-Id: Iabbaf23f9bbe97781857c0c589f2b3db685dfdc2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2994804 Commit-Queue: Peter Kasting <pkasting@chromium.org> Auto-Submit: Peter Kasting <pkasting@chromium.org> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Cr-Commit-Position: refs/heads/master@{#75494}
-
- 21 May, 2019 1 commit
-
-
Yang Guo authored
Bug: v8:9247 TBR=bmeurer@chromium.org,neis@chromium.org NOPRESUBMIT=true Change-Id: Ia1e49d1aac09c4ff9e05d58fab9d08dd71198878 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1621931Reviewed-by:
Yang Guo <yangguo@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Commit-Queue: Yang Guo <yangguo@chromium.org> Cr-Commit-Position: refs/heads/master@{#61682}
-
- 29 Mar, 2019 1 commit
-
-
Clemens Hammacher authored
Even though both are allowed in the style guide, it recommends to use 'using', as its syntax is more consistent with the rest of C++. This CL turns all typedefs in compiler code to 'using' declarations. R=mstarzinger@chromium.org Bug: v8:8834 Change-Id: I3baf3ecbfe2c853cb17bb479ebbf140382193b5c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1545896 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#60527}
-
- 21 Nov, 2018 1 commit
-
-
Clemens Hammacher authored
Register names are static, so we do not need to access them via RegisterConfiguration. This saves a lot of RegisterConfiguration object creations. R=mstarzinger@chromium.org Bug: v8:8238 Change-Id: I295ad4d4b13fe948c70490687b7e3e9b48e70af9 Reviewed-on: https://chromium-review.googlesource.com/c/1342517Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#57668}
-
- 12 Nov, 2018 1 commit
-
-
Ben L. Titzer authored
This CL splits the backend of TurboFan off into its own directory, without changing namespaces. This makes ownership management a bit more fine-grained with a logical separation. R=mstarzinger@chromium.org,jarin@chromium.org,adamk@chromium.org Change-Id: I2ac40d6ca2c4f04b8474b630aae0286ecf79ef42 Reviewed-on: https://chromium-review.googlesource.com/c/1308333 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by:
Adam Klein <adamk@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#57437}
-
- 30 Aug, 2018 1 commit
-
-
Bill Budge authored
- Cleans up existing code that tests for representations using a bitmask. - Bypass FP register allocation for sequences without FP vregs. Change-Id: I5ff32e80e0c33848ba83ee17f786b01e37821aa2 Reviewed-on: https://chromium-review.googlesource.com/1195528 Commit-Queue: Bill Budge <bbudge@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#55535}
-
- 25 Sep, 2017 1 commit
-
-
Clemens Hammacher authored
Use the (D)CHECK_{EQ,NE,GT,...} macros instead of (D)CHECK with an embedded comparison. This gives better error messages and also does the right comparison for signed/unsigned mismatches. This will allow us to reenable the readability/check cpplint check. R=jarin@chromium.org Bug: v8:6837 Change-Id: I712580c2a4326e06ee3d6d0eb4ff8c7d24f5fdb9 Reviewed-on: https://chromium-review.googlesource.com/671227 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#48135}
-
- 03 Aug, 2017 1 commit
-
-
Michael Starzinger authored
This removes the obsolete {Crankshaft} factory method as it returns the same configuration as the {Turbofan} factory by now. We now consistently use {RegisterConfiguration::Default} everywhere. R=jkummerow@chromium.org BUG=v8:6408 Change-Id: I6be25774aa6714ef4dc1ef6856bb6dbc95593a29 Reviewed-on: https://chromium-review.googlesource.com/597858Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47109}
-
- 13 Jul, 2017 1 commit
-
-
Clemens Hammacher authored
There is just one version now, called IsPowerOfTwo. It accepts any integral type. There is one slight semantical change: Called with kMinInt, it previously returned true, because the argument was implicitly casted to an unsigned. It's now (correctly) returning false, so I had to add special handlings of kMinInt in machine-operator-reducer before calling IsPowerOfTwo on that value. R=mlippautz@chromium.org,mstarzinger@chromium.org,jgruber@chromium.org,ishell@chromium.org,yangguo@chromium.org Change-Id: Idc112a89034cdc8c03365b778b33b1c29fefb38d Reviewed-on: https://chromium-review.googlesource.com/568140Reviewed-by:
Igor Sheludko <ishell@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Reviewed-by:
Yang Guo <yangguo@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#46627}
-
- 08 Nov, 2016 1 commit
-
-
jarin authored
The set of operands are really small, so STL set performs really poorly. In Octane/TypeScript, I see move optimization going from >300ms to <100ms. Review-Url: https://codereview.chromium.org/2481853002 Cr-Commit-Position: refs/heads/master@{#40835}
-
- 26 Oct, 2016 1 commit
-
-
bbudge authored
- Modifies RegisterConfiguration to specify complex aliasing on ARM 32. - Modifies RegisterAllocator to consider aliasing. - Modifies ParallelMove::PrepareInsertAfter to handle aliasing. - Modifies GapResolver to split wider register moves when interference with smaller moves is detected. - Modifies MoveOptimizer to handle aliasing. - Adds ARM 32 macro-assembler pseudo move instructions to handle cases where split moves don't correspond to actual s-registers. - Modifies CodeGenerator::AssembleMove and AssembleSwap to handle moves of different widths, and moves involving pseudo-s-registers. - Adds unit tests for FP operand interference checking and PrepareInsertAfter. - Adds more tests of FP for the move optimizer and register allocator. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2410673002 Cr-Commit-Position: refs/heads/master@{#40597}
-
- 10 Oct, 2016 1 commit
-
-
heimbuef authored
BUG=v8:5409 Committed: https://crrev.com/a124feb0760896c8be61de08004a08c3bc9b4b3f Committed: https://crrev.com/fc840361e357a571c709e0239ae82cc089800b3f Review-Url: https://codereview.chromium.org/2348303002 Cr-Original-Original-Commit-Position: refs/heads/master@{#39633} Cr-Original-Commit-Position: refs/heads/master@{#40048} Cr-Commit-Position: refs/heads/master@{#40138}
-
- 07 Oct, 2016 1 commit
-
-
hablich authored
Revert of Replaced different means of zone pooling/reusing by one zone segment pool (patchset #5 id:160001 of https://codereview.chromium.org/2348303002/ ) Reason for revert: related to roll blocker: https://codereview.chromium.org/2400343002/ Original issue's description: > Replaced different means of zone pooling/reusing by one zone segment pool > > BUG=v8:5409 > > Committed: https://crrev.com/a124feb0760896c8be61de08004a08c3bc9b4b3f > Committed: https://crrev.com/fc840361e357a571c709e0239ae82cc089800b3f > Cr-Original-Commit-Position: refs/heads/master@{#39633} > Cr-Commit-Position: refs/heads/master@{#40048} TBR=mstarzinger@chromium.org,verwaest@chromium.org,heimbuef@google.com NOTRY=true NOPRESUBMIT=true NOTREECHECKS=true BUG=v8:5409 Review-Url: https://codereview.chromium.org/2401163002 Cr-Commit-Position: refs/heads/master@{#40099}
-
- 06 Oct, 2016 1 commit
-
-
heimbuef authored
BUG=v8:5409 Committed: https://crrev.com/a124feb0760896c8be61de08004a08c3bc9b4b3f Review-Url: https://codereview.chromium.org/2348303002 Cr-Original-Commit-Position: refs/heads/master@{#39633} Cr-Commit-Position: refs/heads/master@{#40048}
-
- 23 Sep, 2016 1 commit
-
-
hablich authored
Revert of Replaced different means of zone pooling/reusing by one zone segment pool (patchset #3 id:120001 of https://codereview.chromium.org/2348303002/ ) Reason for revert: Blocks Roll https://codereview.chromium.org/2366733002/ Original issue's description: > Replaced different means of zone pooling/reusing by one zone segment pool > > BUG=v8:5409 > > Committed: https://crrev.com/a124feb0760896c8be61de08004a08c3bc9b4b3f > Cr-Commit-Position: refs/heads/master@{#39633} TBR=mstarzinger@chromium.org,verwaest@chromium.org,heimbuef@google.com # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=v8:5409 Review-Url: https://codereview.chromium.org/2360403003 Cr-Commit-Position: refs/heads/master@{#39651}
-
- 22 Sep, 2016 1 commit
-
-
heimbuef authored
BUG=v8:5409 Review-Url: https://codereview.chromium.org/2348303002 Cr-Commit-Position: refs/heads/master@{#39633}
-
- 13 Sep, 2016 1 commit
-
-
bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2328423002 Cr-Commit-Position: refs/heads/master@{#39389}
-
- 09 Aug, 2016 1 commit
-
-
bbudge authored
LOG=N BUG=V8:4124 Review-Url: https://codereview.chromium.org/2214843003 Cr-Commit-Position: refs/heads/master@{#38462}
-
- 29 Jul, 2016 1 commit
-
-
bbudge authored
- Changes register allocation to only use even numbered registers on Arm. - Turns on float32 testing in test-gap-resolver.cc. This is effectively a revert of: https://codereview.chromium.org/2086653003/ LOG=N BUG=V8:4124, V8:5202 Review-Url: https://codereview.chromium.org/2176173003 Cr-Commit-Position: refs/heads/master@{#38151}
-
- 01 Jul, 2016 1 commit
-
-
danno authored
This optimizes the passing of stack parameters in function calls. For some architectures (ia32/x64), using pushes when possible instead of bumping the stack and then storing parameters generates much smaller code, and in some cases is faster (e.g. when a push of a memory location can implement a memory-to-memory copy and thus elide an intermediate load. On others (e.g. ARM), the benefit is smaller, where it's only possible to elide direct stack pointer adjustment in certain cases or combine multiple register stores into a single instruction in other limited situations. On yet other platforms (ARM64, MIPS), there are no push instructions, and this optimization isn't used at all. Ideally, this mechanism would be used for both tail calls and normal calls, but "normal" calls are currently pretty efficient, and tail calls are very inefficient, so this CL sets the bar low for building a new mechanism to handle parameter pushing that only needs to raise the bar on tail calls for now. The key aspect of this change is that adjustment to the stack pointer for tail calls (and perhaps later real calls) is an explicit step separate from instruction selection and gap resolution, but aware of both, making it possible to safely recognize gap moves that are actually pushes. Review-Url: https://codereview.chromium.org/2082263002 Cr-Commit-Position: refs/heads/master@{#37477}
-
- 30 Jun, 2016 1 commit
-
-
bbudge authored
-Defines SIMD128_REGISTERS for all platforms. -Adds Simd128 register information to RegisterConfiguration, and implements aliasing calculations. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2092103004 Cr-Commit-Position: refs/heads/master@{#37437}
-
- 29 Jun, 2016 1 commit
-
-
bbudge authored
- Changes InstructionOperand canonicalization to map all FP operands to kFloat64 on Intel and other platforms with simple aliasing. - Bypass expensive interference calculations and fixed FP live range processing for platforms with simple aliasing. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2101653003 Cr-Commit-Position: refs/heads/master@{#37388}
-
- 27 Jun, 2016 1 commit
-
-
bbudge authored
Replaces ArchDefault method with Crankshaft and Turbofan getters. Eliminates IsAllocated method on Register, FloatRegister, DoubleRegister. Eliminates ToString method too. Changes call sites to access appropriate arch default RegisterConfiguration. LOG=N BUG= Review-Url: https://codereview.chromium.org/2092413002 Cr-Commit-Position: refs/heads/master@{#37297}
-
- 24 Jun, 2016 1 commit
-
-
bbudge authored
- Adds the concept of FP register aliasing to RegisterConfiguration. - Changes RegisterAllocator to distinguish between FP representations when allocating. - Changes LinearScanAllocator to detect interference when FP register aliasing is combining, as on ARM. - Changes ARM code generation to allow all registers s0 - s31 to be accessed. - Adds unit tests for RegisterConfiguration, mostly to test aliasing calculations. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2086653003 Cr-Commit-Position: refs/heads/master@{#37251}
-
- 15 Jun, 2016 1 commit
-
-
bbudge authored
Review-Url: https://codereview.chromium.org/2054343002 Cr-Commit-Position: refs/heads/master@{#37013}
-
- 13 Jun, 2016 1 commit
-
-
bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2067463003 Cr-Commit-Position: refs/heads/master@{#36944}
-
- 04 Feb, 2016 1 commit
-
-
mtrofin authored
So far, we've been moving down gaps wholesale. This change moves individual move operations instead. This improves some benchmarks, and should overall reduce code size, because it improves the chance of reducing the number of moves. For example, there are improvements on x64 in Emscripten (Bullet, in particular) , JetStream geomean, Embenchen (zlib). In the process of making this change, I noticed we can separate the tasks performed by the move optimizer, as follows: - group gaps into 1 - push gaps down, jumping instructions (these 2 were together before) - merge blocks (and then push gaps down) - finalize We can do without a finalization list. This avoids duplicating storage - we already have the list of instructions; it also simplifies the logic, since, with this change, we may process an instruction's gap twice. Compile time doesn't regress much (see pathological cases), but we may want to avoid the allocations of the few sets used in the new code. I'll do that in a subsequent change. BUG= Review URL: https://codereview.chromium.org/1634093002 Cr-Commit-Position: refs/heads/master@{#33715}
-
- 27 Jan, 2016 1 commit
-
-
mtrofin authored
MoveKey used to be a std::pair. Rather than expecting the reader to remember which is "first" and "second", this change makes it a struct with specific names ("source" and "destination") BUG= Review URL: https://codereview.chromium.org/1641523002 Cr-Commit-Position: refs/heads/master@{#33536}
-
- 25 Jan, 2016 1 commit
-
-
mtrofin authored
moves, we move those to the node, and remove them from the predecessors ("merge" them to the common node). If only some of the moves are common, we don't do anything. This is what this change addresses. The bug linked below should be addressed by this change. The only difference in codegen before/after the change that introduced the bug was un-merged moves. BUG=chromium:549262 LOG=N Review URL: https://codereview.chromium.org/1527203002 Cr-Commit-Position: refs/heads/master@{#33481}
-
- 11 Jan, 2016 1 commit
-
-
titzer authored
R=bmeurer@chromium.org BUG= Review URL: https://codereview.chromium.org/1578723002 Cr-Commit-Position: refs/heads/master@{#33202}
-
- 23 Dec, 2015 1 commit
-
-
mtrofin authored
I believe the code reads easier after this change. The original code probably dates back to when we had 4 gap positions. Now that there are only 2, the logic can be simpler by avoiding a loop and instead treating each case explicitly: no gaps; gaps just at end; gaps at start and maybe end. That way, it is also easier to understand how the moves get pushed downwards. This is what got me to make this change in the first place: trying to work out a finer grained move optimization. BUG= Review URL: https://codereview.chromium.org/1543973002 Cr-Commit-Position: refs/heads/master@{#33016}
-
- 22 Dec, 2015 1 commit
-
-
mtrofin authored
There was no use for the second temp vector, and the one we are using is scoped to certain methods, and that scope can be further restricted. I'm curious if there is really any value in having the temp vector instead of allocating a function-scoped local. Will verify that separately. Review URL: https://codereview.chromium.org/1533423003 Cr-Commit-Position: refs/heads/master@{#32998}
-
- 16 Dec, 2015 2 commits
-
-
mtrofin authored
...except for 2 places (map::insert and map::find returns) [turbofan] move down parallel moves BUG= Review URL: https://codereview.chromium.org/1531453003 Cr-Commit-Position: refs/heads/master@{#32875}
-
mtrofin authored
The regression the bug tracks (see the bug link) appears to be due to identical gap moves in the predecessors of a block not being moved to the common successor. This CR fixes one reason that is happening. BUG=chromium:549262 LOG=n Review URL: https://codereview.chromium.org/1523393003 Cr-Commit-Position: refs/heads/master@{#32874}
-
- 29 Oct, 2015 1 commit
-
-
mtrofin authored
we may introduce moves that are redundant in the context of moves on subsequent instructions. Currently, we only detect such redundancies by allowing moves to skip over Nop instructions (true nops, with no input/output). We can also skip over other cases, for example over constant definitions (nop with an output), since whatever moves happen above it do not influence the instruction's outcome. We may be able to handle other cases, too - in subsequent CLs. BUG= Review URL: https://codereview.chromium.org/1422333003 Cr-Commit-Position: refs/heads/master@{#31662}
-
- 27 Oct, 2015 1 commit
-
-
danno authored
Up until now, if one wanted to specify an explicit stack location or register as an operand for an instruction, it had to also be explicitly associated with a virtual register as a so-called FixedRegister or FixedStackSlot. For the implementation of tail calls, the plan is to use the gap resolver needs to shuffle stack locations from the caller to the tail-called callee. In order to do this, it must be possible to explicitly address operand locations on the stack that are not associated with virtual registers. This CL introduces ExplictOperands, which can specify a specific register or stack location that is not associated with virtual register. This will allow tail calls to specify the target locations for the necessary stack moves in the gap for the tail call without the core register allocation having to know about the target of the stack moves at all. In the process this CL: * creates a new Operand kind, ExplicitOperand, with which instructions can specify register and stack slots without an associated virtual register. * creates a LocationOperand class from which AllocatedOperand and ExplicitOperand are derived and provides a common interface to get Register, DoubleRegister and spill slot information. * removes RegisterOperand, DoubleRegisterOperand, StackSlotOperand and DoubleStackSlotOperand, they are subsumed by LocationOperand. * addresses a cleanup TODO in AllocatedOperand to reduce the redundancy of AllocatedOperand::Kind by using machine_type() to determine if an operand corresponds to a general purpose or double register. BUG=v8:4076 LOG=n Review URL: https://codereview.chromium.org/1389373002 Cr-Commit-Position: refs/heads/master@{#31603}
-
- 06 Aug, 2015 1 commit
-
-
mtrofin authored
BUG= Review URL: https://codereview.chromium.org/1271703002 Cr-Commit-Position: refs/heads/master@{#30050}
-
- 20 May, 2015 1 commit
-
-
erikcorry authored
R=verwaest@chromium.org BUG= Review URL: https://codereview.chromium.org/1143133002 Cr-Commit-Position: refs/heads/master@{#28502}
-
- 29 Apr, 2015 2 commits
-
-
dcarney authored
- allows the optimization of emitted gap move code since the representation of the value in the register is known - necessary preparation for vector register allocation - prepare for slot sharing for any value of the same byte width TBR=jarin@chromium.org BUG= Review URL: https://codereview.chromium.org/1111323003 Cr-Commit-Position: refs/heads/master@{#28140}
-
machenbach authored
Revert of [turbofan] add MachineType to AllocatedOperand (patchset #17 id:310001 of https://codereview.chromium.org/1087793002/) Reason for revert: [Sheriff] Breaks compile on chromium asan and v8 msan: http://build.chromium.org/p/client.v8/builders/Linux%20ASAN%20Builder/builds/3446 http://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20MSAN/builds/2085 Original issue's description: > [turbofan] add MachineType to AllocatedOperand > > - allows the optimization of emitted gap move code since the representation of the value in the register is known > - necessary preparation for vector register allocation > - prepare for slot sharing for any value of the same byte width > > BUG= > > Committed: https://crrev.com/3a025d1ab6437559f86a464767aa03d2d9789f6f > Cr-Commit-Position: refs/heads/master@{#28137} TBR=jarin@chromium.org,dcarney@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review URL: https://codereview.chromium.org/1119483003 Cr-Commit-Position: refs/heads/master@{#28139}
-