[Turbofan] Revert FP register aliasing support on Arm.

- Changes register allocation to only use even numbered registers on Arm.
- Turns on float32 testing in test-gap-resolver.cc.

This is effectively a revert of:
https://codereview.chromium.org/2086653003/

LOG=N
BUG=V8:4124, V8:5202

Review-Url: https://codereview.chromium.org/2176173003
Cr-Commit-Position: refs/heads/master@{#38151}

src/compiler/instruction.cc

@@ -65,14 +65,7 @@ FlagsCondition CommuteFlagsCondition(FlagsCondition condition) {
 }
 
 bool InstructionOperand::InterferesWith(const InstructionOperand& that) const {
-  if (!IsFPRegister() || !that.IsFPRegister() || kSimpleFPAliasing)
-    return EqualsCanonicalized(that);
-  // Both operands are fp registers and aliasing is non-simple.
-  const LocationOperand& loc1 = *LocationOperand::cast(this);
-  const LocationOperand& loc2 = LocationOperand::cast(that);
-  return GetRegConfig()->AreAliases(loc1.representation(), loc1.register_code(),
-                                    loc2.representation(),
-                                    loc2.register_code());
+  return EqualsCanonicalized(that);
 }
 
 void InstructionOperand::Print(const RegisterConfiguration* config) const {

src/compiler/instruction.h

@@ -607,14 +607,8 @@ uint64_t InstructionOperand::GetCanonicalizedValue() const {
   if (IsAllocated() || IsExplicit()) {
     MachineRepresentation canonical = MachineRepresentation::kNone;
     if (IsFPRegister()) {
-      if (kSimpleFPAliasing) {
-        // We treat all FP register operands the same for simple aliasing.
-        canonical = MachineRepresentation::kFloat64;
-      } else {
-        // We need to distinguish FP register operands of different reps when
-        // aliasing is not simple (e.g. ARM).
-        canonical = LocationOperand::cast(this)->representation();
-      }
+      // We treat all FP register operands the same for simple aliasing.
+      canonical = MachineRepresentation::kFloat64;
     }
     return InstructionOperand::KindField::update(
         LocationOperand::RepresentationField::update(this->value_, canonical),

src/compiler/move-optimizer.cc

@@ -28,48 +28,20 @@ typedef ZoneMap<MoveKey, unsigned, MoveKeyCompare> MoveMap;
 typedef ZoneSet<InstructionOperand, CompareOperandModuloType> OperandSet;
 
 bool Blocks(const OperandSet& set, const InstructionOperand& operand) {
-  if (set.find(operand) != set.end()) return true;
-  // Only FP registers on archs with non-simple aliasing need extra checks.
-  if (!operand.IsFPRegister() || kSimpleFPAliasing) return false;
+  if (!operand.IsFPRegister()) return set.find(operand) != set.end();
 
-  // Check operand against operands of other FP types for interference.
   const LocationOperand& loc = LocationOperand::cast(operand);
-  MachineRepresentation rep = loc.representation();
-  MachineRepresentation other_rep1, other_rep2;
-  switch (rep) {
-    case MachineRepresentation::kFloat32:
-      other_rep1 = MachineRepresentation::kFloat64;
-      other_rep2 = MachineRepresentation::kSimd128;
-      break;
-    case MachineRepresentation::kFloat64:
-      other_rep1 = MachineRepresentation::kFloat32;
-      other_rep2 = MachineRepresentation::kSimd128;
-      break;
-    case MachineRepresentation::kSimd128:
-      other_rep1 = MachineRepresentation::kFloat32;
-      other_rep2 = MachineRepresentation::kFloat64;
-      break;
-    default:
-      UNREACHABLE();
-      break;
-  }
-  const RegisterConfiguration* config = RegisterConfiguration::Turbofan();
-  int base = -1;
-  int aliases = config->GetAliases(rep, loc.register_code(), other_rep1, &base);
-  DCHECK(aliases > 0 || (aliases == 0 && base == -1));
-  while (aliases--) {
-    if (set.find(LocationOperand(loc.kind(), loc.location_kind(), other_rep1,
-                                 base + aliases)) != set.end())
-      return true;
-  }
-  aliases = config->GetAliases(rep, loc.register_code(), other_rep2, &base);
-  DCHECK(aliases > 0 || (aliases == 0 && base == -1));
-  while (aliases--) {
-    if (set.find(LocationOperand(loc.kind(), loc.location_kind(), other_rep2,
-                                 base + aliases)) != set.end())
-      return true;
-  }
-  return false;
+  if (loc.representation() == MachineRepresentation::kFloat64) {
+    return set.find(operand) != set.end() ||
+           set.find(LocationOperand(loc.kind(), loc.location_kind(),
+                                    MachineRepresentation::kFloat32,
+                                    loc.register_code())) != set.end();
+  }
+  DCHECK_EQ(MachineRepresentation::kFloat32, loc.representation());
+  return set.find(operand) != set.end() ||
+         set.find(LocationOperand(loc.kind(), loc.location_kind(),
+                                  MachineRepresentation::kFloat64,
+                                  loc.register_code())) != set.end();
 }
 
 int FindFirstNonEmptySlot(const Instruction* instr) {

src/compiler/register-allocator.h

@@ -766,24 +766,12 @@ class RegisterAllocationData final : public ZoneObject {
   ZoneVector<TopLevelLiveRange*>& fixed_live_ranges() {
     return fixed_live_ranges_;
   }
-  ZoneVector<TopLevelLiveRange*>& fixed_float_live_ranges() {
-    return fixed_float_live_ranges_;
-  }
-  const ZoneVector<TopLevelLiveRange*>& fixed_float_live_ranges() const {
-    return fixed_float_live_ranges_;
-  }
   ZoneVector<TopLevelLiveRange*>& fixed_double_live_ranges() {
     return fixed_double_live_ranges_;
   }
   const ZoneVector<TopLevelLiveRange*>& fixed_double_live_ranges() const {
     return fixed_double_live_ranges_;
   }
-  ZoneVector<TopLevelLiveRange*>& fixed_simd128_live_ranges() {
-    return fixed_simd128_live_ranges_;
-  }
-  const ZoneVector<TopLevelLiveRange*>& fixed_simd128_live_ranges() const {
-    return fixed_simd128_live_ranges_;
-  }
   ZoneVector<BitVector*>& live_in_sets() { return live_in_sets_; }
   ZoneVector<BitVector*>& live_out_sets() { return live_out_sets_; }
   ZoneVector<SpillRange*>& spill_ranges() { return spill_ranges_; }
@@ -845,9 +833,7 @@ class RegisterAllocationData final : public ZoneObject {
   ZoneVector<BitVector*> live_out_sets_;
   ZoneVector<TopLevelLiveRange*> live_ranges_;
   ZoneVector<TopLevelLiveRange*> fixed_live_ranges_;
-  ZoneVector<TopLevelLiveRange*> fixed_float_live_ranges_;
   ZoneVector<TopLevelLiveRange*> fixed_double_live_ranges_;
-  ZoneVector<TopLevelLiveRange*> fixed_simd128_live_ranges_;
   ZoneVector<SpillRange*> spill_ranges_;
   DelayedReferences delayed_references_;
   BitVector* assigned_registers_;

src/compiler/wasm-linkage.cc

@@ -177,17 +177,6 @@ struct Allocator {
       // Allocate a floating point register/stack location.
       if (fp_offset < fp_count) {
         DoubleRegister reg = fp_regs[fp_offset++];
-#if V8_TARGET_ARCH_ARM
-        // Allocate floats using a double register, but modify the code to
-        // reflect how ARM FP registers alias.
-        // TODO(bbudge) Modify wasm linkage to allow use of all float regs.
-        if (type == kAstF32) {
-          int float_reg_code = reg.code() * 2;
-          DCHECK(float_reg_code < RegisterConfiguration::kMaxFPRegisters);
-          return regloc(DoubleRegister::from_code(float_reg_code),
-                        MachineTypeFor(type));
-        }
-#endif
         return regloc(reg, MachineTypeFor(type));
       } else {
         int offset = -1 - stack_offset;

src/register-configuration.cc

@@ -70,12 +70,15 @@ class ArchDefaultRegisterConfiguration : public RegisterConfiguration {
 #if V8_TARGET_ARCH_IA32
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
+            kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_X87
             kMaxAllocatableGeneralRegisterCount,
             compiler == TURBOFAN ? 1 : kMaxAllocatableDoubleRegisterCount,
+            compiler == TURBOFAN ? 1 : kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_X64
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
+            kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_ARM
             FLAG_enable_embedded_constant_pool
                 ? (kMaxAllocatableGeneralRegisterCount - 1)
@@ -83,21 +86,27 @@ class ArchDefaultRegisterConfiguration : public RegisterConfiguration {
             CpuFeatures::IsSupported(VFP32DREGS)
                 ? kMaxAllocatableDoubleRegisterCount
                 : (ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(REGISTER_COUNT) 0),
+            ALLOCATABLE_NO_VFP32_DOUBLE_REGISTERS(REGISTER_COUNT) 0,
 #elif V8_TARGET_ARCH_ARM64
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
+            kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_MIPS
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
+            kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_MIPS64
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
+            kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_PPC
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
+            kMaxAllocatableDoubleRegisterCount,
 #elif V8_TARGET_ARCH_S390
             kMaxAllocatableGeneralRegisterCount,
             kMaxAllocatableDoubleRegisterCount,
+            kMaxAllocatableDoubleRegisterCount,
 #else
 #error Unsupported target architecture.
 #endif
@@ -136,6 +145,7 @@ const RegisterConfiguration* RegisterConfiguration::Turbofan() {
 RegisterConfiguration::RegisterConfiguration(
     int num_general_registers, int num_double_registers,
     int num_allocatable_general_registers, int num_allocatable_double_registers,
+    int num_allocatable_aliased_double_registers,
     const int* allocatable_general_codes, const int* allocatable_double_codes,
     AliasingKind fp_aliasing_kind, const char* const* general_register_names,
     const char* const* float_register_names,
@@ -148,6 +158,8 @@ RegisterConfiguration::RegisterConfiguration(
       num_allocatable_general_registers_(num_allocatable_general_registers),
       num_allocatable_float_registers_(0),
       num_allocatable_double_registers_(num_allocatable_double_registers),
+      num_allocatable_aliased_double_registers_(
+          num_allocatable_aliased_double_registers),
       num_allocatable_simd128_registers_(0),
       allocatable_general_codes_mask_(0),
       allocatable_float_codes_mask_(0),

src/register-configuration.h

@@ -35,6 +35,7 @@ class RegisterConfiguration {
   RegisterConfiguration(int num_general_registers, int num_double_registers,
                         int num_allocatable_general_registers,
                         int num_allocatable_double_registers,
+                        int num_allocatable_aliased_double_registers,
                         const int* allocatable_general_codes,
                         const int* allocatable_double_codes,
                         AliasingKind fp_aliasing_kind,
@@ -56,6 +57,12 @@ class RegisterConfiguration {
   int num_allocatable_double_registers() const {
     return num_allocatable_double_registers_;
   }
+  // TODO(bbudge): This is a temporary work-around required because our
+  // register allocator does not yet support the aliasing of single/double
+  // registers on ARM.
+  int num_allocatable_aliased_double_registers() const {
+    return num_allocatable_aliased_double_registers_;
+  }
   int num_allocatable_simd128_registers() const {
     return num_allocatable_simd128_registers_;
   }
@@ -135,6 +142,7 @@ class RegisterConfiguration {
   int num_allocatable_general_registers_;
   int num_allocatable_float_registers_;
   int num_allocatable_double_registers_;
+  int num_allocatable_aliased_double_registers_;
   int num_allocatable_simd128_registers_;
   int32_t allocatable_general_codes_mask_;
   int32_t allocatable_float_codes_mask_;

test/cctest/compiler/test-gap-resolver.cc

@@ -83,8 +83,7 @@ class InterpreterState {
       const LocationOperand& loc_op = LocationOperand::cast(op);
       if (loc_op.IsAnyRegister()) {
         if (loc_op.IsFPRegister()) {
-          rep = kSimpleFPAliasing ? MachineRepresentation::kFloat64
-                                  : loc_op.representation();
+          rep = MachineRepresentation::kFloat64;
         }
         index = loc_op.register_code();
       } else {
@@ -186,10 +185,7 @@ class ParallelMoveCreator : public HandleAndZoneScope {
       case 1:
         return MachineRepresentation::kWord64;
       case 2:
-        // TODO(bbudge) Re-enable float operands when GapResolver correctly
-        // handles FP aliasing.
-        return kSimpleFPAliasing ? MachineRepresentation::kFloat32
-                                 : MachineRepresentation::kFloat64;
+        return MachineRepresentation::kFloat32;
       case 3:
         return MachineRepresentation::kFloat64;
       case 4:
@@ -205,13 +201,18 @@ class ParallelMoveCreator : public HandleAndZoneScope {
     auto GetRegisterCode = [&conf](MachineRepresentation rep, int index) {
       switch (rep) {
         case MachineRepresentation::kFloat32:
+#if V8_TARGET_ARCH_ARM
+          // Only even number float registers are used on Arm.
+          // TODO(bbudge) Eliminate this when FP register aliasing works.
+          return conf->RegisterConfiguration::GetAllocatableDoubleCode(index) *
+                 2;
+#endif
+        // Fall through on non-Arm targets.
         case MachineRepresentation::kFloat64:
           return conf->RegisterConfiguration::GetAllocatableDoubleCode(index);
-          break;
 
         default:
           return conf->RegisterConfiguration::GetAllocatableGeneralCode(index);
-          break;
       }
       UNREACHABLE();
       return static_cast<int>(Register::kCode_no_reg);

test/cctest/compiler/test-run-native-calls.cc

@@ -87,16 +87,8 @@ class RegisterPairs : public Pairs {
 class Float32RegisterPairs : public Pairs {
  public:
   Float32RegisterPairs()
-      : Pairs(
-            100,
-#if V8_TARGET_ARCH_ARM
-            // TODO(bbudge) Modify wasm linkage to allow use of all float regs.
-            GetRegConfig()->num_allocatable_double_registers() / 2 - 2,
-#else
-            GetRegConfig()->num_allocatable_double_registers(),
-#endif
-            GetRegConfig()->allocatable_double_codes()) {
-  }
+      : Pairs(100, GetRegConfig()->num_allocatable_aliased_double_registers(),
+              GetRegConfig()->allocatable_double_codes()) {}
 };
 
 
@@ -135,10 +127,6 @@ struct Allocator {
       // Allocate a floating point register/stack location.
       if (fp_offset < fp_count) {
         int code = fp_regs[fp_offset++];
-#if V8_TARGET_ARCH_ARM
-        // TODO(bbudge) Modify wasm linkage to allow use of all float regs.
-        if (type.representation() == MachineRepresentation::kFloat32) code *= 2;
-#endif
         return LinkageLocation::ForRegister(code, type);
       } else {
         int offset = -1 - stack_offset;

test/unittests/compiler/instruction-sequence-unittest.cc

@@ -67,7 +67,8 @@ RegisterConfiguration* InstructionSequenceTest::config() {
   if (!config_) {
     config_.reset(new RegisterConfiguration(
         num_general_registers_, num_double_registers_, num_general_registers_,
-        num_double_registers_, allocatable_codes, allocatable_double_codes,
+        num_double_registers_, num_double_registers_, allocatable_codes,
+        allocatable_double_codes,
         kSimpleFPAliasing ? RegisterConfiguration::OVERLAP
                           : RegisterConfiguration::COMBINE,
         general_register_names_,

test/unittests/register-configuration-unittest.cc

@@ -30,8 +30,9 @@ TEST_F(RegisterConfigurationUnitTest, BasicProperties) {
 
   RegisterConfiguration test(
       kNumGeneralRegs, kNumDoubleRegs, kNumAllocatableGeneralRegs,
-      kNumAllocatableDoubleRegs, general_codes, double_codes,
-      RegisterConfiguration::OVERLAP, nullptr, nullptr, nullptr, nullptr);
+      kNumAllocatableDoubleRegs, kNumAllocatableDoubleRegs, general_codes,
+      double_codes, RegisterConfiguration::OVERLAP, nullptr, nullptr, nullptr,
+      nullptr);
 
   EXPECT_EQ(test.num_general_registers(), kNumGeneralRegs);
   EXPECT_EQ(test.num_double_registers(), kNumDoubleRegs);
@@ -66,8 +67,9 @@ TEST_F(RegisterConfigurationUnitTest, CombineAliasing) {
 
   RegisterConfiguration test(
       kNumGeneralRegs, kNumDoubleRegs, kNumAllocatableGeneralRegs,
-      kNumAllocatableDoubleRegs, general_codes, double_codes,
-      RegisterConfiguration::COMBINE, nullptr, nullptr, nullptr, nullptr);
+      kNumAllocatableDoubleRegs, kNumAllocatableDoubleRegs, general_codes,
+      double_codes, RegisterConfiguration::COMBINE, nullptr, nullptr, nullptr,
+      nullptr);
 
   // There are 3 allocatable double regs, but only 2 can alias float regs.
   EXPECT_EQ(test.num_allocatable_float_registers(), 4);