Commit 8f42679a authored by Bill Budge's avatar Bill Budge Committed by Commit Bot

[compiler] Bypass FP register allocation if there are no FP vregs

- Cleans up existing code that tests for representations using a
  bitmask.
- Bypass FP register allocation for sequences without FP vregs.

Change-Id: I5ff32e80e0c33848ba83ee17f786b01e37821aa2
Reviewed-on: https://chromium-review.googlesource.com/1195528
Commit-Queue: Bill Budge <bbudge@chromium.org>
Reviewed-by: 's avatarJaroslav Sevcik <jarin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#55535}
parent 09a717db
......@@ -13,10 +13,10 @@ namespace compiler {
namespace {
#define REP_BIT(rep) (1 << static_cast<int>(rep))
const int kFloat32Bit = REP_BIT(MachineRepresentation::kFloat32);
const int kFloat64Bit = REP_BIT(MachineRepresentation::kFloat64);
static constexpr int kFloat32Bit =
RepresentationBit(MachineRepresentation::kFloat32);
static constexpr int kFloat64Bit =
RepresentationBit(MachineRepresentation::kFloat64);
// Splits a FP move between two location operands into the equivalent series of
// moves between smaller sub-operands, e.g. a double move to two single moves.
......@@ -91,8 +91,8 @@ void GapResolver::Resolve(ParallelMove* moves) {
}
i++;
if (!kSimpleFPAliasing && move->destination().IsFPRegister()) {
reps |=
REP_BIT(LocationOperand::cast(move->destination()).representation());
reps |= RepresentationBit(
LocationOperand::cast(move->destination()).representation());
}
}
......
......@@ -942,7 +942,7 @@ void InstructionSequence::MarkAsRepresentation(MachineRepresentation rep,
DCHECK_IMPLIES(representations_[virtual_register] != rep,
representations_[virtual_register] == DefaultRepresentation());
representations_[virtual_register] = rep;
representation_mask_ |= 1 << static_cast<int>(rep);
representation_mask_ |= RepresentationBit(rep);
}
int InstructionSequence::AddDeoptimizationEntry(
......
......@@ -1520,7 +1520,6 @@ class V8_EXPORT_PRIVATE InstructionSequence final
}
MachineRepresentation GetRepresentation(int virtual_register) const;
void MarkAsRepresentation(MachineRepresentation rep, int virtual_register);
int representation_mask() const { return representation_mask_; }
bool IsReference(int virtual_register) const {
return CanBeTaggedPointer(GetRepresentation(virtual_register));
......@@ -1528,6 +1527,14 @@ class V8_EXPORT_PRIVATE InstructionSequence final
bool IsFP(int virtual_register) const {
return IsFloatingPoint(GetRepresentation(virtual_register));
}
int representation_mask() const { return representation_mask_; }
bool HasFPVirtualRegisters() const {
constexpr int kFPRepMask =
RepresentationBit(MachineRepresentation::kFloat32) |
RepresentationBit(MachineRepresentation::kFloat64) |
RepresentationBit(MachineRepresentation::kSimd128);
return (representation_mask() & kFPRepMask) != 0;
}
Instruction* GetBlockStart(RpoNumber rpo) const;
......
......@@ -37,7 +37,7 @@ class OperandSet {
set_->push_back(op);
if (!kSimpleFPAliasing && op.IsFPRegister())
fp_reps_ |= RepBit(LocationOperand::cast(op).representation());
fp_reps_ |= RepresentationBit(LocationOperand::cast(op).representation());
}
bool Contains(const InstructionOperand& op) const {
......@@ -55,7 +55,7 @@ class OperandSet {
const LocationOperand& loc = LocationOperand::cast(op);
MachineRepresentation rep = loc.representation();
// If haven't encountered mixed rep FP registers, skip the extra checks.
if (!HasMixedFPReps(fp_reps_ | RepBit(rep))) return false;
if (!HasMixedFPReps(fp_reps_ | RepresentationBit(rep))) return false;
// Check register against aliasing registers of other FP representations.
MachineRepresentation other_rep1, other_rep2;
......@@ -100,10 +100,6 @@ class OperandSet {
}
private:
static int RepBit(MachineRepresentation rep) {
return 1 << static_cast<int>(rep);
}
static bool HasMixedFPReps(int reps) {
return reps && !base::bits::IsPowerOfTwo(reps);
}
......
......@@ -2620,7 +2620,10 @@ void PipelineImpl::AllocateRegisters(const RegisterConfiguration* config,
}
Run<AllocateGeneralRegistersPhase<LinearScanAllocator>>();
Run<AllocateFPRegistersPhase<LinearScanAllocator>>();
if (data->sequence()->HasFPVirtualRegisters()) {
Run<AllocateFPRegistersPhase<LinearScanAllocator>>();
}
if (FLAG_turbo_preprocess_ranges) {
Run<MergeSplintersPhase>();
......
......@@ -21,10 +21,10 @@ namespace compiler {
namespace {
static const int kFloatRepBit =
1 << static_cast<int>(MachineRepresentation::kFloat32);
static const int kSimd128RepBit =
1 << static_cast<int>(MachineRepresentation::kSimd128);
static constexpr int kFloat32Bit =
RepresentationBit(MachineRepresentation::kFloat32);
static constexpr int kSimd128Bit =
RepresentationBit(MachineRepresentation::kSimd128);
void RemoveElement(ZoneVector<LiveRange*>* v, LiveRange* range) {
auto it = std::find(v->begin(), v->end(), range);
......@@ -2041,8 +2041,8 @@ void LiveRangeBuilder::ProcessInstructions(const InstructionBlock* block,
bool fixed_simd128_live_ranges = false;
if (!kSimpleFPAliasing) {
int mask = data()->code()->representation_mask();
fixed_float_live_ranges = (mask & kFloatRepBit) != 0;
fixed_simd128_live_ranges = (mask & kSimd128RepBit) != 0;
fixed_float_live_ranges = (mask & kFloat32Bit) != 0;
fixed_simd128_live_ranges = (mask & kSimd128Bit) != 0;
}
for (int index = block->last_instruction_index(); index >= block_start;
......@@ -2556,7 +2556,7 @@ RegisterAllocator::RegisterAllocator(RegisterAllocationData* data,
check_fp_aliasing_(false) {
if (!kSimpleFPAliasing && kind == FP_REGISTERS) {
check_fp_aliasing_ = (data->code()->representation_mask() &
(kFloatRepBit | kSimd128RepBit)) != 0;
(kFloat32Bit | kSimd128Bit)) != 0;
}
}
......
......@@ -298,6 +298,12 @@ V8_EXPORT_PRIVATE inline int ElementSizeInBytes(MachineRepresentation rep) {
return 1 << ElementSizeLog2Of(rep);
}
// Converts representation to bit for representation masks.
V8_EXPORT_PRIVATE inline constexpr int RepresentationBit(
MachineRepresentation rep) {
return 1 << static_cast<int>(rep);
}
} // namespace internal
} // namespace v8
......
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