- 20 Apr, 2016 2 commits
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titzer authored
Also factor out test cases from test-run-machops.cc into test-run-load-store.cc BUG=chromium:599717 LOG=Y Review URL: https://codereview.chromium.org/1858323003 Cr-Commit-Position: refs/heads/master@{#35651}
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mtrofin authored
Before frame elision, we finalized the frame shape when assembling the prologue, which is also when we prepared the frame (saving sp, etc). The frame finalization only needs to happen once, and happens to be actually a set of idempotent operations. With frame elision, the logic for frame finalization was happening every time we constructed the frame. Albeit idempotent operations, the code would become hard to maintain. This change separates frame shape finalization from frame construction. When constructing the CodeGenerator, we finalize the frame. Subsequent access is to a const Frame*. Also renamed AssemblePrologue to AssembleConstructFrame, as suggested in the frame elision CR. Separating frame setup gave the opportunity to do away with architecture-independent frame aligning (which is something just arm64 cares about), and also with stack pointer setup (also arm64). Both of these happen now at frame finalization on arm64. BUG= Review URL: https://codereview.chromium.org/1843143002 Cr-Commit-Position: refs/heads/master@{#35642}
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- 24 Feb, 2016 1 commit
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bmeurer authored
These macro operators represent a conditional eager deoptimization exit without explicit branching, which greatly reduces overhead of both scheduling and register allocation, and thereby greatly reduces overall compilation time, esp. when there are a lot of eager deoptimization exits. R=jarin@chromium.org Review URL: https://codereview.chromium.org/1721103003 Cr-Commit-Position: refs/heads/master@{#34239}
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- 24 Nov, 2015 1 commit
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danno authored
Some highlights of this CL: * Refactor the mutable state out of Frame into FrameAccessState, which is maintained and updated during code generation to record whether sp- or fp-based frame access is currently active and how deep the stack on top of the frame is. * The operand resultion in linkage.cc now uses FrameAccessState to determine how to generate frame-accessing operands. * Update all platforms to accurately track additionally pushed stack slots (e.g. arguments for calls) in the FrameAccessState. * Add a flag, --turbo_sp_frame_access, which forces all frame access to be sp-based whenever possible. This will likely never be used in production, but for testing it's useful in verifying that the stack-tracking of each platform maintained in the FrameAccessState is correct. * Use sp-based frame access for gap resolving before tail calls. This will allow for slightly more efficient restoration of the frame pointer in the tail call in a later CL. * Remove most ad hoc groping into CallDescriptors to determine if a frame is needed, instead consistently use predicates like needs_frame(), IsCFunctionCall() and IsJSFunctionCall(). BUG=v8:4076 LOG=n Review URL: https://codereview.chromium.org/1460183002 Cr-Commit-Position: refs/heads/master@{#32234}
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- 10 Nov, 2015 1 commit
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bmeurer authored
Avoid write barriers when storing values in the root set, and use cheaper write barriers for storing maps or tagged pointers. Also improve the generated code for write barriers, utilizing the out of line code mechanism that is available to TurboFan backends, which moves the unlikely case out of the hot path. R=jarin@chromium.org, mstarzinger@chromium.org Review URL: https://codereview.chromium.org/1414183006 Cr-Commit-Position: refs/heads/master@{#31914}
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- 27 Oct, 2015 1 commit
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danno authored
Up until now, if one wanted to specify an explicit stack location or register as an operand for an instruction, it had to also be explicitly associated with a virtual register as a so-called FixedRegister or FixedStackSlot. For the implementation of tail calls, the plan is to use the gap resolver needs to shuffle stack locations from the caller to the tail-called callee. In order to do this, it must be possible to explicitly address operand locations on the stack that are not associated with virtual registers. This CL introduces ExplictOperands, which can specify a specific register or stack location that is not associated with virtual register. This will allow tail calls to specify the target locations for the necessary stack moves in the gap for the tail call without the core register allocation having to know about the target of the stack moves at all. In the process this CL: * creates a new Operand kind, ExplicitOperand, with which instructions can specify register and stack slots without an associated virtual register. * creates a LocationOperand class from which AllocatedOperand and ExplicitOperand are derived and provides a common interface to get Register, DoubleRegister and spill slot information. * removes RegisterOperand, DoubleRegisterOperand, StackSlotOperand and DoubleStackSlotOperand, they are subsumed by LocationOperand. * addresses a cleanup TODO in AllocatedOperand to reduce the redundancy of AllocatedOperand::Kind by using machine_type() to determine if an operand corresponds to a general purpose or double register. BUG=v8:4076 LOG=n Review URL: https://codereview.chromium.org/1389373002 Cr-Commit-Position: refs/heads/master@{#31603}
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- 14 Oct, 2015 1 commit
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martyn.capewell authored
Support negate with shifted input on ARM64 by supporting lhs zero registers for binary operations, and removing explicit Neg instruction support. Review URL: https://codereview.chromium.org/1404093003 Cr-Commit-Position: refs/heads/master@{#31263}
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- 02 Oct, 2015 3 commits
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf Cr-Commit-Position: refs/heads/master@{#31075} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31087}
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danno authored
Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on MIPS Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} > > Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf > Cr-Commit-Position: refs/heads/master@{#31075} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1380863004 Cr-Commit-Position: refs/heads/master@{#31083}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31075}
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- 24 Sep, 2015 3 commits
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danno authored
Revert of Remove register index/code indirection (patchset #17 id:320001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on greedy RegAlloc, Fuzzer Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1365073002 Cr-Commit-Position: refs/heads/master@{#30914}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#30913}
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martyn.capewell authored
Reduce operations of the form f64cmp(fp32to64(x), k) to f32cmp(x, k) when k can be encoded as a 32-bit float. Review URL: https://codereview.chromium.org/1365623002 Cr-Commit-Position: refs/heads/master@{#30909}
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- 25 Jun, 2015 1 commit
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Benedikt Meurer authored
This introduces some initial building blocks for calling out to C/C++ functions directly from TurboFan generated code objects. R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/1205023002. Cr-Commit-Position: refs/heads/master@{#29279}
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- 09 Apr, 2015 2 commits
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dcarney authored
R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/1075903002 Cr-Commit-Position: refs/heads/master@{#27709}
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dcarney authored
- ConstantOperand was using a too-small field too store its virtual register - drop ConvertTo, replace it with simple copy - split AllocatedOperand off from Immediate and Constant to make assignment clearer, also paving the way for small Immediates - put zone first in *Operand::New - driveby: drop delayed ssa deconstruction experiment R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/1050803002 Cr-Commit-Position: refs/heads/master@{#27692}
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- 25 Feb, 2015 1 commit
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dcarney authored
BUG= Review URL: https://codereview.chromium.org/951553005 Cr-Commit-Position: refs/heads/master@{#26859}
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- 23 Feb, 2015 1 commit
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bmeurer authored
R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/946553002 Cr-Commit-Position: refs/heads/master@{#26789}
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- 09 Feb, 2015 1 commit
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bmeurer authored
Adds Switch and Case operators to TurboFan and handles them appropriately in instruction selection and code generation. BUG=v8:3872 LOG=n Review URL: https://codereview.chromium.org/892513003 Cr-Commit-Position: refs/heads/master@{#26515}
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- 02 Dec, 2014 1 commit
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Benedikt Meurer authored
TEST=mjsunit,cctest,unittests R=jarin@chromium.org Review URL: https://codereview.chromium.org/763963002 Cr-Commit-Position: refs/heads/master@{#25591}
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- 26 Nov, 2014 1 commit
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titzer authored
R=dcarney@chromium.org BUG= Review URL: https://codereview.chromium.org/758073002 Cr-Commit-Position: refs/heads/master@{#25508}
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- 06 Nov, 2014 1 commit
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dcarney@chromium.org authored
R=bmeurer@chromium.org BUG= Review URL: https://codereview.chromium.org/707803002 Cr-Commit-Position: refs/heads/master@{#25201} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25201 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 30 Oct, 2014 1 commit
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dcarney@chromium.org authored
T=jarin@chromium.org BUG= R=jarin@chromium.org Review URL: https://codereview.chromium.org/688633002 Cr-Commit-Position: refs/heads/master@{#25008} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25008 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 14 Oct, 2014 1 commit
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dcarney@chromium.org authored
R=bmeurer@chromium.org BUG= Review URL: https://codereview.chromium.org/646393002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24584 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 30 Sep, 2014 1 commit
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jarin@chromium.org authored
To manage BasicBlock's predecessors and successors we now use plain std::vector. The change also moves bunch of method definitions from header files to implementation files. In zlib, the change brings 3x improvement in the scheduler's memory consumption. The --turbo-stats flag says we go 169MB -> 55MB in the scheduler, 383MB -> 268MB overall. BUG= R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/606403003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24308 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 08 Aug, 2014 1 commit
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bmeurer@chromium.org authored
LOG=y BUG=v8:3489 R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/457503002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22987 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 06 Aug, 2014 2 commits
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bmeurer@chromium.org authored
This reverts commit r22927 for breaking build. TBR=svenpanne@chromium.org Review URL: https://codereview.chromium.org/448663002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22928 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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bmeurer@chromium.org authored
TEST=compiler-unittests BUG=v8:3489 LOG=y R=svenpanne@chromium.org, jochen@chromium.org Review URL: https://codereview.chromium.org/447563003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22927 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 04 Aug, 2014 1 commit
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bmeurer@chromium.org authored
This way we don't clash with the ASSERT* macros defined by GoogleTest, and we are one step closer to being able to replace our homegrown base/ with base/ from Chrome. R=jochen@chromium.org, svenpanne@chromium.org Review URL: https://codereview.chromium.org/430503007 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22812 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 01 Aug, 2014 1 commit
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bmeurer@chromium.org authored
TEST=cctest/test-run-machops,cctest/test-instruction-selector-arm R=titzer@chromium.org Review URL: https://codereview.chromium.org/436593002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22784 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 30 Jul, 2014 1 commit
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danno@chromium.org authored
R=mstarzinger@chromium.org Review URL: https://codereview.chromium.org/426233002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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