Commit 9c1407da authored by bmeurer's avatar bmeurer Committed by Commit bot

[turbofan] Fix several int vs size_t issues.

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/946553002

Cr-Commit-Position: refs/heads/master@{#26789}
parent 82368b17
......@@ -26,11 +26,11 @@ class ArmOperandConverter FINAL : public InstructionOperandConverter {
ArmOperandConverter(CodeGenerator* gen, Instruction* instr)
: InstructionOperandConverter(gen, instr) {}
SwVfpRegister OutputFloat32Register(int index = 0) {
SwVfpRegister OutputFloat32Register(size_t index = 0) {
return ToFloat32Register(instr_->OutputAt(index));
}
SwVfpRegister InputFloat32Register(int index) {
SwVfpRegister InputFloat32Register(size_t index) {
return ToFloat32Register(instr_->InputAt(index));
}
......@@ -38,11 +38,11 @@ class ArmOperandConverter FINAL : public InstructionOperandConverter {
return ToFloat64Register(op).low();
}
LowDwVfpRegister OutputFloat64Register(int index = 0) {
LowDwVfpRegister OutputFloat64Register(size_t index = 0) {
return ToFloat64Register(instr_->OutputAt(index));
}
LowDwVfpRegister InputFloat64Register(int index) {
LowDwVfpRegister InputFloat64Register(size_t index) {
return ToFloat64Register(instr_->InputAt(index));
}
......@@ -62,7 +62,7 @@ class ArmOperandConverter FINAL : public InstructionOperandConverter {
return LeaveCC;
}
Operand InputImmediate(int index) {
Operand InputImmediate(size_t index) {
Constant constant = ToConstant(instr_->InputAt(index));
switch (constant.type()) {
case Constant::kInt32:
......@@ -83,8 +83,8 @@ class ArmOperandConverter FINAL : public InstructionOperandConverter {
return Operand::Zero();
}
Operand InputOperand2(int first_index) {
const int index = first_index;
Operand InputOperand2(size_t first_index) {
const size_t index = first_index;
switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None:
case kMode_Offset_RI:
......@@ -115,8 +115,8 @@ class ArmOperandConverter FINAL : public InstructionOperandConverter {
return Operand::Zero();
}
MemOperand InputOffset(int* first_index) {
const int index = *first_index;
MemOperand InputOffset(size_t* first_index) {
const size_t index = *first_index;
switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None:
case kMode_Operand2_I:
......@@ -141,7 +141,7 @@ class ArmOperandConverter FINAL : public InstructionOperandConverter {
return MemOperand(r0);
}
MemOperand InputOffset(int first_index = 0) {
MemOperand InputOffset(size_t first_index = 0) {
return InputOffset(&first_index);
}
......@@ -620,7 +620,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
DCHECK_EQ(LeaveCC, i.OutputSBit());
break;
case kArmStrb: {
int index = 0;
size_t index = 0;
MemOperand operand = i.InputOffset(&index);
__ strb(i.InputRegister(index), operand);
DCHECK_EQ(LeaveCC, i.OutputSBit());
......@@ -633,7 +633,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ ldrsh(i.OutputRegister(), i.InputOffset());
break;
case kArmStrh: {
int index = 0;
size_t index = 0;
MemOperand operand = i.InputOffset(&index);
__ strh(i.InputRegister(index), operand);
DCHECK_EQ(LeaveCC, i.OutputSBit());
......@@ -643,7 +643,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ ldr(i.OutputRegister(), i.InputOffset());
break;
case kArmStr: {
int index = 0;
size_t index = 0;
MemOperand operand = i.InputOffset(&index);
__ str(i.InputRegister(index), operand);
DCHECK_EQ(LeaveCC, i.OutputSBit());
......@@ -655,7 +655,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
break;
}
case kArmVstrF32: {
int index = 0;
size_t index = 0;
MemOperand operand = i.InputOffset(&index);
__ vstr(i.InputFloat32Register(index), operand);
DCHECK_EQ(LeaveCC, i.OutputSBit());
......@@ -666,7 +666,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
DCHECK_EQ(LeaveCC, i.OutputSBit());
break;
case kArmVstrF64: {
int index = 0;
size_t index = 0;
MemOperand operand = i.InputOffset(&index);
__ vstr(i.InputFloat64Register(index), operand);
DCHECK_EQ(LeaveCC, i.OutputSBit());
......
......@@ -23,11 +23,11 @@ class Arm64OperandConverter FINAL : public InstructionOperandConverter {
Arm64OperandConverter(CodeGenerator* gen, Instruction* instr)
: InstructionOperandConverter(gen, instr) {}
DoubleRegister InputFloat32Register(int index) {
DoubleRegister InputFloat32Register(size_t index) {
return InputDoubleRegister(index).S();
}
DoubleRegister InputFloat64Register(int index) {
DoubleRegister InputFloat64Register(size_t index) {
return InputDoubleRegister(index);
}
......@@ -35,21 +35,23 @@ class Arm64OperandConverter FINAL : public InstructionOperandConverter {
DoubleRegister OutputFloat64Register() { return OutputDoubleRegister(); }
Register InputRegister32(int index) {
Register InputRegister32(size_t index) {
return ToRegister(instr_->InputAt(index)).W();
}
Register InputRegister64(int index) { return InputRegister(index); }
Register InputRegister64(size_t index) { return InputRegister(index); }
Operand InputImmediate(int index) {
Operand InputImmediate(size_t index) {
return ToImmediate(instr_->InputAt(index));
}
Operand InputOperand(int index) { return ToOperand(instr_->InputAt(index)); }
Operand InputOperand(size_t index) {
return ToOperand(instr_->InputAt(index));
}
Operand InputOperand64(int index) { return InputOperand(index); }
Operand InputOperand64(size_t index) { return InputOperand(index); }
Operand InputOperand32(int index) {
Operand InputOperand32(size_t index) {
return ToOperand32(instr_->InputAt(index));
}
......@@ -57,7 +59,7 @@ class Arm64OperandConverter FINAL : public InstructionOperandConverter {
Register OutputRegister32() { return ToRegister(instr_->Output()).W(); }
Operand InputOperand2_32(int index) {
Operand InputOperand2_32(size_t index) {
switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None:
return InputOperand32(index);
......@@ -77,7 +79,7 @@ class Arm64OperandConverter FINAL : public InstructionOperandConverter {
return Operand(-1);
}
Operand InputOperand2_64(int index) {
Operand InputOperand2_64(size_t index) {
switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None:
return InputOperand64(index);
......@@ -97,8 +99,8 @@ class Arm64OperandConverter FINAL : public InstructionOperandConverter {
return Operand(-1);
}
MemOperand MemoryOperand(int* first_index) {
const int index = *first_index;
MemOperand MemoryOperand(size_t* first_index) {
const size_t index = *first_index;
switch (AddressingModeField::decode(instr_->opcode())) {
case kMode_None:
case kMode_Operand2_R_LSL_I:
......@@ -117,7 +119,7 @@ class Arm64OperandConverter FINAL : public InstructionOperandConverter {
return MemOperand(no_reg);
}
MemOperand MemoryOperand(int first_index = 0) {
MemOperand MemoryOperand(size_t first_index = 0) {
return MemoryOperand(&first_index);
}
......
......@@ -27,49 +27,53 @@ class InstructionOperandConverter {
// -- Instruction operand accesses with conversions --------------------------
Register InputRegister(int index) {
Register InputRegister(size_t index) {
return ToRegister(instr_->InputAt(index));
}
DoubleRegister InputDoubleRegister(int index) {
DoubleRegister InputDoubleRegister(size_t index) {
return ToDoubleRegister(instr_->InputAt(index));
}
double InputDouble(int index) { return ToDouble(instr_->InputAt(index)); }
double InputDouble(size_t index) { return ToDouble(instr_->InputAt(index)); }
int32_t InputInt32(int index) {
int32_t InputInt32(size_t index) {
return ToConstant(instr_->InputAt(index)).ToInt32();
}
int8_t InputInt8(int index) { return static_cast<int8_t>(InputInt32(index)); }
int8_t InputInt8(size_t index) {
return static_cast<int8_t>(InputInt32(index));
}
int16_t InputInt16(int index) {
int16_t InputInt16(size_t index) {
return static_cast<int16_t>(InputInt32(index));
}
uint8_t InputInt5(int index) {
uint8_t InputInt5(size_t index) {
return static_cast<uint8_t>(InputInt32(index) & 0x1F);
}
uint8_t InputInt6(int index) {
uint8_t InputInt6(size_t index) {
return static_cast<uint8_t>(InputInt32(index) & 0x3F);
}
Handle<HeapObject> InputHeapObject(int index) {
Handle<HeapObject> InputHeapObject(size_t index) {
return ToHeapObject(instr_->InputAt(index));
}
Label* InputLabel(int index) { return ToLabel(instr_->InputAt(index)); }
Label* InputLabel(size_t index) { return ToLabel(instr_->InputAt(index)); }
BasicBlock::RpoNumber InputRpo(int index) {
BasicBlock::RpoNumber InputRpo(size_t index) {
return ToRpoNumber(instr_->InputAt(index));
}
Register OutputRegister(int index = 0) {
Register OutputRegister(size_t index = 0) {
return ToRegister(instr_->OutputAt(index));
}
Register TempRegister(int index) { return ToRegister(instr_->TempAt(index)); }
Register TempRegister(size_t index) {
return ToRegister(instr_->TempAt(index));
}
DoubleRegister OutputDoubleRegister() {
return ToDoubleRegister(instr_->Output());
......
......@@ -199,10 +199,8 @@ void CodeGenerator::AssembleInstruction(Instruction* instr) {
if (mode == kFlags_branch) {
// Assemble a branch after this instruction.
InstructionOperandConverter i(this, instr);
BasicBlock::RpoNumber true_rpo =
i.InputRpo(static_cast<int>(instr->InputCount()) - 2);
BasicBlock::RpoNumber false_rpo =
i.InputRpo(static_cast<int>(instr->InputCount()) - 1);
BasicBlock::RpoNumber true_rpo = i.InputRpo(instr->InputCount() - 2);
BasicBlock::RpoNumber false_rpo = i.InputRpo(instr->InputCount() - 1);
if (true_rpo == false_rpo) {
// redundant branch.
......@@ -401,8 +399,8 @@ int CodeGenerator::DefineDeoptimizationLiteral(Handle<Object> literal) {
FrameStateDescriptor* CodeGenerator::GetFrameStateDescriptor(
Instruction* instr, size_t frame_state_offset) {
InstructionOperandConverter i(this, instr);
InstructionSequence::StateId state_id = InstructionSequence::StateId::FromInt(
i.InputInt32(static_cast<int>(frame_state_offset)));
InstructionSequence::StateId state_id =
InstructionSequence::StateId::FromInt(i.InputInt32(frame_state_offset));
return code()->GetFrameStateDescriptor(state_id);
}
......
......@@ -24,9 +24,11 @@ class IA32OperandConverter : public InstructionOperandConverter {
IA32OperandConverter(CodeGenerator* gen, Instruction* instr)
: InstructionOperandConverter(gen, instr) {}
Operand InputOperand(int index) { return ToOperand(instr_->InputAt(index)); }
Operand InputOperand(size_t index) {
return ToOperand(instr_->InputAt(index));
}
Immediate InputImmediate(int index) {
Immediate InputImmediate(size_t index) {
return ToImmediate(instr_->InputAt(index));
}
......@@ -75,8 +77,8 @@ class IA32OperandConverter : public InstructionOperandConverter {
return Immediate(-1);
}
static int NextOffset(int* offset) {
int i = *offset;
static size_t NextOffset(size_t* offset) {
size_t i = *offset;
(*offset)++;
return i;
}
......@@ -91,7 +93,7 @@ class IA32OperandConverter : public InstructionOperandConverter {
return static_cast<ScaleFactor>(scale);
}
Operand MemoryOperand(int* offset) {
Operand MemoryOperand(size_t* offset) {
AddressingMode mode = AddressingModeField::decode(instr_->opcode());
switch (mode) {
case kMode_MR: {
......@@ -154,7 +156,7 @@ class IA32OperandConverter : public InstructionOperandConverter {
return Operand(no_reg, 0);
}
Operand MemoryOperand(int first_input = 0) {
Operand MemoryOperand(size_t first_input = 0) {
return MemoryOperand(&first_input);
}
};
......@@ -162,7 +164,7 @@ class IA32OperandConverter : public InstructionOperandConverter {
namespace {
bool HasImmediateInput(Instruction* instr, int index) {
bool HasImmediateInput(Instruction* instr, size_t index) {
return instr->InputAt(index)->IsImmediate();
}
......@@ -554,7 +556,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ movzx_b(i.OutputRegister(), i.MemoryOperand());
break;
case kIA32Movb: {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
if (HasImmediateInput(instr, index)) {
__ mov_b(operand, i.InputInt8(index));
......@@ -570,7 +572,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ movzx_w(i.OutputRegister(), i.MemoryOperand());
break;
case kIA32Movw: {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
if (HasImmediateInput(instr, index)) {
__ mov_w(operand, i.InputInt16(index));
......@@ -583,7 +585,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (instr->HasOutput()) {
__ mov(i.OutputRegister(), i.MemoryOperand());
} else {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
if (HasImmediateInput(instr, index)) {
__ mov(operand, i.InputImmediate(index));
......@@ -596,7 +598,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (instr->HasOutput()) {
__ movsd(i.OutputDoubleRegister(), i.MemoryOperand());
} else {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
__ movsd(operand, i.InputDoubleRegister(index));
}
......@@ -605,7 +607,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (instr->HasOutput()) {
__ movss(i.OutputDoubleRegister(), i.MemoryOperand());
} else {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
__ movss(operand, i.InputDoubleRegister(index));
}
......
......@@ -462,7 +462,7 @@ void EmitLea(InstructionSelector* selector, Node* result, Node* index,
AddressingMode mode = g.GenerateMemoryOperandInputs(
index, scale, base, displacement, inputs, &input_count);
DCHECK_NE(0, static_cast<int>(input_count));
DCHECK_NE(0u, input_count);
DCHECK_GE(arraysize(inputs), input_count);
InstructionOperand outputs[1];
......@@ -515,7 +515,7 @@ void InstructionSelector::VisitInt32Add(Node* node) {
AddressingMode mode = g.GenerateMemoryOperandInputs(
m.index(), m.scale(), m.base(), m.displacement(), inputs, &input_count);
DCHECK_NE(0, static_cast<int>(input_count));
DCHECK_NE(0u, input_count);
DCHECK_GE(arraysize(inputs), input_count);
InstructionOperand outputs[1];
......
......@@ -398,7 +398,7 @@ void InstructionSelector::InitializeCallBuffer(Node* call, CallBuffer* buffer,
buffer->descriptor->GetInputType(0)));
break;
}
DCHECK_EQ(1, static_cast<int>(buffer->instruction_args.size()));
DCHECK_EQ(1u, buffer->instruction_args.size());
// If the call needs a frame state, we insert the state information as
// follows (n is the number of value inputs to the frame state):
......
......@@ -64,7 +64,6 @@ Scheduler::SchedulerData Scheduler::DefaultSchedulerData() {
Scheduler::SchedulerData* Scheduler::GetData(Node* node) {
DCHECK(node->id() < static_cast<int>(node_data_.size()));
return &node_data_[node->id()];
}
......@@ -1008,7 +1007,7 @@ class SpecialRPONumberer : public ZoneObject {
DCHECK(block->rpo_number() == links + header->rpo_number());
links++;
block = block->rpo_next();
DCHECK(links < static_cast<int>(2 * order->size())); // cycle?
DCHECK_LT(links, static_cast<int>(2 * order->size())); // cycle?
}
DCHECK(links > 0);
DCHECK(links == end->rpo_number() - header->rpo_number());
......
......@@ -24,11 +24,13 @@ class X64OperandConverter : public InstructionOperandConverter {
X64OperandConverter(CodeGenerator* gen, Instruction* instr)
: InstructionOperandConverter(gen, instr) {}
Immediate InputImmediate(int index) {
Immediate InputImmediate(size_t index) {
return ToImmediate(instr_->InputAt(index));
}
Operand InputOperand(int index) { return ToOperand(instr_->InputAt(index)); }
Operand InputOperand(size_t index) {
return ToOperand(instr_->InputAt(index));
}
Operand OutputOperand() { return ToOperand(instr_->Output()); }
......@@ -43,8 +45,8 @@ class X64OperandConverter : public InstructionOperandConverter {
return Operand(offset.from_stack_pointer() ? rsp : rbp, offset.offset());
}
static int NextOffset(int* offset) {
int i = *offset;
static size_t NextOffset(size_t* offset) {
size_t i = *offset;
(*offset)++;
return i;
}
......@@ -59,7 +61,7 @@ class X64OperandConverter : public InstructionOperandConverter {
return static_cast<ScaleFactor>(scale);
}
Operand MemoryOperand(int* offset) {
Operand MemoryOperand(size_t* offset) {
AddressingMode mode = AddressingModeField::decode(instr_->opcode());
switch (mode) {
case kMode_MR: {
......@@ -124,7 +126,7 @@ class X64OperandConverter : public InstructionOperandConverter {
return Operand(no_reg, 0);
}
Operand MemoryOperand(int first_input = 0) {
Operand MemoryOperand(size_t first_input = 0) {
return MemoryOperand(&first_input);
}
};
......@@ -132,7 +134,7 @@ class X64OperandConverter : public InstructionOperandConverter {
namespace {
bool HasImmediateInput(Instruction* instr, int index) {
bool HasImmediateInput(Instruction* instr, size_t index) {
return instr->InputAt(index)->IsImmediate();
}
......@@ -821,7 +823,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ AssertZeroExtended(i.OutputRegister());
break;
case kX64Movb: {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
if (HasImmediateInput(instr, index)) {
__ movb(operand, Immediate(i.InputInt8(index)));
......@@ -839,7 +841,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ AssertZeroExtended(i.OutputRegister());
break;
case kX64Movw: {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
if (HasImmediateInput(instr, index)) {
__ movw(operand, Immediate(i.InputInt16(index)));
......@@ -861,7 +863,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
}
__ AssertZeroExtended(i.OutputRegister());
} else {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
if (HasImmediateInput(instr, index)) {
__ movl(operand, i.InputImmediate(index));
......@@ -877,7 +879,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (instr->HasOutput()) {
__ movq(i.OutputRegister(), i.MemoryOperand());
} else {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
if (HasImmediateInput(instr, index)) {
__ movq(operand, i.InputImmediate(index));
......@@ -890,7 +892,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (instr->HasOutput()) {
__ movss(i.OutputDoubleRegister(), i.MemoryOperand());
} else {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
__ movss(operand, i.InputDoubleRegister(index));
}
......@@ -899,7 +901,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
if (instr->HasOutput()) {
__ movsd(i.OutputDoubleRegister(), i.MemoryOperand());
} else {
int index = 0;
size_t index = 0;
Operand operand = i.MemoryOperand(&index);
__ movsd(operand, i.InputDoubleRegister(index));
}
......@@ -1078,8 +1080,8 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
// Materialize a full 64-bit 1 or 0 value. The result register is always the
// last output of the instruction.
Label check;
DCHECK_NE(0, static_cast<int>(instr->OutputCount()));
Register reg = i.OutputRegister(static_cast<int>(instr->OutputCount() - 1));
DCHECK_NE(0u, instr->OutputCount());
Register reg = i.OutputRegister(instr->OutputCount() - 1);
Condition cc = no_condition;
switch (condition) {
case kUnorderedEqual:
......@@ -1140,8 +1142,8 @@ void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
X64OperandConverter i(this, instr);
Register input = i.InputRegister(0);
for (size_t index = 2; index < instr->InputCount(); index += 2) {
__ cmpl(input, Immediate(i.InputInt32(static_cast<int>(index + 0))));
__ j(equal, GetLabel(i.InputRpo(static_cast<int>(index + 1))));
__ cmpl(input, Immediate(i.InputInt32(index + 0)));
__ j(equal, GetLabel(i.InputRpo(index + 1)));
}
AssembleArchJump(i.InputRpo(1));
}
......
......@@ -346,8 +346,8 @@ static void VisitBinop(InstructionSelector* selector, Node* node,
outputs[output_count++] = g.DefineAsRegister(cont->result());
}
DCHECK_NE(0, static_cast<int>(input_count));
DCHECK_NE(0, static_cast<int>(output_count));
DCHECK_NE(0u, input_count);
DCHECK_NE(0u, output_count);
DCHECK_GE(arraysize(inputs), input_count);
DCHECK_GE(arraysize(outputs), output_count);
......@@ -471,7 +471,7 @@ void EmitLea(InstructionSelector* selector, InstructionCode opcode,
AddressingMode mode = g.GenerateMemoryOperandInputs(
index, scale, base, displacement, inputs, &input_count);
DCHECK_NE(0, static_cast<int>(input_count));
DCHECK_NE(0u, input_count);
DCHECK_GE(arraysize(inputs), input_count);
InstructionOperand outputs[1];
......
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