1. 11 Feb, 2016 1 commit
  2. 05 Feb, 2016 1 commit
  3. 28 Jan, 2016 1 commit
  4. 06 Jan, 2016 1 commit
    • ivica.bogosavljevic's avatar
      MIPS64: r6 compact branch optimization. · 2c63060f
      ivica.bogosavljevic authored
      Several ports to enable r6 compact branch optimizations on MIPS64
      
      Port 3573d3cb
      
      Original commit message:
      MIPS: r6 compact branch optimization.
      
      Port bddf8c9e
      
      Original commit message:
      MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort()
      
      Port 6993cd0d
      
      Original commit message:
      MIPS: Fix 'MIPS:r6 compact branch optimization.'
      
      Jic and jialc compact branch ops are fixed as they does
      not have 'forbidden slot' restriction. Also COP1 branches
      (CTI instructions) added to IsForbiddenAfterBranchInstr().
      
      Port bb332195
      
      Original commit message:
      MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort()
      
      Port c91bcf71
      
      Original commit message:
      MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort()
      for r6.
      
      BUG=
      
      Review URL: https://codereview.chromium.org/1534183002
      
      Cr-Commit-Position: refs/heads/master@{#33136}
      2c63060f
  5. 05 Jan, 2016 1 commit
  6. 02 Dec, 2015 1 commit
  7. 23 Nov, 2015 1 commit
  8. 30 Sep, 2015 1 commit
  9. 29 Sep, 2015 1 commit
  10. 18 Sep, 2015 1 commit
    • balazs.kilvady's avatar
      MIPS64: Optimize simulator. · b89eec39
      balazs.kilvady authored
      Port 09f41681
      
      Original commit message:
      The patch decreases the calls of huge switch instructions making the
      DecodeType*() functions to work in one phase and optimizing
      Instruction::InstructionType(). Speed gain in release full check is
      about 33% (6:13 s -> 4:09 s) and in optdebug full test is about 50%
      (12:29 -> 6:17)
      
      BUG=
      
      Review URL: https://codereview.chromium.org/1356693002
      
      Cr-Commit-Position: refs/heads/master@{#30824}
      b89eec39
  11. 24 Aug, 2015 1 commit
  12. 23 Jul, 2015 1 commit
  13. 15 Jun, 2015 1 commit
  14. 12 Jun, 2015 2 commits
  15. 22 May, 2015 1 commit
  16. 20 May, 2015 1 commit
    • svenpanne's avatar
      Fixed various simulator-related space leaks. · 84aa494e
      svenpanne authored
      Alas, this involved quite a bit of copy-n-paste between the
      architectures, but this is caused by the very convoluted
      relationships, lifetimes and distribution of responsibilities. This
      should really be cleaned up by moving code around and using STL maps,
      but that's not really a priority right now.
      
      Bonus: Fixed leaks in the ARM64 disassembler tests.
      
      Review URL: https://codereview.chromium.org/1132943007
      
      Cr-Commit-Position: refs/heads/master@{#28496}
      84aa494e
  17. 19 May, 2015 1 commit
  18. 14 May, 2015 2 commits
  19. 30 Apr, 2015 1 commit
  20. 06 Apr, 2015 1 commit
    • dusan.milosavljevic's avatar
      MIPS: Major fixes and clean-up in asm. for instruction encoding. · 4b5af7b3
      dusan.milosavljevic authored
      - Fixed single float register type instruction en[de]coding in assembler and disassembler.
      - Added max and min instructions for r6 and corresponding tests.
      - Fixed selection instruction for boundary cases in simulator.
      - Update assembler tests to be more thorough wrt boundary cases.
      
      TEST=cctest/test-assembler-mips64/MIPS17, MIPS18
           cctest/test-disasm-mips64/Type1
           cctest/test-assembler-mips/MIPS16, MIPS17
           cctest/test-disasm-mips/Type1
      BUG=
      
      Review URL: https://codereview.chromium.org/1057323002
      
      Cr-Commit-Position: refs/heads/master@{#27601}
      4b5af7b3
  21. 31 Mar, 2015 1 commit
    • akos.palfi's avatar
      MIPS64: [turbofan] Add backend support for float32 operations. · df40d51e
      akos.palfi authored
      Port 8dad78cd
      
      Original commit message:
      This adds the basics necessary to support float32 operations in TurboFan.
      The actual functionality required to detect safe float32 operations will
      be added based on this later. Therefore this does not affect production
      code except for some cleanup/refactoring.
      
      In detail, this patchset contains the following features:
      - Add support for float32 operations to arm, arm64, ia32 and x64
        backends.
      - Add float32 machine operators.
      - Add support for float32 constants to simplified lowering.
      - Handle float32 representation for phis in simplified lowering.
      
      In addition, contains the following (related) cleanups:
      - Fix/unify naming of backend instructions.
      - Use AVX comparisons when available.
      - Extend ArchOpcodeField to 9 bits (required for arm64).
      - Refactor some code duplication in instruction selectors.
      
      BUG=
      
      Review URL: https://codereview.chromium.org/1045203003
      
      Cr-Commit-Position: refs/heads/master@{#27534}
      df40d51e
  22. 30 Mar, 2015 1 commit
  23. 31 Oct, 2014 1 commit
  24. 17 Sep, 2014 1 commit
  25. 09 Jul, 2014 1 commit
  26. 20 Jun, 2014 1 commit
  27. 03 Jun, 2014 2 commits
  28. 20 May, 2014 1 commit
  29. 29 Apr, 2014 1 commit
  30. 12 Feb, 2014 1 commit
  31. 22 Nov, 2013 1 commit
  32. 19 Jun, 2013 1 commit
  33. 12 Apr, 2013 1 commit
    • plind44@gmail.com's avatar
      MIPS: Accurate function prototypes for native calls from ARM simulator. · dcd3f06b
      plind44@gmail.com authored
      Port r14230 (76c22097)
      
      Original commit message:
      Native method invocation from the arm/simulator-arm.cc previously made
      non-portable assumptions about calling conventions. This was okay for 32-bit
      stack-based machines, where by-value structs are automatically materialized
      on the stack, and where both int and double parameters could be passed on the
      stack. However they are not okay for x86-64, which has an elaborate scheme
      for passing parameters in registers.
      
      This CL replaces the previous non-portable code paths with portable code,
      using call-sites that accurately match the prototype of the callee.
      
      BUG=
      
      Review URL: https://codereview.chromium.org/13989008
      Patch from Akos Palfi <palfia@homejinni.com>.
      
      git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14239 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      dcd3f06b
  34. 02 Apr, 2013 1 commit
  35. 29 Nov, 2012 1 commit
  36. 24 May, 2012 1 commit
  37. 21 Mar, 2012 1 commit
    • danno@chromium.org's avatar
      MIPS: Branch delay slot and other optimizations. · b49dd13c
      danno@chromium.org authored
      List of changes:
      -added a minor optimization to the Simulator that quickly skips nops in the delay slot
      -slightly re-worked CEntryStub to save a few instructions
       CEntryStub now expects the following values:
        -s0: number of arguments including receiver
        -s1: size of arguments excluding receiver
        -s2: pointer to builtin function
       Two new MacroAssembler functions were added to make usage more convenient:
        -PrepareCEntryArgs(int num_args) to set up s0 and s1
        -PrepareCEntryFunction(const ExternalReference&) to set up s2
      -removed branch delay slot nops from the most frequently used code areas
      -reorganized some code to execute fewer instructions
      -utilized the delay slot of most Ret instructions
       This does not cover all Rets, only the most obvious cases.
       Also added a special version of DropAndRet that utilizes the delay slot.
      -added some comments to code areas where explanation of the register/delay slot usage may be needed
      -added an optimization to Jump so it doesn't always pre-load the target register
      
      BUG=
      TEST=
      
      Review URL: https://chromiumcodereview.appspot.com/9699071
      Patch from Daniel Kalmar <kalmard@homejinni.com>.
      
      git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@11099 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      b49dd13c