- 11 Feb, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1691763002 Cr-Commit-Position: refs/heads/master@{#33913}
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- 05 Feb, 2016 1 commit
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balazs.kilvady authored
BUG= TEST=cctest/test-assembler-mips/min_max, cctest/test-assembler-mips/mina_maxa, cctest/test-assembler-mips64/min_max, cctest/test-assembler-mips64/mina_maxa Review URL: https://codereview.chromium.org/1668143002 Cr-Commit-Position: refs/heads/master@{#33790}
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- 28 Jan, 2016 1 commit
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Ilija.Pavlovic authored
Compilation dependencies for O32 ABI are removed from the code and now compilation will be done according n64 ABI only. TEST= BUG= Review URL: https://codereview.chromium.org/1638303005 Cr-Commit-Position: refs/heads/master@{#33589}
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- 06 Jan, 2016 1 commit
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ivica.bogosavljevic authored
Several ports to enable r6 compact branch optimizations on MIPS64 Port 3573d3cb Original commit message: MIPS: r6 compact branch optimization. Port bddf8c9e Original commit message: MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort() Port 6993cd0d Original commit message: MIPS: Fix 'MIPS:r6 compact branch optimization.' Jic and jialc compact branch ops are fixed as they does not have 'forbidden slot' restriction. Also COP1 branches (CTI instructions) added to IsForbiddenAfterBranchInstr(). Port bb332195 Original commit message: MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort() Port c91bcf71 Original commit message: MIPS: Fix trampoline pool handling in MacroAssembler::BranchShort() for r6. BUG= Review URL: https://codereview.chromium.org/1534183002 Cr-Commit-Position: refs/heads/master@{#33136}
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- 05 Jan, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1545013002 Cr-Commit-Position: refs/heads/master@{#33127}
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- 02 Dec, 2015 1 commit
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ivica.bogosavljevic authored
MIPS R6 introduced new behavior for handling of NaN values for TRUNC, FLOOR, CEIL and CVT instructions. Adding support for the new behavior in MIPS and MIPS64 simulators. Fixing tests for MIPS and MIPS64 to align them with the new behavior. BUG= Review URL: https://codereview.chromium.org/1488613007 Cr-Commit-Position: refs/heads/master@{#32499}
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- 23 Nov, 2015 1 commit
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jochen authored
BUG=2487 R=ulan@chromium.org LOG=n Review URL: https://codereview.chromium.org/1457223005 Cr-Commit-Position: refs/heads/master@{#32164}
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- 30 Sep, 2015 1 commit
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mstarzinger authored
This enables linter checking for "readability/namespace" violations during presubmit and instead marks the few known exceptions that we allow explicitly. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1371083003 Cr-Commit-Position: refs/heads/master@{#31019}
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- 29 Sep, 2015 1 commit
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dusan.m.milosavljevic authored
TEST= BUG= Review URL: https://codereview.chromium.org/1334793004 Cr-Commit-Position: refs/heads/master@{#31011}
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- 18 Sep, 2015 1 commit
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balazs.kilvady authored
Port 09f41681 Original commit message: The patch decreases the calls of huge switch instructions making the DecodeType*() functions to work in one phase and optimizing Instruction::InstructionType(). Speed gain in release full check is about 33% (6:13 s -> 4:09 s) and in optdebug full test is about 50% (12:29 -> 6:17) BUG= Review URL: https://codereview.chromium.org/1356693002 Cr-Commit-Position: refs/heads/master@{#30824}
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- 24 Aug, 2015 1 commit
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mstarzinger authored
The simulator uses a separate JS stack, exhaustion of the C stack however is not caught by JS limit checks. This change now lowers the limit of the JS stack accordingly on function calls. R=mvstanton@chromium.org BUG=chromium:522380 TEST=mjsunit/regress/regress-crbug-522380 LOG=n Review URL: https://codereview.chromium.org/1314623002 Cr-Commit-Position: refs/heads/master@{#30334}
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- 23 Jul, 2015 1 commit
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Ilija.Pavlovic authored
In simulator data trace, DSLL did not print result and BAL/BGEZAL omitted result from an instruction executed in delay slot. TEST=cctest/test-assembler-mips[64] BUG= Review URL: https://codereview.chromium.org/1245173002 Cr-Commit-Position: refs/heads/master@{#29796}
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- 15 Jun, 2015 1 commit
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balazs.kilvady authored
Port cdc43bc5 Original review: https://codereview.chromium.org/1133163005/ Original commit message: Enable clang's shorten-64-to-32 warning flag on ARM64, and fix the warnings that arise. BUG= Review URL: https://codereview.chromium.org/1182193004 Cr-Commit-Position: refs/heads/master@{#29024}
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- 12 Jun, 2015 2 commits
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yangguo authored
Revert of MIPS64: Enable shorten-64-to-32 warning. (patchset #12 id:240001 of https://codereview.chromium.org/1133163005/) Reason for revert: Compile failure: https://chromegw.corp.google.com/i/client.v8/builders/V8%20Mac64%20-%20debug/builds/3070/steps/compile/logs/stdio Original issue's description: > MIPS64: Enable shorten-64-to-32 warning. > > Port cdc43bc5 > > Original commit message: > Enable clang's shorten-64-to-32 warning flag on ARM64, and fix the warnings > that arise. > > BUG= > > Committed: https://crrev.com/9af578a7c83b58a0ce25345998d9287cbf2030cb > Cr-Commit-Position: refs/heads/master@{#28990} TBR=danno@chromium.org,martyn.capewell@arm.com,paul.lind@imgtec.com,akos.palfi@imgtec.com,dusan.milosavljevic@imgtec.com,jkummerow@chromium.org,machenbach@chromium.org,svenpanne@chromium.org,balazs.kilvady@imgtec.com NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review URL: https://codereview.chromium.org/1182493007 Cr-Commit-Position: refs/heads/master@{#28991}
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balazs.kilvady authored
Port cdc43bc5 Original commit message: Enable clang's shorten-64-to-32 warning flag on ARM64, and fix the warnings that arise. BUG= Review URL: https://codereview.chromium.org/1133163005 Cr-Commit-Position: refs/heads/master@{#28990}
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- 22 May, 2015 1 commit
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1145223002 Cr-Commit-Position: refs/heads/master@{#28595}
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- 20 May, 2015 1 commit
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svenpanne authored
Alas, this involved quite a bit of copy-n-paste between the architectures, but this is caused by the very convoluted relationships, lifetimes and distribution of responsibilities. This should really be cleaned up by moving code around and using STL maps, but that's not really a priority right now. Bonus: Fixed leaks in the ARM64 disassembler tests. Review URL: https://codereview.chromium.org/1132943007 Cr-Commit-Position: refs/heads/master@{#28496}
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- 19 May, 2015 1 commit
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1147493002 Cr-Commit-Position: refs/heads/master@{#28472}
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- 14 May, 2015 2 commits
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paul.lind authored
Reason for revert: Simulator test failures in RunChangeFloat64ToInt.., RunChangeTaggedToInt32, div-mul-minus-one Original issue's description: > Implement assembler, disassembler tests for all instructions for mips32 > and mips64. Additionally, add missing single precision float instructions > for r2 and r6 architecture variants in assembler, simulator and disassembler > with corresponding tests. BUG= Review URL: https://codereview.chromium.org/1143473003 Cr-Commit-Position: refs/heads/master@{#28404}
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1119203003 Cr-Commit-Position: refs/heads/master@{#28402}
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- 30 Apr, 2015 1 commit
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Djordje.Pesic authored
Added rounding according to fcsr, CVT_W_D and RINT.D instruction in assembler, dissasembler and simulator and wrote appropiate tests. BUG= Review URL: https://codereview.chromium.org/1108583003 Cr-Commit-Position: refs/heads/master@{#28143}
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- 06 Apr, 2015 1 commit
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dusan.milosavljevic authored
- Fixed single float register type instruction en[de]coding in assembler and disassembler. - Added max and min instructions for r6 and corresponding tests. - Fixed selection instruction for boundary cases in simulator. - Update assembler tests to be more thorough wrt boundary cases. TEST=cctest/test-assembler-mips64/MIPS17, MIPS18 cctest/test-disasm-mips64/Type1 cctest/test-assembler-mips/MIPS16, MIPS17 cctest/test-disasm-mips/Type1 BUG= Review URL: https://codereview.chromium.org/1057323002 Cr-Commit-Position: refs/heads/master@{#27601}
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- 31 Mar, 2015 1 commit
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akos.palfi authored
Port 8dad78cd Original commit message: This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG= Review URL: https://codereview.chromium.org/1045203003 Cr-Commit-Position: refs/heads/master@{#27534}
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- 30 Mar, 2015 1 commit
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dusan.milosavljevic authored
TEST= BUG= Review URL: https://codereview.chromium.org/1046873004 Cr-Commit-Position: refs/heads/master@{#27530}
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- 31 Oct, 2014 1 commit
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dusan.milosavljevic@imgtec.com authored
Removed workaround for this issue. TEST=mjsunit, cctest on sim64 BUG= R=paul.lind@imgtec.com Review URL: https://codereview.chromium.org/695933002 Cr-Commit-Position: refs/heads/master@{#25043} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25043 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 17 Sep, 2014 1 commit
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dusan.milosavljevic@imgtec.com authored
This resolves calculation errors for trigonometric functions. TEST=test262/S15.8.2.7_A6.js BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/558163006 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24013 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 09 Jul, 2014 1 commit
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dusan.milosavljevic@rt-rk.com authored
Summary: - Changes in common code are mainly boilerplate changes, gyp and test status files updates. - On mips64 simulator all tests pass from all test units. - Current issues: mjsunit JS debugger tests fail randomly on HW in release mode. Corresponding tests are skipped on HW. - Skipped tests on mips64: test-heap/ReleaseOverReservedPages, mjsunit/debug-* TEST= BUG= R=danno@chromium.org, plind44@gmail.com, ulan@chromium.org Review URL: https://codereview.chromium.org/371923006 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22297 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 20 Jun, 2014 1 commit
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mstarzinger@chromium.org authored
R=rossberg@chromium.org Review URL: https://codereview.chromium.org/333013002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21894 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 03 Jun, 2014 2 commits
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ishell@chromium.org authored
Fixed lint errors caused by "runtime/references" rule (Is this a non-const reference?) and the rule itself is restored. BUG=v8:3326 LOG=N R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/314723002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21651 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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jochen@chromium.org authored
- this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 20 May, 2014 1 commit
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ishell@chromium.org authored
BUG=chromium:369962 LOG=N R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/282783004 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21382 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 29 Apr, 2014 1 commit
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bmeurer@chromium.org authored
R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/259183002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 12 Feb, 2014 1 commit
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ulan@chromium.org authored
BUG=v8:3113 LOG=Y R=jochen@chromium.org, rmcilroy@chromium.org, rodolph.perfetta@arm.com Review URL: https://codereview.chromium.org/148293020 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19311 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 22 Nov, 2013 1 commit
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palfia@homejinni.com authored
This commit fixes a lot of test failures that we saw earlier in the buildbots (http://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20mips%20-%20sim/builds/3034/steps/Check/logs/stdio). In some very rare cases the code age stub address can be 0xXXXX0000 and in this case the li maco instruction emits only 1 instruction (instead of the expected 2). Thus the code age sequence will be 6 instructions long instead of 7, which breaks the code aging feature. This change makes sure that li always emits 2 instructions and it also simplifies the code aging sequence. Also fixes a small mistake in the simulator at the jalr instruction. BUG= R=gergely@homejinni.com Review URL: https://codereview.chromium.org/83583003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18030 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 19 Jun, 2013 1 commit
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plind44@gmail.com authored
BUG=v8:2628 TEST=cctest/test-cpu-profiler/SampleWhenFrameIsNotSetup R=jkummerow@chromium.org, yurys@chromium.org Review URL: https://codereview.chromium.org/17265004 Patch from Dusan Milosavljevic <Dusan.Milosavljevic@rt-rk.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15213 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 12 Apr, 2013 1 commit
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plind44@gmail.com authored
Port r14230 (76c22097) Original commit message: Native method invocation from the arm/simulator-arm.cc previously made non-portable assumptions about calling conventions. This was okay for 32-bit stack-based machines, where by-value structs are automatically materialized on the stack, and where both int and double parameters could be passed on the stack. However they are not okay for x86-64, which has an elaborate scheme for passing parameters in registers. This CL replaces the previous non-portable code paths with portable code, using call-sites that accurately match the prototype of the callee. BUG= Review URL: https://codereview.chromium.org/13989008 Patch from Akos Palfi <palfia@homejinni.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14239 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 02 Apr, 2013 1 commit
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ulan@chromium.org authored
BUG=none Review URL: https://chromiumcodereview.appspot.com/13469002 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14113 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 29 Nov, 2012 1 commit
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jkummerow@chromium.org authored
Port r13054 (636985d7) BUG= TEST= Review URL: https://codereview.chromium.org/11415192 Patch from Akos Palfi <palfia@homejinni.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13089 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 24 May, 2012 1 commit
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yangguo@chromium.org authored
Port r11623 (f153116d) BUG= TEST= Review URL: https://chromiumcodereview.appspot.com/10436012 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@11639 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 21 Mar, 2012 1 commit
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danno@chromium.org authored
List of changes: -added a minor optimization to the Simulator that quickly skips nops in the delay slot -slightly re-worked CEntryStub to save a few instructions CEntryStub now expects the following values: -s0: number of arguments including receiver -s1: size of arguments excluding receiver -s2: pointer to builtin function Two new MacroAssembler functions were added to make usage more convenient: -PrepareCEntryArgs(int num_args) to set up s0 and s1 -PrepareCEntryFunction(const ExternalReference&) to set up s2 -removed branch delay slot nops from the most frequently used code areas -reorganized some code to execute fewer instructions -utilized the delay slot of most Ret instructions This does not cover all Rets, only the most obvious cases. Also added a special version of DropAndRet that utilizes the delay slot. -added some comments to code areas where explanation of the register/delay slot usage may be needed -added an optimization to Jump so it doesn't always pre-load the target register BUG= TEST= Review URL: https://chromiumcodereview.appspot.com/9699071 Patch from Daniel Kalmar <kalmard@homejinni.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@11099 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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