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Commit a58c750c authored by balazs.kilvady's avatar balazs.kilvady Committed by Commit bot
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MIPS: Fix FPU min, max, mina, maxa in simulator. 

BUG=
TEST=cctest/test-assembler-mips/min_max, cctest/test-assembler-mips/mina_maxa, cctest/test-assembler-mips64/min_max, cctest/test-assembler-mips64/mina_maxa

Review URL: https://codereview.chromium.org/1668143002

Cr-Commit-Position: refs/heads/master@{#33790}
parent 3dc2635d
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Showing with 335 additions and 322 deletions
src/mips/simulator-mips.cc
View file @ a58c750c
......@@ -2347,6 +2347,89 @@ void Simulator::SignalException(Exception e) {
static_cast<int>(e));
}
template <typename T>
T FPAbs(T a);
template <>
double FPAbs<double>(double a) {
return fabs(a);
}
template <>
float FPAbs<float>(float a) {
return fabsf(a);
}
template <typename T>
bool Simulator::FPUProcessNaNsAndZeros(T a, T b, IsMin min, T& result) {
if (std::isnan(a) && std::isnan(b)) {
result = a;
} else if (std::isnan(a)) {
result = b;
} else if (std::isnan(b)) {
result = a;
} else if (b == a) {
// Handle -0.0 == 0.0 case.
// std::signbit() returns int 0 or 1 so substracting IsMin::kMax negates the
// result.
result = std::signbit(b) - static_cast<int>(min) ? b : a;
} else {
return false;
}
return true;
}
template <typename T>
T Simulator::FPUMin(T a, T b) {
T result;
if (FPUProcessNaNsAndZeros(a, b, IsMin::kMin, result)) {
return result;
} else {
return b < a ? b : a;
}
}
template <typename T>
T Simulator::FPUMax(T a, T b) {
T result;
if (FPUProcessNaNsAndZeros(a, b, IsMin::kMax, result)) {
return result;
} else {
return b > a ? b : a;
}
}
template <typename T>
T Simulator::FPUMinA(T a, T b) {
T result;
if (!FPUProcessNaNsAndZeros(a, b, IsMin::kMin, result)) {
if (FPAbs(a) < FPAbs(b)) {
result = a;
} else if (FPAbs(b) < FPAbs(a)) {
result = b;
} else {
result = a < b ? a : b;
}
}
return result;
}
template <typename T>
T Simulator::FPUMaxA(T a, T b) {
T result;
if (!FPUProcessNaNsAndZeros(a, b, IsMin::kMin, result)) {
if (FPAbs(a) > FPAbs(b)) {
result = a;
} else if (FPAbs(b) > FPAbs(a)) {
result = b;
} else {
result = a > b ? a : b;
}
}
return result;
}
// Handle execution based on instruction types.
void Simulator::DecodeTypeRegisterDRsType() {
double ft, fs, fd;
......@@ -2442,72 +2525,19 @@ void Simulator::DecodeTypeRegisterDRsType() {
}
case MIN:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
set_fpu_register_double(fd_reg(), (fs >= ft) ? ft : fs);
}
set_fpu_register_double(fd_reg(), FPUMin(ft, fs));
break;
case MINA:
case MAX:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
double result;
if (fabs(fs) > fabs(ft)) {
result = ft;
} else if (fabs(fs) < fabs(ft)) {
result = fs;
} else {
result = (fs < ft ? fs : ft);
}
set_fpu_register_double(fd_reg(), result);
}
set_fpu_register_double(fd_reg(), FPUMax(ft, fs));
break;
case MAXA:
case MINA:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
double result;
if (fabs(fs) < fabs(ft)) {
result = ft;
} else if (fabs(fs) > fabs(ft)) {
result = fs;
} else {
result = (fs > ft ? fs : ft);
}
set_fpu_register_double(fd_reg(), result);
}
set_fpu_register_double(fd_reg(), FPUMinA(ft, fs));
break;
case MAX:
case MAXA:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
set_fpu_register_double(fd_reg(), (fs <= ft) ? ft : fs);
}
break;
set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs));
break;
case ADD_D:
set_fpu_register_double(fd_reg(), fs + ft);
......@@ -3193,71 +3223,19 @@ void Simulator::DecodeTypeRegisterSRsType() {
}
case MIN:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
set_fpu_register_float(fd_reg(), (fs >= ft) ? ft : fs);
}
set_fpu_register_float(fd_reg(), FPUMin(ft, fs));
break;
case MAX:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
set_fpu_register_float(fd_reg(), (fs <= ft) ? ft : fs);
}
set_fpu_register_float(fd_reg(), FPUMax(ft, fs));
break;
case MINA:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
float result;
if (fabs(fs) > fabs(ft)) {
result = ft;
} else if (fabs(fs) < fabs(ft)) {
result = fs;
} else {
result = (fs < ft ? fs : ft);
}
set_fpu_register_float(fd_reg(), result);
}
set_fpu_register_float(fd_reg(), FPUMinA(ft, fs));
break;
case MAXA:
DCHECK(IsMipsArchVariant(kMips32r6));
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
float result;
if (fabs(fs) < fabs(ft)) {
result = ft;
} else if (fabs(fs) > fabs(ft)) {
result = fs;
} else {
result = (fs > ft ? fs : ft);
}
set_fpu_register_float(fd_reg(), result);
}
set_fpu_register_float(fd_reg(), FPUMaxA(ft, fs));
break;
case CVT_L_S: {
if (IsFp64Mode()) {
......
src/mips/simulator-mips.h
View file @ a58c750c
......@@ -300,6 +300,24 @@ class Simulator {
inline int32_t SetDoubleHIW(double* addr);
inline int32_t SetDoubleLOW(double* addr);
// Min/Max template functions for Double and Single arguments.
enum class IsMin : int { kMin = 0, kMax = 1 };
template <typename T>
bool FPUProcessNaNsAndZeros(T a, T b, IsMin min, T& result);
template <typename T>
T FPUMin(T a, T b);
template <typename T>
T FPUMax(T a, T b);
template <typename T>
T FPUMinA(T a, T b);
template <typename T>
T FPUMaxA(T a, T b);
// Executing is handled based on the instruction type.
void DecodeTypeRegister(Instruction* instr);
......
src/mips64/simulator-mips64.cc
View file @ a58c750c
......@@ -2332,6 +2332,87 @@ void Simulator::SignalException(Exception e) {
static_cast<int>(e));
}
template <typename T>
T FPAbs(T a);
template <>
double FPAbs<double>(double a) {
return fabs(a);
}
template <>
float FPAbs<float>(float a) {
return fabsf(a);
}
template <typename T>
bool Simulator::FPUProcessNaNsAndZeros(T a, T b, IsMin min, T& result) {
if (std::isnan(a) && std::isnan(b)) {
result = a;
} else if (std::isnan(a)) {
result = b;
} else if (std::isnan(b)) {
result = a;
} else if (b == a) {
// Handle -0.0 == 0.0 case.
// std::signbit() returns int 0 or 1 so substracting IsMin::kMax negates the
// result.
result = std::signbit(b) - static_cast<int>(min) ? b : a;
} else {
return false;
}
return true;
}
template <typename T>
T Simulator::FPUMin(T a, T b) {
T result;
if (FPUProcessNaNsAndZeros(a, b, IsMin::kMin, result)) {
return result;
} else {
return b < a ? b : a;
}
}
template <typename T>
T Simulator::FPUMax(T a, T b) {
T result;
if (FPUProcessNaNsAndZeros(a, b, IsMin::kMax, result)) {
return result;
} else {
return b > a ? b : a;
}
}
template <typename T>
T Simulator::FPUMinA(T a, T b) {
T result;
if (!FPUProcessNaNsAndZeros(a, b, IsMin::kMin, result)) {
if (FPAbs(a) < FPAbs(b)) {
result = a;
} else if (FPAbs(b) < FPAbs(a)) {
result = b;
} else {
result = a < b ? a : b;
}
}
return result;
}
template <typename T>
T Simulator::FPUMaxA(T a, T b) {
T result;
if (!FPUProcessNaNsAndZeros(a, b, IsMin::kMin, result)) {
if (FPAbs(a) > FPAbs(b)) {
result = a;
} else if (FPAbs(b) > FPAbs(a)) {
result = b;
} else {
result = a > b ? a : b;
}
}
return result;
}
// Handle execution based on instruction types.
......@@ -2616,71 +2697,19 @@ void Simulator::DecodeTypeRegisterSRsType() {
}
case MINA:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
float result;
if (fabs(fs) > fabs(ft)) {
result = ft;
} else if (fabs(fs) < fabs(ft)) {
result = fs;
} else {
result = (fs < ft ? fs : ft);
}
set_fpu_register_float(fd_reg(), result);
}
set_fpu_register_float(fd_reg(), FPUMinA(ft, fs));
break;
case MAXA:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
float result;
if (fabs(fs) < fabs(ft)) {
result = ft;
} else if (fabs(fs) > fabs(ft)) {
result = fs;
} else {
result = (fs > ft ? fs : ft);
}
set_fpu_register_float(fd_reg(), result);
}
set_fpu_register_float(fd_reg(), FPUMaxA(ft, fs));
break;
case MIN:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
set_fpu_register_float(fd_reg(), (fs >= ft) ? ft : fs);
}
set_fpu_register_float(fd_reg(), FPUMin(ft, fs));
break;
case MAX:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_float(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_float(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_float(fd_reg(), fs);
} else {
set_fpu_register_float(fd_reg(), (fs <= ft) ? ft : fs);
}
set_fpu_register_float(fd_reg(), FPUMax(ft, fs));
break;
case SEL:
DCHECK(kArchVariant == kMips64r6);
......@@ -2825,71 +2854,19 @@ void Simulator::DecodeTypeRegisterDRsType() {
}
case MINA:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
double result;
if (fabs(fs) > fabs(ft)) {
result = ft;
} else if (fabs(fs) < fabs(ft)) {
result = fs;
} else {
result = (fs < ft ? fs : ft);
}
set_fpu_register_double(fd_reg(), result);
}
set_fpu_register_double(fd_reg(), FPUMinA(ft, fs));
break;
case MAXA:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
double result;
if (fabs(fs) < fabs(ft)) {
result = ft;
} else if (fabs(fs) > fabs(ft)) {
result = fs;
} else {
result = (fs > ft ? fs : ft);
}
set_fpu_register_double(fd_reg(), result);
}
set_fpu_register_double(fd_reg(), FPUMaxA(ft, fs));
break;
case MIN:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
set_fpu_register_double(fd_reg(), (fs >= ft) ? ft : fs);
}
set_fpu_register_double(fd_reg(), FPUMin(ft, fs));
break;
case MAX:
DCHECK(kArchVariant == kMips64r6);
fs = get_fpu_register_double(fs_reg());
if (std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else if (std::isnan(fs) && !std::isnan(ft)) {
set_fpu_register_double(fd_reg(), ft);
} else if (!std::isnan(fs) && std::isnan(ft)) {
set_fpu_register_double(fd_reg(), fs);
} else {
set_fpu_register_double(fd_reg(), (fs <= ft) ? ft : fs);
}
set_fpu_register_double(fd_reg(), FPUMax(ft, fs));
break;
case ADD_D:
set_fpu_register_double(fd_reg(), fs + ft);
......
src/mips64/simulator-mips64.h
View file @ a58c750c
......@@ -315,6 +315,24 @@ class Simulator {
inline int32_t SetDoubleHIW(double* addr);
inline int32_t SetDoubleLOW(double* addr);
// Min/Max template functions for Double and Single arguments.
enum class IsMin : int { kMin = 0, kMax = 1 };
template <typename T>
bool FPUProcessNaNsAndZeros(T a, T b, IsMin min, T& result);
template <typename T>
T FPUMin(T a, T b);
template <typename T>
T FPUMax(T a, T b);
template <typename T>
T FPUMinA(T a, T b);
template <typename T>
T FPUMaxA(T a, T b);
// functions called from DecodeTypeRegister.
void DecodeTypeRegisterCOP1();
......
test/cctest/test-assembler-mips.cc
View file @ a58c750c
......@@ -1456,10 +1456,10 @@ TEST(min_max) {
CcTest::InitializeVM();
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
MacroAssembler assm(isolate, NULL, 0,
MacroAssembler assm(isolate, nullptr, 0,
v8::internal::CodeObjectRequired::kYes);
typedef struct test_float {
struct TestFloat {
double a;
double b;
double c;
......@@ -1468,21 +1468,35 @@ TEST(min_max) {
float f;
float g;
float h;
} TestFloat;
};
TestFloat test;
const double double_nan = std::numeric_limits<double>::quiet_NaN();
const float float_nan = std::numeric_limits<float>::quiet_NaN();
const int kTableLength = 5;
double inputsa[kTableLength] = {2.0, 3.0, double_nan, 3.0, double_nan};
double inputsb[kTableLength] = {3.0, 2.0, 3.0, double_nan, double_nan};
double outputsdmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, double_nan};
double outputsdmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, double_nan};
float inputse[kTableLength] = {2.0, 3.0, float_nan, 3.0, float_nan};
float inputsf[kTableLength] = {3.0, 2.0, 3.0, float_nan, float_nan};
float outputsfmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, float_nan};
float outputsfmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, float_nan};
const double dnan = std::numeric_limits<double>::quiet_NaN();
const double dinf = std::numeric_limits<double>::infinity();
const double dminf = -std::numeric_limits<double>::infinity();
const float fnan = std::numeric_limits<float>::quiet_NaN();
const float finf = std::numeric_limits<float>::infinity();
const float fminf = std::numeric_limits<float>::infinity();
const int kTableLength = 13;
double inputsa[kTableLength] = {2.0, 3.0, dnan, 3.0, -0.0, 0.0, dinf,
dnan, 42.0, dinf, dminf, dinf, dnan};
double inputsb[kTableLength] = {3.0, 2.0, 3.0, dnan, 0.0, -0.0, dnan,
dinf, dinf, 42.0, dinf, dminf, dnan};
double outputsdmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, -0.0,
-0.0, dinf, dinf, 42.0, 42.0,
dminf, dminf, dnan};
double outputsdmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, 0.0, 0.0, dinf,
dinf, dinf, dinf, dinf, dinf, dnan};
float inputse[kTableLength] = {2.0, 3.0, fnan, 3.0, -0.0, 0.0, finf,
fnan, 42.0, finf, fminf, finf, fnan};
float inputsf[kTableLength] = {3.0, 2.0, 3.0, fnan, -0.0, 0.0, fnan,
finf, finf, 42.0, finf, fminf, fnan};
float outputsfmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, -0.0,
-0.0, finf, finf, 42.0, 42.0,
fminf, fminf, fnan};
float outputsfmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, 0.0, 0.0, finf,
finf, finf, finf, finf, finf, fnan};
__ ldc1(f4, MemOperand(a0, offsetof(TestFloat, a)));
__ ldc1(f8, MemOperand(a0, offsetof(TestFloat, b)));
......@@ -1863,16 +1877,20 @@ TEST(Cvt_d_uw) {
TEST(mina_maxa) {
if (IsMipsArchVariant(kMips32r6)) {
const int kTableLength = 15;
const int kTableLength = 23;
CcTest::InitializeVM();
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
MacroAssembler assm(isolate, NULL, 0,
MacroAssembler assm(isolate, nullptr, 0,
v8::internal::CodeObjectRequired::kYes);
const double double_nan = std::numeric_limits<double>::quiet_NaN();
const float float_nan = std::numeric_limits<float>::quiet_NaN();
typedef struct test_float {
const double dnan = std::numeric_limits<double>::quiet_NaN();
const double dinf = std::numeric_limits<double>::infinity();
const double dminf = -std::numeric_limits<double>::infinity();
const float fnan = std::numeric_limits<float>::quiet_NaN();
const float finf = std::numeric_limits<float>::infinity();
const float fminf = std::numeric_limits<float>::infinity();
struct TestFloat {
double a;
double b;
double resd;
......@@ -1881,41 +1899,34 @@ TEST(mina_maxa) {
float d;
float resf;
float resf1;
}TestFloat;
};
TestFloat test;
double inputsa[kTableLength] = {
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9,
-9.8, -10.0, -8.9, -9.8, double_nan, 3.0, double_nan
};
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9, -9.8, -10.0, -8.9, -9.8,
dnan, 3.0, -0.0, 0.0, dinf, dnan, 42.0, dinf, dminf, dinf, dnan};
double inputsb[kTableLength] = {
4.8, 5.3, 6.1, -10.0, -8.9, -9.8, 9.8, 9.8,
9.8, -9.8, -11.2, -9.8, 3.0, double_nan, double_nan
};
4.8, 5.3, 6.1, -10.0, -8.9, -9.8, 9.8, 9.8, 9.8, -9.8, -11.2, -9.8,
3.0, dnan, 0.0, -0.0, dnan, dinf, dinf, 42.0, dinf, dminf, dnan};
double resd[kTableLength] = {
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9,
-9.8, -9.8, -8.9, -9.8, 3.0, 3.0, double_nan
};
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9, -9.8, -9.8, -8.9, -9.8,
3.0, 3.0, -0.0, -0.0, dinf, dinf, 42.0, 42.0, dminf, dminf, dnan};
double resd1[kTableLength] = {
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8,
9.8, -10.0, -11.2, -9.8, 3.0, 3.0, double_nan
};
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8, 9.8, -10.0, -11.2, -9.8,
3.0, 3.0, 0.0, 0.0, dinf, dinf, dinf, dinf, dinf, dinf, dnan};
float inputsc[kTableLength] = {
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9,
-9.8, -10.0, -8.9, -9.8, float_nan, 3.0, float_nan
};
float inputsd[kTableLength] = {
4.8, 5.3, 6.1, -10.0, -8.9, -9.8, 9.8, 9.8,
9.8, -9.8, -11.2, -9.8, 3.0, float_nan, float_nan
};
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9, -9.8, -10.0, -8.9, -9.8,
fnan, 3.0, -0.0, 0.0, finf, fnan, 42.0, finf, fminf, finf, fnan};
float inputsd[kTableLength] = {4.8, 5.3, 6.1, -10.0, -8.9, -9.8,
9.8, 9.8, 9.8, -9.8, -11.2, -9.8,
3.0, fnan, -0.0, 0.0, fnan, finf,
finf, 42.0, finf, fminf, fnan};
float resf[kTableLength] = {
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9,
-9.8, -9.8, -8.9, -9.8, 3.0, 3.0, float_nan
};
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9, -9.8, -9.8, -8.9, -9.8,
3.0, 3.0, -0.0, -0.0, finf, finf, 42.0, 42.0, fminf, fminf, fnan};
float resf1[kTableLength] = {
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8,
9.8, -10.0, -11.2, -9.8, 3.0, 3.0, float_nan
};
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8, 9.8, -10.0, -11.2, -9.8,
3.0, 3.0, 0.0, 0.0, finf, finf, finf, finf, finf, finf, fnan};
__ ldc1(f2, MemOperand(a0, offsetof(TestFloat, a)) );
__ ldc1(f4, MemOperand(a0, offsetof(TestFloat, b)) );
......
test/cctest/test-assembler-mips64.cc
View file @ a58c750c
......@@ -1586,10 +1586,10 @@ TEST(min_max) {
CcTest::InitializeVM();
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
MacroAssembler assm(isolate, NULL, 0,
MacroAssembler assm(isolate, nullptr, 0,
v8::internal::CodeObjectRequired::kYes);
typedef struct test_float {
struct TestFloat {
double a;
double b;
double c;
......@@ -1598,21 +1598,35 @@ TEST(min_max) {
float f;
float g;
float h;
} TestFloat;
};
TestFloat test;
const double double_nan = std::numeric_limits<double>::quiet_NaN();
const float float_nan = std::numeric_limits<float>::quiet_NaN();
const int kTableLength = 5;
double inputsa[kTableLength] = {2.0, 3.0, double_nan, 3.0, double_nan};
double inputsb[kTableLength] = {3.0, 2.0, 3.0, double_nan, double_nan};
double outputsdmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, double_nan};
double outputsdmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, double_nan};
float inputse[kTableLength] = {2.0, 3.0, float_nan, 3.0, float_nan};
float inputsf[kTableLength] = {3.0, 2.0, 3.0, float_nan, float_nan};
float outputsfmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, float_nan};
float outputsfmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, float_nan};
const double dnan = std::numeric_limits<double>::quiet_NaN();
const double dinf = std::numeric_limits<double>::infinity();
const double dminf = -std::numeric_limits<double>::infinity();
const float fnan = std::numeric_limits<float>::quiet_NaN();
const float finf = std::numeric_limits<float>::infinity();
const float fminf = std::numeric_limits<float>::infinity();
const int kTableLength = 13;
double inputsa[kTableLength] = {2.0, 3.0, dnan, 3.0, -0.0, 0.0, dinf,
dnan, 42.0, dinf, dminf, dinf, dnan};
double inputsb[kTableLength] = {3.0, 2.0, 3.0, dnan, 0.0, -0.0, dnan,
dinf, dinf, 42.0, dinf, dminf, dnan};
double outputsdmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, -0.0,
-0.0, dinf, dinf, 42.0, 42.0,
dminf, dminf, dnan};
double outputsdmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, 0.0, 0.0, dinf,
dinf, dinf, dinf, dinf, dinf, dnan};
float inputse[kTableLength] = {2.0, 3.0, fnan, 3.0, -0.0, 0.0, finf,
fnan, 42.0, finf, fminf, finf, fnan};
float inputsf[kTableLength] = {3.0, 2.0, 3.0, fnan, -0.0, 0.0, fnan,
finf, finf, 42.0, finf, fminf, fnan};
float outputsfmin[kTableLength] = {2.0, 2.0, 3.0, 3.0, -0.0,
-0.0, finf, finf, 42.0, 42.0,
fminf, fminf, fnan};
float outputsfmax[kTableLength] = {3.0, 3.0, 3.0, 3.0, 0.0, 0.0, finf,
finf, finf, finf, finf, finf, fnan};
__ ldc1(f4, MemOperand(a0, offsetof(TestFloat, a)));
__ ldc1(f8, MemOperand(a0, offsetof(TestFloat, b)));
......@@ -1946,16 +1960,20 @@ TEST(rint_s) {
TEST(mina_maxa) {
if (kArchVariant == kMips64r6) {
const int kTableLength = 15;
const int kTableLength = 23;
CcTest::InitializeVM();
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
MacroAssembler assm(isolate, NULL, 0,
MacroAssembler assm(isolate, nullptr, 0,
v8::internal::CodeObjectRequired::kYes);
const double double_nan = std::numeric_limits<double>::quiet_NaN();
const float float_nan = std::numeric_limits<float>::quiet_NaN();
typedef struct test_float {
const double dnan = std::numeric_limits<double>::quiet_NaN();
const double dinf = std::numeric_limits<double>::infinity();
const double dminf = -std::numeric_limits<double>::infinity();
const float fnan = std::numeric_limits<float>::quiet_NaN();
const float finf = std::numeric_limits<float>::infinity();
const float fminf = std::numeric_limits<float>::infinity();
struct TestFloat {
double a;
double b;
double resd;
......@@ -1964,41 +1982,34 @@ TEST(mina_maxa) {
float d;
float resf;
float resf1;
}TestFloat;
};
TestFloat test;
double inputsa[kTableLength] = {
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9,
-9.8, -10.0, -8.9, -9.8, double_nan, 3.0, double_nan
};
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9, -9.8, -10.0, -8.9, -9.8,
dnan, 3.0, -0.0, 0.0, dinf, dnan, 42.0, dinf, dminf, dinf, dnan};
double inputsb[kTableLength] = {
4.8, 5.3, 6.1, -10.0, -8.9, -9.8, 9.8, 9.8,
9.8, -9.8, -11.2, -9.8, 3.0, double_nan, double_nan
};
4.8, 5.3, 6.1, -10.0, -8.9, -9.8, 9.8, 9.8, 9.8, -9.8, -11.2, -9.8,
3.0, dnan, 0.0, -0.0, dnan, dinf, dinf, 42.0, dinf, dminf, dnan};
double resd[kTableLength] = {
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9,
-9.8, -9.8, -8.9, -9.8, 3.0, 3.0, double_nan
};
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9, -9.8, -9.8, -8.9, -9.8,
3.0, 3.0, -0.0, -0.0, dinf, dinf, 42.0, 42.0, dminf, dminf, dnan};
double resd1[kTableLength] = {
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8,
9.8, -10.0, -11.2, -9.8, 3.0, 3.0, double_nan
};
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8, 9.8, -10.0, -11.2, -9.8,
3.0, 3.0, 0.0, 0.0, dinf, dinf, dinf, dinf, dinf, dinf, dnan};
float inputsc[kTableLength] = {
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9,
-9.8, -10.0, -8.9, -9.8, float_nan, 3.0, float_nan
};
float inputsd[kTableLength] = {
4.8, 5.3, 6.1, -10.0, -8.9, -9.8, 9.8, 9.8,
9.8, -9.8, -11.2, -9.8, 3.0, float_nan, float_nan
};
5.3, 4.8, 6.1, 9.8, 9.8, 9.8, -10.0, -8.9, -9.8, -10.0, -8.9, -9.8,
fnan, 3.0, -0.0, 0.0, finf, fnan, 42.0, finf, fminf, finf, fnan};
float inputsd[kTableLength] = {4.8, 5.3, 6.1, -10.0, -8.9, -9.8,
9.8, 9.8, 9.8, -9.8, -11.2, -9.8,
3.0, fnan, -0.0, 0.0, fnan, finf,
finf, 42.0, finf, fminf, fnan};
float resf[kTableLength] = {
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9,
-9.8, -9.8, -8.9, -9.8, 3.0, 3.0, float_nan
};
4.8, 4.8, 6.1, 9.8, -8.9, -9.8, 9.8, -8.9, -9.8, -9.8, -8.9, -9.8,
3.0, 3.0, -0.0, -0.0, finf, finf, 42.0, 42.0, fminf, fminf, fnan};
float resf1[kTableLength] = {
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8,
9.8, -10.0, -11.2, -9.8, 3.0, 3.0, float_nan
};
5.3, 5.3, 6.1, -10.0, 9.8, 9.8, -10.0, 9.8, 9.8, -10.0, -11.2, -9.8,
3.0, 3.0, 0.0, 0.0, finf, finf, finf, finf, finf, finf, fnan};
__ ldc1(f2, MemOperand(a0, offsetof(TestFloat, a)) );
__ ldc1(f4, MemOperand(a0, offsetof(TestFloat, b)) );
......
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