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  1. 26 Oct, 2016 1 commit
    • bbudge's avatar
      [Turbofan] Add concept of FP register aliasing on ARM 32. · 09ab8e6a
      bbudge authored 
      - Modifies RegisterConfiguration to specify complex aliasing on ARM 32.
- Modifies RegisterAllocator to consider aliasing.
- Modifies ParallelMove::PrepareInsertAfter to handle aliasing.
- Modifies GapResolver to split wider register moves when interference
with smaller moves is detected.
- Modifies MoveOptimizer to handle aliasing.
- Adds ARM 32 macro-assembler pseudo move instructions to handle cases where
  split moves don't correspond to actual s-registers.
- Modifies CodeGenerator::AssembleMove and AssembleSwap to handle moves of
  different widths, and moves involving pseudo-s-registers.
- Adds unit tests for FP operand interference checking and PrepareInsertAfter.
- Adds more tests of FP for the move optimizer and register allocator.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2410673002
Cr-Commit-Position: refs/heads/master@{#40597}
      09ab8e6a
  3. 11 Oct, 2016 1 commit
    • mtrofin's avatar
      [turbofan] Avoid large deopt blocks · 33629651
      mtrofin authored 
      Treat allocation of splintered ranges differently, by optimizing for move
counts (i.e. try to have less move counts), rather than optimizing for
quality of moves (which is what normal allocation does).

We can see reductions in code size in the benchmarks that measure it
(e.g. Unity)

BUG=

Review-Url: https://codereview.chromium.org/2347563004
Cr-Commit-Position: refs/heads/master@{#40178}
      33629651
  5. 19 Sep, 2016 1 commit
  7. 06 Sep, 2016 1 commit
  9. 01 Sep, 2016 1 commit
  11. 16 Aug, 2016 1 commit
  13. 29 Jul, 2016 1 commit
  15. 18 Jul, 2016 1 commit
    • bmeurer's avatar
      [turbofan] Add support for eager/soft deoptimization reasons. · db635d5b
      bmeurer authored 
      So far TurboFan wasn't adding the deoptimization reasons for eager/soft
deoptimization exits that can be used by either the DevTools profiler or
the --trace-deopt flag. This adds basic support for deopt reasons on
Deoptimize, DeoptimizeIf and DeoptimizeUnless nodes and threads through
the reasons to the code generation.

Also moves the DeoptReason to it's own file (to resolve include cycles)
and drops unused reasons.

R=jarin@chromium.org

Review-Url: https://codereview.chromium.org/2161543002
Cr-Commit-Position: refs/heads/master@{#37823}
      db635d5b
  17. 04 Jul, 2016 1 commit
  19. 30 Jun, 2016 1 commit
    • ahaas's avatar
      [turbofan] Don't call String::Flatten in Constant::ToHeapObject() · 5d8cfbbd
      ahaas authored 
      The call to String::Flatten can cause garbage collection and in general adds
complexity to the code generation. It also blocks the way to run code generation on worker threads.

The call to String::Flatten in Constant::ToHeapObject() seems not to be necessary
for correctness. If removing this call affects performance negatively, we can revert
this CL.

Review-Url: https://codereview.chromium.org/2107243002
Cr-Commit-Position: refs/heads/master@{#37422}
      5d8cfbbd
  21. 29 Jun, 2016 2 commits
    • georgia.kouveli's avatar
      [arm64] Generate adds/ands. · 317dc057
      georgia.kouveli authored 
      Perform the following transformation:

    | Before           | After               |
    |------------------+---------------------|
    | add w2, w0, w1   | adds w2, w0, w1     |
    | cmp w2, #0x0     | b.<cond'> <addr>    |
    | b.<cond> <addr>  |                     |
    |------------------+---------------------|
    | add w2, w0, w1   | adds w2, w0, w1     |
    | cmp #0x0, w2     | b.<cond'> <addr>    |
    | b.<cond> <addr>  |                     |

and the same for and instructions instead of add.  When the result of the
add/and is not used, generate cmn/tst instead. We need to take care with which
conditions we can handle and what new condition we map them to.

BUG=

Review-Url: https://codereview.chromium.org/2065243005
Cr-Commit-Position: refs/heads/master@{#37400}
      317dc057
    • bbudge's avatar
      [Turbofan] Simplify operand canonicalization on archs with simple FP aliasing. · 4b76dc85
      bbudge authored 
      - Changes InstructionOperand canonicalization to map all FP operands to kFloat64 on Intel and other platforms with simple aliasing.
- Bypass expensive interference calculations and fixed FP live range processing for platforms with simple aliasing.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2101653003
Cr-Commit-Position: refs/heads/master@{#37388}
      4b76dc85
  23. 27 Jun, 2016 1 commit
  25. 24 Jun, 2016 2 commits
    • bbudge's avatar
      [Turbofan] Add the concept of aliasing to RegisterConfiguration. · a933b704
      bbudge authored 
      - Adds the concept of FP register aliasing to RegisterConfiguration.
- Changes RegisterAllocator to distinguish between FP representations
when allocating.
- Changes LinearScanAllocator to detect interference when FP register
aliasing is combining, as on ARM.
- Changes ARM code generation to allow all registers s0 - s31 to be
accessed.
- Adds unit tests for RegisterConfiguration, mostly to test aliasing
calculations.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2086653003
Cr-Commit-Position: refs/heads/master@{#37251}
      a933b704
    • balazs.kilvady's avatar
      Fix '[tests] Don't test moves between different reps in test-gap-resolver.cc' · 5cda2db7
      balazs.kilvady authored 
      Port fc59eb8a

Original commit message:
Moves between operands with different representations shouldn't happen,
so don't test them. This makes it easier to modify canonicalization to
differentiate between floating point types, which is needed to support
floating point register aliasing for ARM and MIPS.

This change also expands tests to include explicit FP moves (both register and stack slot).

LOG=N
BUG=v8:4124
BUG=chromium:622619

Review-Url: https://codereview.chromium.org/2090993002
Cr-Commit-Position: refs/heads/master@{#37241}
      5cda2db7
  27. 15 Jun, 2016 1 commit
  29. 03 Jun, 2016 1 commit
  31. 27 May, 2016 1 commit
  33. 10 May, 2016 1 commit
    • bbudge's avatar
      [turbofan] Rename floating point register / slot methods. · 8c8600db
      bbudge authored 
      Renames IsDouble* predicates to IsFP*.
Adds specific IsFloat*, IsDouble*, and IsSimd128* predicates.
Adds specific GetFloatRegister, GetDoubleRegister, and
GetSimd128Register methods.

This is mostly a mechanical renaming of IsDouble* to IsFP* methods.

This shouldn't change code generation at all. All fp registers are still
treated as double registers.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/1959763002
Cr-Commit-Position: refs/heads/master@{#36146}
      8c8600db
  35. 04 May, 2016 1 commit
    • gdeepti's avatar
      Add new relocation type WASM_MEMORY_SIZE_REFERENCE, use relocatable pointers... · 117a56b7
      gdeepti authored 
      Add new relocation type WASM_MEMORY_SIZE_REFERENCE, use relocatable pointers to update wasm memory size references in generated code.
 - Add new RelocInfo mode WASM_MEMORY_SIZE_REFERENCE in the assembler and add relocation information to immediates in compare instructions.
 - Use relocatable constants for MemSize/BoundsCheck in the wasm compiler

R=titzer@chromium.org, yangguo@chromium.org, bradnelson@chromium.org

Review-Url: https://codereview.chromium.org/1921203002
Cr-Commit-Position: refs/heads/master@{#36044}
      117a56b7
  37. 30 Apr, 2016 1 commit
    • bmeurer's avatar
      [turbofan] Run everything after representation selection concurrently. · d1b3d426
      bmeurer authored 
      Further refactor the pipeline to even run the first scheduler (part of
the effect control linearization) concurrently. This temporarily
disables most of the write barrier elimination, but we will get back to
that later.

Drive-by-fix: Remove the dead code from ChangeLowering, and stack
allocate the Typer in the pipeline. Also migrate the AllocateStub to a
native code builtin, so that we have the code object + a handle to it
available all the time.

CQ_INCLUDE_TRYBOTS=tryserver.v8:v8_linux64_tsan_rel
R=mstarzinger@chromium.org
BUG=v8:4969
LOG=n

Review-Url: https://codereview.chromium.org/1926023002
Cr-Commit-Position: refs/heads/master@{#35918}
      d1b3d426
  39. 28 Apr, 2016 2 commits
  41. 23 Apr, 2016 1 commit
    • mtrofin's avatar
      [turbofan] Single entry into deferred · 5ae587cf
      mtrofin authored 
      If a deferred block has multiple predecessors, they have to be
all deferred. Otherwise, we can run into a situation where if a range
that spills only in deferred blocks inserts its spill in the block, and
other ranges need moves inserted by ResolveControlFlow in the predecessors,
the register of the range spilled in the deferred block may be clobbered.

To avoid that, when a deferred block has multiple predecessors, and some
are not deferred, we add a non-deferred block to collect all such edges.

This CL addresses the validator assertion failure the referenced issue, as well
as the greedy allocator failure - which was caused by the situation described
above.

BUG=v8:4940
LOG=n

Review URL: https://codereview.chromium.org/1912093005

Cr-Commit-Position: refs/heads/master@{#35742}
      5ae587cf
  43. 21 Apr, 2016 1 commit
  45. 12 Apr, 2016 2 commits
  47. 11 Apr, 2016 1 commit
  49. 01 Apr, 2016 2 commits
  51. 23 Mar, 2016 1 commit
    • mtrofin's avatar
      [turbofan] Validation for deferred->hot transition edges · 66c6cadc
      mtrofin authored 
      Validate that the transition from deferred to hot happens through a
deferred block with one successor. This is needed for frame elision: if
we need to deconstruct the frame on the deferred path, this extra block
offers that location.

A precondition for this validation is that the sequence is in split edge
form.

BUG=

Review URL: https://codereview.chromium.org/1811213003

Cr-Commit-Position: refs/heads/master@{#35015}
      66c6cadc
  53. 18 Mar, 2016 1 commit
  55. 04 Mar, 2016 1 commit
  57. 29 Feb, 2016 1 commit
  59. 24 Feb, 2016 1 commit
  61. 17 Feb, 2016 1 commit
  63. 05 Feb, 2016 1 commit
  65. 26 Jan, 2016 1 commit
    • mtrofin's avatar
      [turbofan] InstructionBlock::PrintBlock · e3edb12f
      mtrofin authored 
      Debugging helper. Centralized the logic for printing blocks from
InstructionSequence.

A clean(-er) design would be to define an operator<< on a
PrintableInstructionBlock. However, we've discussed moving off those
operators, so it seemed unnecessary to complicate the change.

BUG=

Review URL: https://codereview.chromium.org/1632803003

Cr-Commit-Position: refs/heads/master@{#33505}
      e3edb12f
  67. 11 Jan, 2016 1 commit
  69. 05 Jan, 2016 1 commit
    • sigurds's avatar
      [turbofan] Deopt support for escape analysis · 3b473d7a
      sigurds authored 
      Deopt support is added on two levels. On the IR level,
a new ObjectState node is added, which represenents an
object to be materialized. ObjectState nodes appear as
inputs of FrameState and StateValues nodes. On the
instruction select/code-generation level, the
FrameStateDescriptor class handles the nesting
introduced by ObjectState, and ensures that deopt code
with CAPTURED_OBJECT/DUPLICATED_OBJECT entries are
generated similarly to what crankshaft's escape
analysis does.

Two unittests test correctness of the IR level implementation.

Correctness for instruction selection / code generation
is tested by mjsunit tests.

R=jarin@chromium.org,mstarzinger@chromium.org
BUG=v8:4586
LOG=n

Review URL: https://codereview.chromium.org/1485183002

Cr-Commit-Position: refs/heads/master@{#33115}
      3b473d7a