1. 12 Jul, 2017 1 commit
  2. 05 Jul, 2017 1 commit
  3. 30 Jun, 2017 1 commit
  4. 29 Jun, 2017 1 commit
  5. 28 Jun, 2017 1 commit
  6. 27 Jun, 2017 1 commit
  7. 20 Jun, 2017 1 commit
  8. 19 Jun, 2017 1 commit
  9. 13 Jun, 2017 1 commit
  10. 08 Jun, 2017 1 commit
    • bbudge's avatar
      [WASM] Eliminate SIMD boolean vector types. · 381f7da0
      bbudge authored
      - Eliminates b1x4, b1x8, and b1x16 as distinct WASM types.
      - All vector comparisons return v128 type.
      - Eliminates b1xN and, or, xor, not.
      - Selects take a v128 mask vector and are now bit-wise.
      - Adds a new test for Select, where mask is non-canonical (not 0's and -1's).
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2919203002
      Cr-Commit-Position: refs/heads/master@{#45795}
      381f7da0
  11. 01 Jun, 2017 1 commit
  12. 25 May, 2017 1 commit
    • bbudge's avatar
      [Turbofan] Remove UnallocatedOperand::set_virtual_register. · 5dde8b31
      bbudge authored
      - Removes set_virtual_register method. InstructionOperands are immutable.
      - Adds a new ctor to copy an UnallocatedOperand with a new vreg.
      - Removes some DCHECKs in UnallocatedOperand that are always true. To
        make sure, make UnallocatedOperand final.
      - Cleans up some comments on UnallocatedOperand Lifetime enum.
      
      BUG=v8:6325
      
      Review-Url: https://codereview.chromium.org/2897203002
      Cr-Commit-Position: refs/heads/master@{#45533}
      5dde8b31
  13. 24 May, 2017 1 commit
    • dusan.simicic's avatar
      MIPS[64]: Support for some SIMD operations (7) · a8421ddd
      dusan.simicic authored
      Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS,
      I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS,
      I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU,
      I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for
      mips32 and mips64 architectures.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2798853003
      Cr-Commit-Position: refs/heads/master@{#45512}
      a8421ddd
  14. 22 May, 2017 1 commit
  15. 21 May, 2017 1 commit
    • gdeepti's avatar
      [wasm] Swap the implementation of SIMD compare ops using Gt/Ge insteas of Lt/Le · eeefc74a
      gdeepti authored
      Currently SIMD integer comparison ops are implemented using Lt/Le, this is
      sub-optimal on Intel, because all compares are done using pcmpgt(d/w/b) that
      clobber the destination register, and will need additional instructions to
      when using Lt/Le as the base implementation. This CL proposes moving to Gt/Ge
      as the underlying implementation as this will only require swapping operands
      on MIPS and is consistent with x86/ARM instructions.
      
      BUG=v8:6020
      
      R=bbudge@chromium.org, bmeurer@chromium.org, bradnelson@chromium.org
      
      Review-Url: https://codereview.chromium.org/2874403002
      Cr-Commit-Position: refs/heads/master@{#45440}
      eeefc74a
  16. 16 May, 2017 1 commit
  17. 15 May, 2017 2 commits
  18. 09 May, 2017 2 commits
  19. 04 May, 2017 2 commits
  20. 02 May, 2017 1 commit
  21. 24 Apr, 2017 1 commit
  22. 21 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Remove opcodes that are slow on some platforms. · dddfcfd0
      bbudge authored
      These can be synthesized from existing operations and scheduled for
      better performance than if we have to generate blocks of instructions
      that take many cycles to complete.
      - Remove F32x4RecipRefine, F32x4RecipSqrtRefine. Clients are better off
        synthesizing these from splats, multiplies and adds.
      - Remove F32x4Div, F32x4Sqrt, F32x4MinNum, F32x4MaxNum. Clients are
        better off synthesizing these or using the reciprocal approximations,
        possibly with a refinement step.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2827143002
      Cr-Commit-Position: refs/heads/master@{#44784}
      dddfcfd0
  23. 19 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Implement primitive shuffles. · 5806d862
      bbudge authored
      - Adds unary Reverse shuffles (swizzles): S32x2Reverse, S16x4Reverse,
        S16x2Reverse, S8x8Reverse, S8x4Reverse, S8x2Reverse. Reversals are
        done within the sub-vectors that prefix the opcode name, e.g. S8x2
        reverses the 8 consecutive pairs in an S8x16 vector.
      
      - Adds binary Zip (interleave) left and right half-shuffles to return a
        single vector: S32x4ZipLeft, S32x4ZipRightS16x8ZipLeft, S16x8ZipRight,
        S8x16ZipLeft, S8x16ZipRight.
      
      - Adds binary Unzip (de-interleave) left and right half shuffles to return
        a single vector: S32x4UnzipLeft, S32x4UnzipRight, S16x8UnzipLeft,
        S16x8UnzipRight, S8x16UnzipLeft, S8x16UnzipRight.
      
      - Adds binary Transpose left and right half shuffles to return
        a single vector: S32x4TransposeLeft, S32x4TransposeRight,
        S16x8TransposeLeft, S16xTransposeRight, S8x16TransposeLeft,
        S8x16TransposeRight.
      
      - Adds binary Concat (concatenate) byte shuffle: S8x16Concat #bytes to
        paste two vectors together.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2801183002
      Cr-Commit-Position: refs/heads/master@{#44734}
      5806d862
  24. 18 Apr, 2017 2 commits
  25. 17 Apr, 2017 1 commit
    • gdeepti's avatar
      [wasm] Implement wasm x64 I16x8 Ops · c8c03c15
      gdeepti authored
       - Add I16x8 Splat, ExtractLane, ReplaceLane, shift ops, Some BinOps and compare ops
       - Add pshufhw, pshuflw in the assembler, disassembler
       - Fix incorrect modrm for pextrw, this bug disregards the register allocated and always makes pextrw use rax.
       - Fix pextrw disasm to take the 0 - 7 bits of the immediate instead of 0 - 3.
       - Pextrw, pinsrw are in the assembler use 128 bit encodings, pextrw, pinsrw in the disassembler use legacy encodings, fix inconsistencies causing weird code gen when --print-code is used.
      
      Review-Url: https://codereview.chromium.org/2767983002
      Cr-Commit-Position: refs/heads/master@{#44664}
      c8c03c15
  26. 12 Apr, 2017 1 commit
  27. 11 Apr, 2017 2 commits
  28. 10 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Implement packing and unpacking integer conversions. · dbfc0300
      bbudge authored
      - Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High,
        I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of
        an I16x8 register into a whole I32x4 register, with signed or unsigned
        extension. Having separate Low/High opcodes works around the difficulty
        of having multiple output registers, which would be necessary if we unpacked
        the entire I16x8 register.
      
      - Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High,
        I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above.
      
      - Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4,
        I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers
        into a single destination register with signed or unsigned saturation. These
        could have been separated into half operations, but this is simpler to
        implement with SSE, AVX, and is acceptable on ARM. It also avoids adding
        operations that only modify half of their destination register.
      
      - Implements these opcodes for ARM.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2800523002
      Cr-Commit-Position: refs/heads/master@{#44541}
      dbfc0300
  29. 04 Apr, 2017 1 commit
  30. 03 Apr, 2017 1 commit
  31. 31 Mar, 2017 1 commit
  32. 29 Mar, 2017 1 commit
  33. 16 Mar, 2017 1 commit
  34. 15 Mar, 2017 2 commits