- 12 Jul, 2017 1 commit
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Michael Starzinger authored
This introduces 2^16 as an upper limit for the allowed value range of a table switch on all architectures. It also fixes several overflows in the table size calculation. R=bmeurer@chromium.org TEST=mjsunit/regress/regress-crbug-736633 BUG=chromium:736633 Change-Id: I931bd226c99eb8a1ae1770c159fc314ff650bf57 Reviewed-on: https://chromium-review.googlesource.com/566829Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#46575}
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- 05 Jul, 2017 1 commit
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jing.bao authored
Add Pxor, Pshuflw, Pshufb, Pextrb, Pextrw macros Reconstruct SIMD opcodes to macros BUG= Review-Url: https://codereview.chromium.org/2937653002 Cr-Commit-Position: refs/heads/master@{#46400}
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- 30 Jun, 2017 1 commit
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Leszek Swirski authored
With FCG no longer able to deoptimize, we can remove the "push" version of output frame state combine, as deoptimisation to bytecode is always the PokeAt variant. Bug: v8:6409 Change-Id: I9b6d38a7441ca834835615c238228fa8a75a027b Reviewed-on: https://chromium-review.googlesource.com/557866 Commit-Queue: Leszek Swirski <leszeks@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#46355}
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- 29 Jun, 2017 1 commit
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gdeepti authored
Ops Implemented: I32x4Neg, I32x4GtS, I32x4GeS, I32x4GtU, I32x4GeU, I16x8Neg, I16x8GtS, I16x8GeS, I16x8GtU, I16x8GeU I8x16Neg, I8x16GtS, I8x16GeS, I8x16GtU, I8x16GeU S128Not BUG=v8:6020 R=bbudge@chromium.org, zvi.rackover@intel.com, mtrofin@chromium.org Review-Url: https://codereview.chromium.org/2951793003 Cr-Commit-Position: refs/heads/master@{#46329}
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- 28 Jun, 2017 1 commit
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Dusan Simicic authored
Add support for F32x4AddHoriz, I32x4AddHoriz, I16x8AddHoriz operations for mips32 and mips64 architectures. Bug: Change-Id: I5a40f23677418ffd81d4d5229203a439545575b8 Reviewed-on: https://chromium-review.googlesource.com/518016 Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Mircea Trofin <mtrofin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Miran Karić <Miran.Karic@imgtec.com> Reviewed-by:
Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Cr-Commit-Position: refs/heads/master@{#46272}
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- 27 Jun, 2017 1 commit
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Dusan Simicic authored
Add support for I32x4SConvertI16x8Low, I32x4SConvertI16x8High, I32x4UConvertI16x8Low, I32x4UConvertI16x8High, I16x8SConvertI8x16Low, I16x8SConvertI8x16High,I16x8SConvertI32x4, I16x8UConvertI32x4, I16x8UConvertI8x16Low, I16x8UConvertI8x16High, I8x16SConvertI16x8, I8x16UConvertI16x8 operations for mips32 and mips64 architectures. Bug: Change-Id: I32f24956fc8e3c7df7f525bf0d4518161493a3ed Reviewed-on: https://chromium-review.googlesource.com/517500 Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Mircea Trofin <mtrofin@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Miran Karić <Miran.Karic@imgtec.com> Reviewed-by:
Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Cr-Commit-Position: refs/heads/master@{#46260}
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- 20 Jun, 2017 1 commit
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Dusan Simicic authored
Add support for S32x4Shuffle, S16x8Shuffle, S8x16Shuffle for mips and mips64 architectures. Bug: Change-Id: I2c062525ed94edfcb38a53f4bbef02131e313ba3 Reviewed-on: https://chromium-review.googlesource.com/531007 Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Reviewed-by:
Bill Budge <bbudge@chromium.org> Reviewed-by:
Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Reviewed-by:
Mircea Trofin <mtrofin@chromium.org> Cr-Commit-Position: refs/heads/master@{#46053}
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- 19 Jun, 2017 1 commit
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Bill Budge authored
BUG: v8:6020 Change-Id: I7280827aa9a493677253cc2fbd42be8173b55b7a Reviewed-on: https://chromium-review.googlesource.com/534956Reviewed-by:
Martyn Capewell <martyn.capewell@arm.com> Reviewed-by:
Mircea Trofin <mtrofin@chromium.org> Commit-Queue: Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#46018}
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- 13 Jun, 2017 1 commit
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bbudge authored
- Eliminates S32x4Shuffle, S16x8Shuffle opcodes. All shuffles are subsumed by S8x16Shuffle. This aligns us with the latest WASM SIMD spec. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2923103003 Cr-Commit-Position: refs/heads/master@{#45929}
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- 08 Jun, 2017 1 commit
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bbudge authored
- Eliminates b1x4, b1x8, and b1x16 as distinct WASM types. - All vector comparisons return v128 type. - Eliminates b1xN and, or, xor, not. - Selects take a v128 mask vector and are now bit-wise. - Adds a new test for Select, where mask is non-canonical (not 0's and -1's). LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2919203002 Cr-Commit-Position: refs/heads/master@{#45795}
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- 01 Jun, 2017 1 commit
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dusan.simicic authored
Add support for S1x4And, S1x4Or, S1x4Xor, S1x4Not, S1x4AnyTrue, S1x4AllTrue, S1x8And, S1x8Or, S1x8Xor, S1x8Not, S1x8AnyTrue, S1x8AllTrue, S1x16And, S1x16Or, S1x16Xor, S1x16Not, S1x16AnyTrue, S1x16AllTrue, SimdLoad, SimdStore operations for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2801683003 Cr-Commit-Position: refs/heads/master@{#45662}
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- 25 May, 2017 1 commit
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bbudge authored
- Removes set_virtual_register method. InstructionOperands are immutable. - Adds a new ctor to copy an UnallocatedOperand with a new vreg. - Removes some DCHECKs in UnallocatedOperand that are always true. To make sure, make UnallocatedOperand final. - Cleans up some comments on UnallocatedOperand Lifetime enum. BUG=v8:6325 Review-Url: https://codereview.chromium.org/2897203002 Cr-Commit-Position: refs/heads/master@{#45533}
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- 24 May, 2017 1 commit
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dusan.simicic authored
Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS, I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS, I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU, I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2798853003 Cr-Commit-Position: refs/heads/master@{#45512}
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- 22 May, 2017 1 commit
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Wiktor Garbacz authored
Change-Id: I20ed35a7fb5104a9cc66bb54fa8966589c43d7f9 Reviewed-on: https://chromium-review.googlesource.com/507287Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Daniel Clifford <danno@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Marja Hölttä <marja@chromium.org> Reviewed-by:
Jochen Eisinger <jochen@chromium.org> Commit-Queue: Wiktor Garbacz <wiktorg@google.com> Cr-Commit-Position: refs/heads/master@{#45458}
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- 21 May, 2017 1 commit
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gdeepti authored
Currently SIMD integer comparison ops are implemented using Lt/Le, this is sub-optimal on Intel, because all compares are done using pcmpgt(d/w/b) that clobber the destination register, and will need additional instructions to when using Lt/Le as the base implementation. This CL proposes moving to Gt/Ge as the underlying implementation as this will only require swapping operands on MIPS and is consistent with x86/ARM instructions. BUG=v8:6020 R=bbudge@chromium.org, bmeurer@chromium.org, bradnelson@chromium.org Review-Url: https://codereview.chromium.org/2874403002 Cr-Commit-Position: refs/heads/master@{#45440}
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- 16 May, 2017 1 commit
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ivica.bogosavljevic authored
Reland d8bfdb7a Original commit message: If alignment parameter is set, the memory returned by the StackSlot operator will be aligned according to the parameter. The implementation goes like this. If alignment parameter is set we allocate a bit more memory than actually needed and so we can move the beginning of the StackSlot in order to have it aligned. BUG= Review-Url: https://codereview.chromium.org/2874713003 Cr-Commit-Position: refs/heads/master@{#45339}
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- 15 May, 2017 2 commits
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dusan.simicic authored
Add support for I16x8Mul, I16x8MaxS, I16x8MinS, I16x8Eq, I16x8Ne, I16x8LtS, I16x8LeS, I16x8AddSaturateU, I16x8SubSaturateU, I16x8MaxU, I16x8MinU, I16x8LtU, I16x8LeU, I8x16Splat, I8x16ExtractLane, I8x16ReplaceLane, I8x16Neg, I8x16Shl, I8x16ShrS, S16x8Select, S8x16Select for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2791213003 Cr-Commit-Position: refs/heads/master@{#45312}
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Camillo Bruni authored
- Add BasicBlock::Print method for easier inspection in gdb - Print detailed error message in InstructionSelector::VisitControl instead of just a check failure Change-Id: Ice9d70567114f014b244c1b4e41e450900030994 Reviewed-on: https://chromium-review.googlesource.com/504388 Commit-Queue: Camillo Bruni <cbruni@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#45295}
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- 09 May, 2017 2 commits
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machenbach authored
Revert of [turbofan] Add alignment parameter to StackSlot operator (patchset #7 id:120001 of https://codereview.chromium.org/2816743003/ ) Reason for revert: Seems to break cfi: https://build.chromium.org/p/client.v8/builders/V8%20Linux64%20-%20cfi/builds/9989 Original issue's description: > [turbofan] Add alignment parameter to StackSlot operator > > If alignment parameter is set, the memory returned by the > StackSlot operator will be aligned according to the parameter. > > The implementation goes like this. If alignment parameter is set > we allocate a bit more memory than actually needed and so we > can move the beginning of the StackSlot in order to have it aligned. > > > BUG= > > Review-Url: https://codereview.chromium.org/2816743003 > Cr-Commit-Position: refs/heads/master@{#45197} > Committed: https://chromium.googlesource.com/v8/v8/+/d8bfdb7a998adadc56aa5705a5998e75ceae7675 TBR=ahaas@chromium.org,clemensh@chromium.org,titzer@chromium.org,bmeurer@chromium.org,ivica.bogosavljevic@imgtec.com # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review-Url: https://codereview.chromium.org/2867403002 Cr-Commit-Position: refs/heads/master@{#45203}
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ivica.bogosavljevic authored
If alignment parameter is set, the memory returned by the StackSlot operator will be aligned according to the parameter. The implementation goes like this. If alignment parameter is set we allocate a bit more memory than actually needed and so we can move the beginning of the StackSlot in order to have it aligned. BUG= Review-Url: https://codereview.chromium.org/2816743003 Cr-Commit-Position: refs/heads/master@{#45197}
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- 04 May, 2017 2 commits
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bbudge authored
- Removes primitive shuffle opcodes. - Adds Shuffle opcode for S32x4, S16x8, S8x16. - Adds code to ARM instruction selector to pick best opcodes for some common shuffle patterns. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2847663005 Cr-Commit-Position: refs/heads/master@{#45104}
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dusan.simicic authored
Add support for I32x4Neg, I32x4LtS, I32x4LeS, I32x4LtU, I32x4LeU, I16x8Splat, I16x8ExtractLane, I16x8ReplaceLane, I16x8Neg, I16x8Shl, I16x8ShrS, I16x8ShrU, I16x8Add, I16x8AddSaturateS, I16x8Sub, I16x8SubSaturateS for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2795143003 Cr-Commit-Position: refs/heads/master@{#45092}
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- 02 May, 2017 1 commit
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gdeepti authored
- Ops: S128Load, S128Store, S128And, S128Or, S128Xor, S128Not, I32x4AddHoriz, I16x8AddHoriz - Add x64 assembler support for - phaddd, phaddw, pand, por - Enable tests for Globals, other tests applicable to x64 apart from tests for implemented ops BUG=v8:6020 R=bbudge@chromium.org, bmeurer@chromium.org, zvi.rackover@intel.com Review-Url: https://codereview.chromium.org/2849463003 Cr-Commit-Position: refs/heads/master@{#45005}
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- 24 Apr, 2017 1 commit
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bbudge authored
- Adds new F32x4AddHoriz, I32x4AddHoriz, etc. to WASM opcodes. - Implements them for ARM. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2804883008 Cr-Commit-Position: refs/heads/master@{#44812}
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- 21 Apr, 2017 1 commit
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bbudge authored
These can be synthesized from existing operations and scheduled for better performance than if we have to generate blocks of instructions that take many cycles to complete. - Remove F32x4RecipRefine, F32x4RecipSqrtRefine. Clients are better off synthesizing these from splats, multiplies and adds. - Remove F32x4Div, F32x4Sqrt, F32x4MinNum, F32x4MaxNum. Clients are better off synthesizing these or using the reciprocal approximations, possibly with a refinement step. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2827143002 Cr-Commit-Position: refs/heads/master@{#44784}
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- 19 Apr, 2017 1 commit
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bbudge authored
- Adds unary Reverse shuffles (swizzles): S32x2Reverse, S16x4Reverse, S16x2Reverse, S8x8Reverse, S8x4Reverse, S8x2Reverse. Reversals are done within the sub-vectors that prefix the opcode name, e.g. S8x2 reverses the 8 consecutive pairs in an S8x16 vector. - Adds binary Zip (interleave) left and right half-shuffles to return a single vector: S32x4ZipLeft, S32x4ZipRightS16x8ZipLeft, S16x8ZipRight, S8x16ZipLeft, S8x16ZipRight. - Adds binary Unzip (de-interleave) left and right half shuffles to return a single vector: S32x4UnzipLeft, S32x4UnzipRight, S16x8UnzipLeft, S16x8UnzipRight, S8x16UnzipLeft, S8x16UnzipRight. - Adds binary Transpose left and right half shuffles to return a single vector: S32x4TransposeLeft, S32x4TransposeRight, S16x8TransposeLeft, S16xTransposeRight, S8x16TransposeLeft, S8x16TransposeRight. - Adds binary Concat (concatenate) byte shuffle: S8x16Concat #bytes to paste two vectors together. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2801183002 Cr-Commit-Position: refs/heads/master@{#44734}
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- 18 Apr, 2017 2 commits
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gdeepti authored
- I8x16Splat, I8x16ExtractLane, I8x16ReplaceLane - Binops: I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS, I8x16MinS, I8x16MaxS, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MinU, I8x16MaxU - Compare ops: I8x16Eq, I8x16Ne BUG=v8:6020 R=bbudge@chromium.org, bmeurer@chromium.org Review-Url: https://codereview.chromium.org/2829483002 Cr-Commit-Position: refs/heads/master@{#44706}
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Michael Starzinger authored
This fixes the de-duplication logic used when writing the deoptimizer translation of a frame-state containing {kArgumentsElementsState}. The object counts as a captured object and participates in the numbering of duplicated objects. R=jarin@chromium.org TEST=mjsunit/regress/regress-crbug-711166 BUG=chromium:711166 Change-Id: I4a3b892017ab8217197e5f94c1a0975d0cd6979f Reviewed-on: https://chromium-review.googlesource.com/476631 Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#44692}
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- 17 Apr, 2017 1 commit
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gdeepti authored
- Add I16x8 Splat, ExtractLane, ReplaceLane, shift ops, Some BinOps and compare ops - Add pshufhw, pshuflw in the assembler, disassembler - Fix incorrect modrm for pextrw, this bug disregards the register allocated and always makes pextrw use rax. - Fix pextrw disasm to take the 0 - 7 bits of the immediate instead of 0 - 3. - Pextrw, pinsrw are in the assembler use 128 bit encodings, pextrw, pinsrw in the disassembler use legacy encodings, fix inconsistencies causing weird code gen when --print-code is used. Review-Url: https://codereview.chromium.org/2767983002 Cr-Commit-Position: refs/heads/master@{#44664}
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- 12 Apr, 2017 1 commit
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dusan.simicic authored
Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox, F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine, F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min, F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4, I32x4UConvertF32x4 operations for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2778203002 Cr-Commit-Position: refs/heads/master@{#44597}
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- 11 Apr, 2017 2 commits
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dusan.simicic authored
Add support for I32x4Mul, I32x4MaxS, I32x4MinS, I32x4Eq, I32x4Ne, I32x4Shl, I32x4ShrS, I32x4ShrU, I32x4MaxU, I32x4MinU, S32x4Select operations for mips32 and mips64 architectures BUG= Review-Url: https://codereview.chromium.org/2780713003 Cr-Commit-Position: refs/heads/master@{#44559}
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aseemgarg authored
BUG=v8:4614 R=binji@chromium.org,jarin@chromium.org Review-Url: https://codereview.chromium.org/2799863002 Cr-Commit-Position: refs/heads/master@{#44542}
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- 10 Apr, 2017 1 commit
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bbudge authored
- Adds WASM opcodes I32x4SConvertI16x8Low, I32x4SConvertI16x8High, I32x4UConvertI16x8Low, I32x4UConvertI16x8High, which unpack half of an I16x8 register into a whole I32x4 register, with signed or unsigned extension. Having separate Low/High opcodes works around the difficulty of having multiple output registers, which would be necessary if we unpacked the entire I16x8 register. - Adds WASM opcodes I16x8SConvertI8x16Low, I16x8SConvertI8x16High, I16x8UConvertI8x16Low, I16x8UConvertI8x16High, similarly to above. - Adds WASM opcodes I16x8SConvertI32x4, I16x8UConvertI32x4, I8x16SConvert16x8, I8x16UConvertI16x8, which pack two source registers into a single destination register with signed or unsigned saturation. These could have been separated into half operations, but this is simpler to implement with SSE, AVX, and is acceptable on ARM. It also avoids adding operations that only modify half of their destination register. - Implements these opcodes for ARM. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2800523002 Cr-Commit-Position: refs/heads/master@{#44541}
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- 04 Apr, 2017 1 commit
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dusan.simicic authored
Add support for F32x4Splat, F32x4ExtractLane, F32x4ReplaceLane, F32x4SConvertI32x4, F32x4UConvertI32x4 operations for mips32 and mips64 architectures. BUG= Note: Depends on https://codereview.chromium.org/2753903004/ Review-Url: https://codereview.chromium.org/2780503002 Cr-Commit-Position: refs/heads/master@{#44359}
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- 03 Apr, 2017 1 commit
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dusan.simicic authored
Adds support for I32x4Splat, I32x4ExtractLane, I32x4ReplaceLane, I32x4Add, I32x4Sub, S128Zero operations for mips32 and mips64 architectures. BUG= Note: Depends on patch: https://codereview.chromium.org/2740123004/ Review-Url: https://codereview.chromium.org/2753903004 Cr-Commit-Position: refs/heads/master@{#44326}
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- 31 Mar, 2017 1 commit
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jyan authored
some arch like s390 has native instr can benefit from this. see ~10% improvement on MathAbs on s390 Review-Url: https://codereview.chromium.org/2785773002 Cr-Commit-Position: refs/heads/master@{#44310}
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- 29 Mar, 2017 1 commit
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gdeepti authored
- Fix opcode names to be consistent with opcodes as in wasm-opcodes.h - Fix Ordering of Ops, inconsistencies BUG=v8:6020 Review-Url: https://codereview.chromium.org/2776753004 Cr-Commit-Position: refs/heads/master@{#44239}
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- 16 Mar, 2017 1 commit
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aseemgarg authored
BUG=v8:4614 R=binji@chromium.org Review-Url: https://codereview.chromium.org/2649703002 Cr-Commit-Position: refs/heads/master@{#43878}
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- 15 Mar, 2017 2 commits
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gdeepti authored
- Added: Int32x4Mul, Int32x4Min, Int32x4Max, Int32x4Equal, Int32x4NotEqual Uint32x4Min, Uint32x4Max - Fix I32x4Splat R=bbudge@chromium.org, bradnelson@chromium.org, mtrofin@chromium.org Review-Url: https://codereview.chromium.org/2719953002 Cr-Commit-Position: refs/heads/master@{#43827}
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Marja Hölttä authored
BUG=v8:5294 Change-Id: I6214c50c7d1344210a80763b066e5ec56df1265a Reviewed-on: https://chromium-review.googlesource.com/453460 Commit-Queue: Marja Hölttä <marja@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Yang Guo <yangguo@chromium.org> Cr-Commit-Position: refs/heads/master@{#43820}
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