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Commit 22aad80e authored by Bill Budge's avatar Bill Budge Committed by Commit Bot
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[ARM64] Implement WebAssembly SIMD opcodes for ARM64. 

BUG: v8:6020
Change-Id: I7280827aa9a493677253cc2fbd42be8173b55b7a
Reviewed-on: https://chromium-review.googlesource.com/534956Reviewed-by: 's avatarMartyn Capewell <martyn.capewell@arm.com>
Reviewed-by: 's avatarMircea Trofin <mtrofin@chromium.org>
Commit-Queue: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#46018}
parent 1280954d
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Showing with 1362 additions and 217 deletions
src/arm64/assembler-arm64-inl.h
View file @ 22aad80e
......@@ -16,7 +16,7 @@ namespace internal {
bool CpuFeatures::SupportsCrankshaft() { return true; }
bool CpuFeatures::SupportsWasmSimd128() { return false; }
bool CpuFeatures::SupportsWasmSimd128() { return true; }
void RelocInfo::apply(intptr_t delta) {
// On arm64 only internal references need extra work.
......
src/arm64/assembler-arm64.h
View file @ 22aad80e
......@@ -417,9 +417,13 @@ ALIAS_REGISTER(Register, wzr, w31);
// Keeps the 0 double value.
ALIAS_REGISTER(VRegister, fp_zero, d15);
// MacroAssembler fixed V Registers.
ALIAS_REGISTER(VRegister, fp_fixed1, d27);
ALIAS_REGISTER(VRegister, fp_fixed2, d28);
ALIAS_REGISTER(VRegister, fp_fixed3, d29); // same as Crankshaft scratch.
// Crankshaft double scratch register.
ALIAS_REGISTER(VRegister, crankshaft_fp_scratch, d29);
// MacroAssembler double scratch registers.
// MacroAssembler scratch V registers.
ALIAS_REGISTER(VRegister, fp_scratch, d30);
ALIAS_REGISTER(VRegister, fp_scratch1, d30);
ALIAS_REGISTER(VRegister, fp_scratch2, d31);
......
src/arm64/macro-assembler-arm64.h
View file @ 22aad80e
......@@ -2641,6 +2641,9 @@ class UseScratchRegisterScope {
Register AcquireX() { return AcquireNextAvailable(available_).X(); }
VRegister AcquireS() { return AcquireNextAvailable(availablefp_).S(); }
VRegister AcquireD() { return AcquireNextAvailable(availablefp_).D(); }
VRegister AcquireV(VectorFormat format) {
return VRegister::Create(AcquireNextAvailable(availablefp_).code(), format);
}
Register UnsafeAcquire(const Register& reg) {
return Register(UnsafeAcquire(available_, reg));
......
src/compiler/arm64/code-generator-arm64.cc
View file @ 22aad80e
This diff is collapsed.
src/compiler/arm64/instruction-codes-arm64.h
View file @ 22aad80e
......@@ -143,6 +143,8 @@ namespace compiler {
V(Arm64StrS) \
V(Arm64LdrD) \
V(Arm64StrD) \
V(Arm64LdrQ) \
V(Arm64StrQ) \
V(Arm64Ldrb) \
V(Arm64Ldrsb) \
V(Arm64Strb) \
......@@ -153,7 +155,149 @@ namespace compiler {
V(Arm64LdrW) \
V(Arm64StrW) \
V(Arm64Ldr) \
V(Arm64Str)
V(Arm64Str) \
V(Arm64F32x4Splat) \
V(Arm64F32x4ExtractLane) \
V(Arm64F32x4ReplaceLane) \
V(Arm64F32x4SConvertI32x4) \
V(Arm64F32x4UConvertI32x4) \
V(Arm64F32x4Abs) \
V(Arm64F32x4Neg) \
V(Arm64F32x4RecipApprox) \
V(Arm64F32x4RecipSqrtApprox) \
V(Arm64F32x4Add) \
V(Arm64F32x4AddHoriz) \
V(Arm64F32x4Sub) \
V(Arm64F32x4Mul) \
V(Arm64F32x4Min) \
V(Arm64F32x4Max) \
V(Arm64F32x4Eq) \
V(Arm64F32x4Ne) \
V(Arm64F32x4Lt) \
V(Arm64F32x4Le) \
V(Arm64I32x4Splat) \
V(Arm64I32x4ExtractLane) \
V(Arm64I32x4ReplaceLane) \
V(Arm64I32x4SConvertF32x4) \
V(Arm64I32x4SConvertI16x8Low) \
V(Arm64I32x4SConvertI16x8High) \
V(Arm64I32x4Neg) \
V(Arm64I32x4Shl) \
V(Arm64I32x4ShrS) \
V(Arm64I32x4Add) \
V(Arm64I32x4AddHoriz) \
V(Arm64I32x4Sub) \
V(Arm64I32x4Mul) \
V(Arm64I32x4MinS) \
V(Arm64I32x4MaxS) \
V(Arm64I32x4Eq) \
V(Arm64I32x4Ne) \
V(Arm64I32x4GtS) \
V(Arm64I32x4GeS) \
V(Arm64I32x4UConvertF32x4) \
V(Arm64I32x4UConvertI16x8Low) \
V(Arm64I32x4UConvertI16x8High) \
V(Arm64I32x4ShrU) \
V(Arm64I32x4MinU) \
V(Arm64I32x4MaxU) \
V(Arm64I32x4GtU) \
V(Arm64I32x4GeU) \
V(Arm64I16x8Splat) \
V(Arm64I16x8ExtractLane) \
V(Arm64I16x8ReplaceLane) \
V(Arm64I16x8SConvertI8x16Low) \
V(Arm64I16x8SConvertI8x16High) \
V(Arm64I16x8Neg) \
V(Arm64I16x8Shl) \
V(Arm64I16x8ShrS) \
V(Arm64I16x8SConvertI32x4) \
V(Arm64I16x8Add) \
V(Arm64I16x8AddSaturateS) \
V(Arm64I16x8AddHoriz) \
V(Arm64I16x8Sub) \
V(Arm64I16x8SubSaturateS) \
V(Arm64I16x8Mul) \
V(Arm64I16x8MinS) \
V(Arm64I16x8MaxS) \
V(Arm64I16x8Eq) \
V(Arm64I16x8Ne) \
V(Arm64I16x8GtS) \
V(Arm64I16x8GeS) \
V(Arm64I16x8UConvertI8x16Low) \
V(Arm64I16x8UConvertI8x16High) \
V(Arm64I16x8ShrU) \
V(Arm64I16x8UConvertI32x4) \
V(Arm64I16x8AddSaturateU) \
V(Arm64I16x8SubSaturateU) \
V(Arm64I16x8MinU) \
V(Arm64I16x8MaxU) \
V(Arm64I16x8GtU) \
V(Arm64I16x8GeU) \
V(Arm64I8x16Splat) \
V(Arm64I8x16ExtractLane) \
V(Arm64I8x16ReplaceLane) \
V(Arm64I8x16Neg) \
V(Arm64I8x16Shl) \
V(Arm64I8x16ShrS) \
V(Arm64I8x16SConvertI16x8) \
V(Arm64I8x16Add) \
V(Arm64I8x16AddSaturateS) \
V(Arm64I8x16Sub) \
V(Arm64I8x16SubSaturateS) \
V(Arm64I8x16Mul) \
V(Arm64I8x16MinS) \
V(Arm64I8x16MaxS) \
V(Arm64I8x16Eq) \
V(Arm64I8x16Ne) \
V(Arm64I8x16GtS) \
V(Arm64I8x16GeS) \
V(Arm64I8x16ShrU) \
V(Arm64I8x16UConvertI16x8) \
V(Arm64I8x16AddSaturateU) \
V(Arm64I8x16SubSaturateU) \
V(Arm64I8x16MinU) \
V(Arm64I8x16MaxU) \
V(Arm64I8x16GtU) \
V(Arm64I8x16GeU) \
V(Arm64S128Zero) \
V(Arm64S128And) \
V(Arm64S128Or) \
V(Arm64S128Xor) \
V(Arm64S128Not) \
V(Arm64S128Select) \
V(Arm64S32x4ZipLeft) \
V(Arm64S32x4ZipRight) \
V(Arm64S32x4UnzipLeft) \
V(Arm64S32x4UnzipRight) \
V(Arm64S32x4TransposeLeft) \
V(Arm64S32x4TransposeRight) \
V(Arm64S32x4Shuffle) \
V(Arm64S16x8ZipLeft) \
V(Arm64S16x8ZipRight) \
V(Arm64S16x8UnzipLeft) \
V(Arm64S16x8UnzipRight) \
V(Arm64S16x8TransposeLeft) \
V(Arm64S16x8TransposeRight) \
V(Arm64S8x16ZipLeft) \
V(Arm64S8x16ZipRight) \
V(Arm64S8x16UnzipLeft) \
V(Arm64S8x16UnzipRight) \
V(Arm64S8x16TransposeLeft) \
V(Arm64S8x16TransposeRight) \
V(Arm64S8x16Concat) \
V(Arm64S8x16Shuffle) \
V(Arm64S32x2Reverse) \
V(Arm64S16x4Reverse) \
V(Arm64S16x2Reverse) \
V(Arm64S8x8Reverse) \
V(Arm64S8x4Reverse) \
V(Arm64S8x2Reverse) \
V(Arm64S1x4AnyTrue) \
V(Arm64S1x4AllTrue) \
V(Arm64S1x8AnyTrue) \
V(Arm64S1x8AllTrue) \
V(Arm64S1x16AnyTrue) \
V(Arm64S1x16AllTrue)
// Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes
......
src/compiler/arm64/instruction-scheduler-arm64.cc
View file @ 22aad80e
......@@ -132,6 +132,148 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64Float64MoveU64:
case kArm64U64MoveFloat64:
case kArm64Float64SilenceNaN:
case kArm64F32x4Splat:
case kArm64F32x4ExtractLane:
case kArm64F32x4ReplaceLane:
case kArm64F32x4SConvertI32x4:
case kArm64F32x4UConvertI32x4:
case kArm64F32x4Abs:
case kArm64F32x4Neg:
case kArm64F32x4RecipApprox:
case kArm64F32x4RecipSqrtApprox:
case kArm64F32x4Add:
case kArm64F32x4AddHoriz:
case kArm64F32x4Sub:
case kArm64F32x4Mul:
case kArm64F32x4Min:
case kArm64F32x4Max:
case kArm64F32x4Eq:
case kArm64F32x4Ne:
case kArm64F32x4Lt:
case kArm64F32x4Le:
case kArm64I32x4Splat:
case kArm64I32x4ExtractLane:
case kArm64I32x4ReplaceLane:
case kArm64I32x4SConvertF32x4:
case kArm64I32x4SConvertI16x8Low:
case kArm64I32x4SConvertI16x8High:
case kArm64I32x4Neg:
case kArm64I32x4Shl:
case kArm64I32x4ShrS:
case kArm64I32x4Add:
case kArm64I32x4AddHoriz:
case kArm64I32x4Sub:
case kArm64I32x4Mul:
case kArm64I32x4MinS:
case kArm64I32x4MaxS:
case kArm64I32x4Eq:
case kArm64I32x4Ne:
case kArm64I32x4GtS:
case kArm64I32x4GeS:
case kArm64I32x4UConvertF32x4:
case kArm64I32x4UConvertI16x8Low:
case kArm64I32x4UConvertI16x8High:
case kArm64I32x4ShrU:
case kArm64I32x4MinU:
case kArm64I32x4MaxU:
case kArm64I32x4GtU:
case kArm64I32x4GeU:
case kArm64I16x8Splat:
case kArm64I16x8ExtractLane:
case kArm64I16x8ReplaceLane:
case kArm64I16x8SConvertI8x16Low:
case kArm64I16x8SConvertI8x16High:
case kArm64I16x8Neg:
case kArm64I16x8Shl:
case kArm64I16x8ShrS:
case kArm64I16x8SConvertI32x4:
case kArm64I16x8Add:
case kArm64I16x8AddSaturateS:
case kArm64I16x8AddHoriz:
case kArm64I16x8Sub:
case kArm64I16x8SubSaturateS:
case kArm64I16x8Mul:
case kArm64I16x8MinS:
case kArm64I16x8MaxS:
case kArm64I16x8Eq:
case kArm64I16x8Ne:
case kArm64I16x8GtS:
case kArm64I16x8GeS:
case kArm64I16x8UConvertI8x16Low:
case kArm64I16x8UConvertI8x16High:
case kArm64I16x8ShrU:
case kArm64I16x8UConvertI32x4:
case kArm64I16x8AddSaturateU:
case kArm64I16x8SubSaturateU:
case kArm64I16x8MinU:
case kArm64I16x8MaxU:
case kArm64I16x8GtU:
case kArm64I16x8GeU:
case kArm64I8x16Splat:
case kArm64I8x16ExtractLane:
case kArm64I8x16ReplaceLane:
case kArm64I8x16Neg:
case kArm64I8x16Shl:
case kArm64I8x16ShrS:
case kArm64I8x16SConvertI16x8:
case kArm64I8x16Add:
case kArm64I8x16AddSaturateS:
case kArm64I8x16Sub:
case kArm64I8x16SubSaturateS:
case kArm64I8x16Mul:
case kArm64I8x16MinS:
case kArm64I8x16MaxS:
case kArm64I8x16Eq:
case kArm64I8x16Ne:
case kArm64I8x16GtS:
case kArm64I8x16GeS:
case kArm64I8x16UConvertI16x8:
case kArm64I8x16AddSaturateU:
case kArm64I8x16SubSaturateU:
case kArm64I8x16ShrU:
case kArm64I8x16MinU:
case kArm64I8x16MaxU:
case kArm64I8x16GtU:
case kArm64I8x16GeU:
case kArm64S128Zero:
case kArm64S128And:
case kArm64S128Or:
case kArm64S128Xor:
case kArm64S128Not:
case kArm64S128Select:
case kArm64S32x4ZipLeft:
case kArm64S32x4ZipRight:
case kArm64S32x4UnzipLeft:
case kArm64S32x4UnzipRight:
case kArm64S32x4TransposeLeft:
case kArm64S32x4TransposeRight:
case kArm64S32x4Shuffle:
case kArm64S16x8ZipLeft:
case kArm64S16x8ZipRight:
case kArm64S16x8UnzipLeft:
case kArm64S16x8UnzipRight:
case kArm64S16x8TransposeLeft:
case kArm64S16x8TransposeRight:
case kArm64S8x16ZipLeft:
case kArm64S8x16ZipRight:
case kArm64S8x16UnzipLeft:
case kArm64S8x16UnzipRight:
case kArm64S8x16TransposeLeft:
case kArm64S8x16TransposeRight:
case kArm64S8x16Concat:
case kArm64S8x16Shuffle:
case kArm64S32x2Reverse:
case kArm64S16x4Reverse:
case kArm64S16x2Reverse:
case kArm64S8x8Reverse:
case kArm64S8x4Reverse:
case kArm64S8x2Reverse:
case kArm64S1x4AnyTrue:
case kArm64S1x4AllTrue:
case kArm64S1x8AnyTrue:
case kArm64S1x8AllTrue:
case kArm64S1x16AnyTrue:
case kArm64S1x16AllTrue:
return kNoOpcodeFlags;
case kArm64TestAndBranch32:
......@@ -142,6 +284,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64LdrS:
case kArm64LdrD:
case kArm64LdrQ:
case kArm64Ldrb:
case kArm64Ldrsb:
case kArm64Ldrh:
......@@ -158,6 +301,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArm64PokePair:
case kArm64StrS:
case kArm64StrD:
case kArm64StrQ:
case kArm64Strb:
case kArm64Strh:
case kArm64StrW:
......
src/compiler/instruction-selector.cc
View file @ 22aad80e
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test/cctest/wasm/test-run-wasm-simd.cc
View file @ 22aad80e
This diff is collapsed.
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