1. 03 Nov, 2015 1 commit
  2. 13 Oct, 2015 1 commit
  3. 04 Sep, 2015 1 commit
    • balazs.kilvady's avatar
      MIPS: Optimize simulator. · 09f41681
      balazs.kilvady authored
      The patch decreases the calls of huge switch instructions making the DecodeType*() functions to work in one phase and optimizing Instruction::InstructionType(). Speed gain in release full check is about 33% (6:13 s -> 4:09 s) and in optdebug full test is about 50% (12:29 -> 6:17)
      
      BUG=
      
      Review URL: https://codereview.chromium.org/1310883005
      
      Cr-Commit-Position: refs/heads/master@{#30596}
      09f41681
  4. 24 Aug, 2015 1 commit
  5. 17 Aug, 2015 1 commit
  6. 01 Jul, 2015 1 commit
  7. 19 Jun, 2015 2 commits
  8. 17 Jun, 2015 1 commit
  9. 08 Jun, 2015 1 commit
  10. 01 Jun, 2015 1 commit
  11. 22 May, 2015 1 commit
  12. 20 May, 2015 1 commit
    • svenpanne's avatar
      Fixed various simulator-related space leaks. · 84aa494e
      svenpanne authored
      Alas, this involved quite a bit of copy-n-paste between the
      architectures, but this is caused by the very convoluted
      relationships, lifetimes and distribution of responsibilities. This
      should really be cleaned up by moving code around and using STL maps,
      but that's not really a priority right now.
      
      Bonus: Fixed leaks in the ARM64 disassembler tests.
      
      Review URL: https://codereview.chromium.org/1132943007
      
      Cr-Commit-Position: refs/heads/master@{#28496}
      84aa494e
  13. 19 May, 2015 1 commit
  14. 14 May, 2015 2 commits
  15. 30 Apr, 2015 1 commit
  16. 14 Apr, 2015 1 commit
  17. 06 Apr, 2015 1 commit
    • dusan.milosavljevic's avatar
      MIPS: Major fixes and clean-up in asm. for instruction encoding. · 4b5af7b3
      dusan.milosavljevic authored
      - Fixed single float register type instruction en[de]coding in assembler and disassembler.
      - Added max and min instructions for r6 and corresponding tests.
      - Fixed selection instruction for boundary cases in simulator.
      - Update assembler tests to be more thorough wrt boundary cases.
      
      TEST=cctest/test-assembler-mips64/MIPS17, MIPS18
           cctest/test-disasm-mips64/Type1
           cctest/test-assembler-mips/MIPS16, MIPS17
           cctest/test-disasm-mips/Type1
      BUG=
      
      Review URL: https://codereview.chromium.org/1057323002
      
      Cr-Commit-Position: refs/heads/master@{#27601}
      4b5af7b3
  18. 30 Mar, 2015 2 commits
    • balazs.kilvady's avatar
      MIPS: [turbofan] Add backend support for float32 operations. · dd402998
      balazs.kilvady authored
      Port 8dad78cd
      
      Original commit message:
      This adds the basics necessary to support float32 operations in TurboFan.
      The actual functionality required to detect safe float32 operations will
      be added based on this later. Therefore this does not affect production
      code except for some cleanup/refactoring.
      
      In detail, this patchset contains the following features:
      - Add support for float32 operations to arm, arm64, ia32 and x64
        backends.
      - Add float32 machine operators.
      - Add support for float32 constants to simplified lowering.
      - Handle float32 representation for phis in simplified lowering.
      
      In addition, contains the following (related) cleanups:
      - Fix/unify naming of backend instructions.
      - Use AVX comparisons when available.
      - Extend ArchOpcodeField to 9 bits (required for arm64).
      - Refactor some code duplication in instruction selectors.
      
      BUG=v8:3589
      LOG=n
      
      Review URL: https://codereview.chromium.org/1046953004
      
      Cr-Commit-Position: refs/heads/master@{#27531}
      dd402998
    • dusan.milosavljevic's avatar
      MIPS: Refactor simulator and add selection instructions for r6. · f00b4e94
      dusan.milosavljevic authored
      TEST=
      BUG=
      
      Review URL: https://codereview.chromium.org/1046873004
      
      Cr-Commit-Position: refs/heads/master@{#27530}
      f00b4e94
  19. 04 Mar, 2015 1 commit
  20. 20 Jan, 2015 1 commit
  21. 20 Dec, 2014 1 commit
  22. 19 Dec, 2014 1 commit
  23. 08 Sep, 2014 1 commit
  24. 20 Aug, 2014 1 commit
  25. 13 Aug, 2014 1 commit
  26. 12 Aug, 2014 1 commit
  27. 11 Aug, 2014 4 commits
  28. 04 Aug, 2014 1 commit
  29. 31 Jul, 2014 1 commit
  30. 07 Jul, 2014 1 commit
  31. 30 Jun, 2014 1 commit
  32. 20 Jun, 2014 1 commit
  33. 03 Jun, 2014 2 commits