- 22 Nov, 2017 1 commit
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Clemens Hammacher authored
The Label class currently allows to be copied on all platforms except for arm64, where it can not be copied or moved. This allows too much though: Copying a label even on another platform than arm64 might fail if the label was linked already, because only one of the copies will be bound later, and the other will fire a DCHECK error in its destructor. This CL changes the restriction to never allow to copy construct or assign a Label, but allow move construction and move assignment on all platforms except arm64. This will allow to place Labels in containers, as will be done in Liftoff (except for arm64, where it still needs to be allocated on the heap). R=mstarzinger@chromium.org Bug: v8:6600 Change-Id: Ic1234c2d233317eed6a3d537c13faed2c701fe13 Reviewed-on: https://chromium-review.googlesource.com/783190 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#49570}
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- 13 Oct, 2017 2 commits
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Mathias Bynens authored
New code should use nullptr instead of NULL. This patch updates existing use of NULL to nullptr where applicable, making the code base more consistent. BUG=v8:6928,v8:6921 Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng Change-Id: I4687f5b96fcfd88b41fa970a2b937b4f6538777c Reviewed-on: https://chromium-review.googlesource.com/718338 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Reviewed-by:
Toon Verwaest <verwaest@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Yang Guo <yangguo@chromium.org> Cr-Commit-Position: refs/heads/master@{#48557}
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Toon Verwaest authored
Bug: v8:6921 Change-Id: I82e0d29aba237dff22dd8dfa80ddecd7fd724df3 Reviewed-on: https://chromium-review.googlesource.com/718421Reviewed-by:
Camillo Bruni <cbruni@chromium.org> Commit-Queue: Toon Verwaest <verwaest@chromium.org> Cr-Commit-Position: refs/heads/master@{#48539}
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- 07 Sep, 2017 1 commit
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Clemens Hammacher authored
Use operator== and operator!= instead. Implemented for x64, ia32, arm, arm64, mips and mips64. R=mstarzinger@chromium.org,ishell@chromium.org,jgruber@chromium.org Change-Id: Iad0f03f7f442709dcaa12d6a49a8bc4b03b9cdae Reviewed-on: https://chromium-review.googlesource.com/654857 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Igor Sheludko <ishell@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47889}
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- 06 Sep, 2017 1 commit
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Clemens Hammacher authored
Up to now, each architecture defined all Register types as structs, with lots of redundancy. An often found comment noted that they cannot be classes due to initialization order problems. As these problems are gone with C++11 constexpr constants, I now tried making Registers classes again. All register types now inherit from RegisterBase, which provides a default set of methods and named constructors (like ::from_code, code(), bit(), is_valid(), ...). This design allows to guarantee an interesting property: Each register is either valid, or it's the no_reg register. There are no other invalid registers. This is guaranteed statically by the constexpr constructor, and dynamically by ::from_code. I decided to disallow the default constructor completely, so instead of "Register reg;" you now need "Register reg = no_reg;". This makes explicit how the Register is initialized. I did this change to the x64, ia32, arm, arm64, mips and mips64 ports. Overall, code got much more compact and more safe. In theory, it should also increase performance (since the is_valid() check is simpler), but this is probably not measurable. R=mstarzinger@chromium.org Change-Id: I5ccfa4050daf4e146a557970e9d37fd3d2788d4a Reviewed-on: https://chromium-review.googlesource.com/650927Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Igor Sheludko <ishell@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#47847}
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- 16 Aug, 2017 1 commit
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Yang Guo authored
This removes: - CodeBreakIterator for FCG code. - RelocModes for debug breaks. - Code generator for debug break slots. - GC support for debug break slots. - Code flag to indicate code with debug break slots. - Builtin type DBG. - Mechanisms to replace FCG code in the debugger and LiveEdit. - Runtime entry to the debugger from debug break slots. R=bmeurer@chromium.org, rmcilroy@chromium.org, ulan@chromium.org Bug: v8:6409 Change-Id: I5662c8800e3ef1b1584ad107bfe0aae26c9d8abb Reviewed-on: https://chromium-review.googlesource.com/613263Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Commit-Queue: Yang Guo <yangguo@chromium.org> Cr-Commit-Position: refs/heads/master@{#47364}
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- 02 Aug, 2017 1 commit
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Julien Brianceau authored
Bug: chromium:750830 Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng Change-Id: Icab7b5a1c469d5e77d04df8bfca8319784e92af4 Reviewed-on: https://chromium-review.googlesource.com/595655 Commit-Queue: Julien Brianceau <jbriance@cisco.com> Reviewed-by:
Yang Guo <yangguo@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Daniel Ehrenberg <littledan@chromium.org> Cr-Commit-Position: refs/heads/master@{#47072}
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- 01 Aug, 2017 1 commit
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Ben L. Titzer authored
Register configuration data is not the same as frame configuration data. This CL moves the last remnants of register configuration into the assembler files, to be with the other register configuration macros. Next step: extract this register configuration data into platform-specific files that can be included independent of the assembler. R=mstarzinger@chromium.org Bug: Change-Id: I10933b5090be94e90e2a1442197528dfe30bb566 Reviewed-on: https://chromium-review.googlesource.com/595590 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47044}
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- 20 Jul, 2017 1 commit
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Andreas Haas authored
Apparently the name float.h causes problems on Windows when V8 is compiled with Visual Studio, see the bug description. R=clemensh@chromium.org Bug: v8:6588 Change-Id: Iaa9c1e93e62509a779f1a8ddecbb03a53981cf8a Reviewed-on: https://chromium-review.googlesource.com/578029Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Clemens Hammacher <clemensh@chromium.org> Commit-Queue: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#46791}
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- 07 Jul, 2017 1 commit
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Andreas Haas authored
This CL changes for floats what https://chromium-review.googlesource.com/c/558964/ changed for doubles. Original message: On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. New in this CL: Although src/double.h existed already, src/float.h did not exist yet. I created the file in this CL, and moved the classes Float32 and Float64 there, which already existed in src/deoptimizer.h. R=titzer@chromium.org, martyn.capewell@arm.com, v8-arm-ports@googlegroups.com BUG=v8:6564 Change-Id: I6a3f1f154af9c8cd4bb8e7e856235d3eee5e9edd Reviewed-on: https://chromium-review.googlesource.com/561009 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by:
Martyn Capewell <martyn.capewell@arm.com> Reviewed-by:
Ben Titzer <titzer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46473}
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- 06 Jul, 2017 2 commits
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Georg Neis authored
Remove all IsHeapObject/IsSmi checks from assembler and also from the macro-assembler functions that Turbofan code generation uses. Note for porters: In case it's unclear which macro-assembler functions need to be modified, it may be best to wait until I split MacroAssembler in a followup-CL, which will make that clear. Bug: v8:6048 Change-Id: Ife0735cc6f48713c9ec493faf2dac5e553d1c06b Reviewed-on: https://chromium-review.googlesource.com/561015 Commit-Queue: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46436}
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Pierre Langlois authored
Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
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- 05 Jul, 2017 1 commit
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Andreas Haas authored
On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. BUG=v8:6564 Change-Id: I062559f9a7ba8b0f560628e5c39621ca578c3e7d Reviewed-on: https://chromium-review.googlesource.com/558964 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by:
Ben Titzer <titzer@chromium.org> Reviewed-by:
Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#46418}
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- 28 Jun, 2017 1 commit
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Georg Neis authored
Bug: v8:6048 Change-Id: I055f8207d0a32b7fa0fb95961f2e0f29d1c02569 Reviewed-on: https://chromium-review.googlesource.com/548078 Commit-Queue: Georg Neis <neis@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#46300}
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- 20 Jun, 2017 1 commit
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mvstanton authored
These are no longer being used. BUG=v8:6408 Review-Url: https://codereview.chromium.org/2944013002 Cr-Commit-Position: refs/heads/master@{#46024}
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- 14 Jun, 2017 1 commit
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Pierre Langlois authored
This cleanup is the result of trying to modify the `Assembler::addrmod1` method and realising it's very easy to break it. It handles three groups of instructions with different operands and uses `r0` when a register is not used: - General case: rd, rn, (rm|rm shift #imm|rm shift rs) - Comparison instructions: rn, (rm|rm shift #imm|rm shift rs) - Move instructions rd, (rm|rm shift #imm|rm shift rs) Let's use `no_reg` instead of `r0` with explicit checks and assertions so that it's clear this method is used with multiple types of instructions. Additionaly, keep the order of operands as "rd", "rn", "rm". As drive-by fixes, I've taken the opportunity to add a few helper methods to the `Operand` class. Bug: Change-Id: If8140d804bc90dea1d3c186b3cee54297f91462a Reviewed-on: https://chromium-review.googlesource.com/531284 Commit-Queue: Georg Neis <neis@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#45949}
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- 01 Jun, 2017 1 commit
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georgia.kouveli authored
This fixes an issue with ful-codegen where code target entries for the OSR check were being incorrectly shared. We now explicitly disable sharing of code target constant pool entries for full-codegen and for calls to builtins from WASM code, using a scope. BUG=chromium:725743 Review-Url: https://codereview.chromium.org/2922433002 Cr-Commit-Position: refs/heads/master@{#45661}
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- 31 May, 2017 1 commit
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neis authored
Instead of allocating and embedding certain heap numbers into the code during code assembly, emit dummies but record the allocation requests. Later then, in Assembler::GetCode, allocate the heap numbers and patch the code by replacing the dummies with the actual objects. The RelocInfos for the embedded objects are already recorded correctly when emitting the dummies. R=jarin@chromium.org BUG=v8:6048 Review-Url: https://codereview.chromium.org/2900683002 Cr-Commit-Position: refs/heads/master@{#45635}
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- 23 May, 2017 1 commit
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georgia.kouveli authored
This patch also adds sharing of code target entries, which requires sharing the RelocInfo for those entries as well. The disassembler is also modified in order to print comments for the RelocInfo that is now shared. This improves the snapshot size for arm by about 4%. BUG= Review-Url: https://codereview.chromium.org/2869683004 Cr-Commit-Position: refs/heads/master@{#45497}
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- 16 May, 2017 1 commit
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bbudge authored
- Adds vdup.<size> Dd/Qd, Dm[i] instruction. - Adds vsli, vsri instructions. - Changes VMovExtended to use these to avoid moves to core registers. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2868603002 Cr-Commit-Position: refs/heads/master@{#45351}
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- 28 Apr, 2017 1 commit
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hpayer authored
BUG=chromium:716032 Review-Url: https://codereview.chromium.org/2842303003 Cr-Commit-Position: refs/heads/master@{#44975}
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- 24 Apr, 2017 1 commit
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bbudge authored
- Adds new F32x4AddHoriz, I32x4AddHoriz, etc. to WASM opcodes. - Implements them for ARM. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2804883008 Cr-Commit-Position: refs/heads/master@{#44812}
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- 19 Apr, 2017 1 commit
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bbudge authored
- Reserves q15 (d30,d31) as a scratch register for NEON operations. - Rewrites CodeGenerator::AssembleSwap to use it. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2827743002 Cr-Commit-Position: refs/heads/master@{#44728}
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- 13 Apr, 2017 1 commit
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georgia.kouveli authored
This option doesn't work for ARM any more. BUG= Review-Url: https://codereview.chromium.org/2816703002 Cr-Commit-Position: refs/heads/master@{#44646}
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- 10 Apr, 2017 3 commits
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Original-Commit-Position: refs/heads/master@{#44536} Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44540}
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bbudge authored
Revert of [ARM] Implement D-register versions of vzip, vuzp, and vtrn. (patchset #4 id:60001 of https://codereview.chromium.org/2797923006/ ) Reason for revert: Breaks: http://builders/V8%20Arm%20-%20debug/builds/2751 Original issue's description: > [ARM] Implement D-register versions of vzip, vuzp, and vtrn. > > LOG=N > BUG=v8:6020 > > Review-Url: https://codereview.chromium.org/2797923006 > Cr-Commit-Position: refs/heads/master@{#44536} > Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 TBR=martyn.capewell@arm.com,bmeurer@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=v8:6020 Review-Url: https://codereview.chromium.org/2810703003 Cr-Commit-Position: refs/heads/master@{#44537}
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44536}
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- 27 Mar, 2017 1 commit
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bbudge authored
- Fixes vmovl for widening 16 to 32, 32 to 64. - Adds vqmovn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2773303002 Cr-Commit-Position: refs/heads/master@{#44156}
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- 17 Mar, 2017 1 commit
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neis authored
This is a first step towards moving Turbofan code generation off the main thread. Summary of the changes: - AssemblerBase no longer has a pointer to the isolate. Instead, its constructor receives the few things that it needs from the isolate (on most architectures this is just the serializer_enabled flag). - RelocInfo no longer has a pointer to the isolate. Instead, the functions that need it take it as an argument. (There are currently still a few that implicitly access the isolate through a HeapObject.) - The MacroAssembler now explicitly holds a pointer to the isolate (before, it used to get it from the Assembler). - The jit_cookie also moved from AssemblerBase to the MacroAssemblers, since it's not used at all in the Assemblers. - A few architectures implemented parts of the Assembler with the help of a Codepatcher that is based on MacroAssembler. Since the Assembler no longer has the isolate, but the MacroAssembler still needs it, this doesn't work anymore. Instead, these Assemblers now use a new PatchingAssembler. BUG=v8:6048 Review-Url: https://codereview.chromium.org/2732273003 Cr-Commit-Position: refs/heads/master@{#43890}
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- 14 Mar, 2017 1 commit
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bbudge authored
- Implements vuzp, vtrn instructions for q-registers. - Refactors vmvn, vswp to use common unary op helper fn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2739033002 Cr-Commit-Position: refs/heads/master@{#43795}
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- 07 Mar, 2017 1 commit
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Clemens Hammacher authored
I originally needed this for the initialization of a constexpr array in the wasm lazy compile builtin, but since it's a bigger change, I now split it off as this separate CL. The style guide recommends constexpr over const. I thus apply the constexprificaton over all headers that I touched anyway. I also remove the ARM64_DEFINE_REG_STATICS hack. It was introduced when merging in arm64 support more than three years ago, and I don't see the purpose for this. Also, some #defines can now be constexpr definitions, which was not possible before according to the comment. R=bmeurer@chromium.org, mstarzinger@chromium.org, ishell@chromium.org Change-Id: I6d743b4462c347d363f99e28007bc9e8c84ae617 Reviewed-on: https://chromium-review.googlesource.com/451277Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Igor Sheludko <ishell@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#43637}
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- 02 Mar, 2017 1 commit
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bbudge authored
- Implements Select instructions using a single ARM vbsl instruction. - Renames boolean machine operators to match renamed S1xN machine types. - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM. - Implements S1xN AnyTrue, AllTrue ops for ARM. - Eliminates unused SIMD op categories in opcodes.h. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2711863002 Cr-Commit-Position: refs/heads/master@{#43556}
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- 28 Feb, 2017 1 commit
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Marja Hölttä authored
The x64 side is included in https://chromium-review.googlesource.com/c/444226/ BUG=v8:5294 Change-Id: Ie255604c5e38c72e3c2b76e1ca3557a5fde108ee Reviewed-on: https://chromium-review.googlesource.com/446394Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Yang Guo <yangguo@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/master@{#43481}
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- 21 Feb, 2017 1 commit
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bbudge authored
- Adds new machine types SimdBool4/8/16 for the different boolean vector types. - Adds a kSimdMaskRegisters flag for each platform. These are all false for now. - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle opcodes from the Boolean types. These are unlikely to be well supported natively, and can be synthesized using Select. - Changes the signature of Relational opcodes to return boolean vectors. - Changes the signature of Select opcodes to take boolean vectors. - Updates the ARM implementation of Relational and Select opcodes. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2700813002 Cr-Commit-Position: refs/heads/master@{#43348}
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- 09 Feb, 2017 1 commit
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Marja Hölttä authored
arguments.h is one of the headers including objects-inl.h. Files needing objects-inl.h used to innocently pull in debug.h, so that needs to be fixed now too. BUG=v8:5294 R=mstarzinger@chromium.org Change-Id: I8ce671c533ed757103ef9a3b0bf0a0509230fdd8 Reviewed-on: https://chromium-review.googlesource.com/439287Reviewed-by:
Yang Guo <yangguo@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/master@{#43054}
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- 01 Feb, 2017 1 commit
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bbudge authored
- Adds vqadd.s/u, vqsub.s/u for all integer lane sizes. - Refactors disassembler and simulator, using switches instead of long if-else chains. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2649323012 Cr-Commit-Position: refs/heads/master@{#42865}
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- 23 Jan, 2017 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2629223005 Cr-Commit-Position: refs/heads/master@{#42610}
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- 18 Jan, 2017 1 commit
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bbudge authored
- Refactors many FP, integer, and signed integer instructions where possible. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2639443002 Cr-Commit-Position: refs/heads/master@{#42463}
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- 16 Jan, 2017 1 commit
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bbudge authored
- Adds vmin, vmax for FP and integer vectors, both signed and unsigned. - Regularizes switching logic in disasm and simulator for special codes 4 and 6. - Factors vrecpe, vrsqrte, vrecps, vrsqrts into helper fns. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2623993006 Cr-Commit-Position: refs/heads/master@{#42385}
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- 12 Jan, 2017 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2620343002 Cr-Commit-Position: refs/heads/master@{#42273}
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