1. 22 Nov, 2017 1 commit
    • Clemens Hammacher's avatar
      Allow move semantics on Labels · eeb32224
      Clemens Hammacher authored
      The Label class currently allows to be copied on all platforms except
      for arm64, where it can not be copied or moved.
      This allows too much though:
      Copying a label even on another platform than arm64 might fail if the
      label was linked already, because only one of the copies will be bound
      later, and the other will fire a DCHECK error in its destructor.
      
      This CL changes the restriction to never allow to copy construct or
      assign a Label, but allow move construction and move assignment on all
      platforms except arm64.
      This will allow to place Labels in containers, as will be done in
      Liftoff (except for arm64, where it still needs to be allocated on the
      heap).
      
      R=mstarzinger@chromium.org
      
      Bug: v8:6600
      Change-Id: Ic1234c2d233317eed6a3d537c13faed2c701fe13
      Reviewed-on: https://chromium-review.googlesource.com/783190
      Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
      Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#49570}
      eeb32224
  2. 13 Oct, 2017 2 commits
  3. 07 Sep, 2017 1 commit
  4. 06 Sep, 2017 1 commit
    • Clemens Hammacher's avatar
      [assembler] Make Register et al. real classes · 9e995e12
      Clemens Hammacher authored
      Up to now, each architecture defined all Register types as structs,
      with lots of redundancy. An often found comment noted that they cannot
      be classes due to initialization order problems. As these problems are
      gone with C++11 constexpr constants, I now tried making Registers
      classes again.
      All register types now inherit from RegisterBase, which provides a
      default set of methods and named constructors (like ::from_code,
      code(), bit(), is_valid(), ...).
      This design allows to guarantee an interesting property: Each register
      is either valid, or it's the no_reg register. There are no other
      invalid registers. This is guaranteed statically by the constexpr
      constructor, and dynamically by ::from_code.
      
      I decided to disallow the default constructor completely, so instead of
      "Register reg;" you now need "Register reg = no_reg;". This makes
      explicit how the Register is initialized.
      
      I did this change to the x64, ia32, arm, arm64, mips and mips64 ports.
      Overall, code got much more compact and more safe. In theory, it should
      also increase performance (since the is_valid() check is simpler), but
      this is probably not measurable.
      
      R=mstarzinger@chromium.org
      
      Change-Id: I5ccfa4050daf4e146a557970e9d37fd3d2788d4a
      Reviewed-on: https://chromium-review.googlesource.com/650927Reviewed-by: 's avatarJakob Gruber <jgruber@chromium.org>
      Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
      Reviewed-by: 's avatarIgor Sheludko <ishell@chromium.org>
      Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#47847}
      9e995e12
  5. 16 Aug, 2017 1 commit
  6. 02 Aug, 2017 1 commit
  7. 01 Aug, 2017 1 commit
  8. 20 Jul, 2017 1 commit
  9. 07 Jul, 2017 1 commit
    • Andreas Haas's avatar
      [arm] Pass float immediates to vmov as uint32_t · 08688b39
      Andreas Haas authored
      This CL changes for floats what https://chromium-review.googlesource.com/c/558964/
      changed for doubles.
      
      Original message:
      On x86, signalling NaNs get converted to quiet NaNs when they get push
      on the stack and popped again. This happens in the code generation for
      arm, specifically for the vmov instruction with the immediate parameter.
      This CL replaces the vmov function in assembler-arm to take the
      immediate as a uint64_t instead of a double, to guarantee that the bit
      pattern does not change even if the parameter is a signalling NaN.
      
      New in this CL:
      Although src/double.h existed already, src/float.h did not exist yet.
      I created the file in this CL, and moved the classes Float32 and
      Float64 there, which already existed in src/deoptimizer.h.
      
      R=titzer@chromium.org, martyn.capewell@arm.com, v8-arm-ports@googlegroups.com
      
      BUG=v8:6564
      
      Change-Id: I6a3f1f154af9c8cd4bb8e7e856235d3eee5e9edd
      Reviewed-on: https://chromium-review.googlesource.com/561009
      Commit-Queue: Andreas Haas <ahaas@chromium.org>
      Reviewed-by: 's avatarMartyn Capewell <martyn.capewell@arm.com>
      Reviewed-by: 's avatarBen Titzer <titzer@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#46473}
      08688b39
  10. 06 Jul, 2017 2 commits
    • Georg Neis's avatar
      Don't dereference handles in (macro-)assembler functions used by TF. · 9b3174b2
      Georg Neis authored
      Remove all IsHeapObject/IsSmi checks from assembler and also from
      the macro-assembler functions that Turbofan code generation uses.
      
      Note for porters: In case it's unclear which macro-assembler
      functions need to be modified, it may be best to wait until I
      split MacroAssembler in a followup-CL, which will make that clear.
      
      Bug: v8:6048
      Change-Id: Ife0735cc6f48713c9ec493faf2dac5e553d1c06b
      Reviewed-on: https://chromium-review.googlesource.com/561015
      Commit-Queue: Benedikt Meurer <bmeurer@chromium.org>
      Reviewed-by: 's avatarBenedikt Meurer <bmeurer@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#46436}
      9b3174b2
    • Pierre Langlois's avatar
      [arm] Introduce UseScratchRegisterScope · 8e84b715
      Pierre Langlois authored
      Introduce a stripped down version of UseScratchRegisterScope for ARM and use it
      inside the assembler and macro-assembler. At the exception of the Call
      instructions, we now use this scope instead of using the ip register
      directly. This is inspired from how the ARM64 backend works.
      
      In general, the benefit of doing this is we can catch cases where ip is being
      used both by the caller and by the assembler. But more specifically, TurboFan
      reserves r9 as an extra scratch register because ip can already be used by the
      assembler. With this utility, we can isolate the cases in the code generator
      which need an extra register and potentially fix them, allowing us to give r9
      back to the register allocator.
      
      This patch uncovered places in the assembler where we were using ip
      unconditionally when we could have re-used the destination register instead.
      
      Bug: v8:6553
      Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78
      Reviewed-on: https://chromium-review.googlesource.com/544956
      Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
      Reviewed-by: 's avatarBenedikt Meurer <bmeurer@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#46425}
      8e84b715
  11. 05 Jul, 2017 1 commit
  12. 28 Jun, 2017 1 commit
  13. 20 Jun, 2017 1 commit
  14. 14 Jun, 2017 1 commit
    • Pierre Langlois's avatar
      [arm] Cleanup addrmod1 encoding and Operand class · 30a29fa2
      Pierre Langlois authored
      This cleanup is the result of trying to modify the `Assembler::addrmod1` method
      and realising it's very easy to break it. It handles three groups of
      instructions with different operands and uses `r0` when a register is not used:
      
      - General case:            rd, rn, (rm|rm shift #imm|rm shift rs)
      - Comparison instructions:     rn, (rm|rm shift #imm|rm shift rs)
      - Move instructions        rd,     (rm|rm shift #imm|rm shift rs)
      
      Let's use `no_reg` instead of `r0` with explicit checks and assertions so that
      it's clear this method is used with multiple types of instructions.
      Additionaly, keep the order of operands as "rd", "rn", "rm".
      
      As drive-by fixes, I've taken the opportunity to add a few helper methods to the
      `Operand` class.
      
      Bug: 
      Change-Id: If8140d804bc90dea1d3c186b3cee54297f91462a
      Reviewed-on: https://chromium-review.googlesource.com/531284
      Commit-Queue: Georg Neis <neis@chromium.org>
      Reviewed-by: 's avatarJaroslav Sevcik <jarin@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#45949}
      30a29fa2
  15. 01 Jun, 2017 1 commit
  16. 31 May, 2017 1 commit
    • neis's avatar
      [compiler] Delay allocation of code-embedded heap numbers. · 659e8f7b
      neis authored
      Instead of allocating and embedding certain heap numbers into the code
      during code assembly, emit dummies but record the allocation requests.
      Later then, in Assembler::GetCode, allocate the heap numbers and patch
      the code by replacing the dummies with the actual objects. The
      RelocInfos for the embedded objects are already recorded correctly when
      emitting the dummies.
      
      R=jarin@chromium.org
      BUG=v8:6048
      
      Review-Url: https://codereview.chromium.org/2900683002
      Cr-Commit-Position: refs/heads/master@{#45635}
      659e8f7b
  17. 23 May, 2017 1 commit
  18. 16 May, 2017 1 commit
  19. 28 Apr, 2017 1 commit
  20. 24 Apr, 2017 1 commit
  21. 19 Apr, 2017 1 commit
  22. 13 Apr, 2017 1 commit
  23. 10 Apr, 2017 3 commits
  24. 27 Mar, 2017 1 commit
  25. 17 Mar, 2017 1 commit
    • neis's avatar
      Disentangle assembler from isolate. · 94b088ca
      neis authored
      This is a first step towards moving Turbofan code generation off the main thread.
      
      Summary of the changes:
      - AssemblerBase no longer has a pointer to the isolate. Instead, its
        constructor receives the few things that it needs from the isolate (on most
        architectures this is just the serializer_enabled flag).
      - RelocInfo no longer has a pointer to the isolate. Instead, the functions
        that need it take it as an argument.  (There are currently still a few that
        implicitly access the isolate through a HeapObject.)
      - The MacroAssembler now explicitly holds a pointer to the isolate (before, it
        used to get it from the Assembler).
      - The jit_cookie also moved from AssemblerBase to the MacroAssemblers, since
        it's not used at all in the Assemblers.
      - A few architectures implemented parts of the Assembler with the help
        of a Codepatcher that is based on MacroAssembler.  Since the Assembler no
        longer has the isolate, but the MacroAssembler still needs it, this doesn't
        work anymore.  Instead, these Assemblers now use a new PatchingAssembler.
      
      BUG=v8:6048
      
      Review-Url: https://codereview.chromium.org/2732273003
      Cr-Commit-Position: refs/heads/master@{#43890}
      94b088ca
  26. 14 Mar, 2017 1 commit
  27. 07 Mar, 2017 1 commit
    • Clemens Hammacher's avatar
      [assembler] Make register definitions constexpr · e82b7ccd
      Clemens Hammacher authored
      I originally needed this for the initialization of a constexpr array in
      the wasm lazy compile builtin, but since it's a bigger change, I now
      split it off as this separate CL.
      The style guide recommends constexpr over const. I thus apply the
      constexprificaton over all headers that I touched anyway.
      
      I also remove the ARM64_DEFINE_REG_STATICS hack. It was introduced when
      merging in arm64 support more than three years ago, and I don't see the
      purpose for this.
      Also, some #defines can now be constexpr definitions, which was not
      possible before according to the comment.
      
      R=bmeurer@chromium.org, mstarzinger@chromium.org, ishell@chromium.org
      
      Change-Id: I6d743b4462c347d363f99e28007bc9e8c84ae617
      Reviewed-on: https://chromium-review.googlesource.com/451277Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
      Reviewed-by: 's avatarIgor Sheludko <ishell@chromium.org>
      Reviewed-by: 's avatarBenedikt Meurer <bmeurer@chromium.org>
      Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#43637}
      e82b7ccd
  28. 02 Mar, 2017 1 commit
    • bbudge's avatar
      Implement remaining Boolean SIMD operations on ARM. · 386e5a11
      bbudge authored
      - Implements Select instructions using a single ARM vbsl instruction.
      - Renames boolean machine operators to match renamed S1xN machine types.
      - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM.
      - Implements S1xN AnyTrue, AllTrue ops for ARM.
      - Eliminates unused SIMD op categories in opcodes.h.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2711863002
      Cr-Commit-Position: refs/heads/master@{#43556}
      386e5a11
  29. 28 Feb, 2017 1 commit
  30. 21 Feb, 2017 1 commit
    • bbudge's avatar
      [V8] Implement SIMD Boolean vector types to allow mask registers. · 9fe0b4c7
      bbudge authored
      - Adds new machine types SimdBool4/8/16 for the different boolean vector types.
      - Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
      - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
        opcodes from the Boolean types. These are unlikely to be well supported natively,
        and can be synthesized using Select.
      - Changes the signature of Relational opcodes to return boolean vectors.
      - Changes the signature of Select opcodes to take boolean vectors.
      - Updates the ARM implementation of Relational and Select opcodes.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2700813002
      Cr-Commit-Position: refs/heads/master@{#43348}
      9fe0b4c7
  31. 09 Feb, 2017 1 commit
  32. 01 Feb, 2017 1 commit
  33. 23 Jan, 2017 1 commit
  34. 18 Jan, 2017 1 commit
  35. 16 Jan, 2017 1 commit
  36. 12 Jan, 2017 1 commit