- 10 Jul, 2017 2 commits
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Georg Neis authored
Port https://chromium-review.googlesource.com/c/561015/. Bug: v8:6048 Change-Id: I887ad0651674fb1c503bea19660199eb5ab3e9ba Reviewed-on: https://chromium-review.googlesource.com/565568Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#46531}
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Ivica Bogosavljevic authored
Port 040fa06f Port 659e8f7b Bug: Change-Id: Ie08d65ff6647f8a15127a065e7224b5b5cec09a4 Reviewed-on: https://chromium-review.googlesource.com/558294 Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Reviewed-by:
Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#46525}
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- 05 Jul, 2017 1 commit
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Miran.Karic authored
The CL replaces several helper functions for memory load/store using base register and offset with one helper function that contains several optimizations. BUG= Change-Id: I187e7e882131552abd9a0b3a0070d78adefd25b6 Reviewed-on: https://chromium-review.googlesource.com/552119 Commit-Queue: Miran Karić <Miran.Karic@imgtec.com> Reviewed-by:
Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Cr-Commit-Position: refs/heads/master@{#46420}
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- 28 Jun, 2017 2 commits
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Georg Neis authored
Bug: v8:6048 Change-Id: I055f8207d0a32b7fa0fb95961f2e0f29d1c02569 Reviewed-on: https://chromium-review.googlesource.com/548078 Commit-Queue: Georg Neis <neis@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#46300}
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sreten.kovacevic authored
Changed value of kGap constexpr from 32 to 128. Old value caused debugger/debug/debug-scopes test to fail TEST=debugger/debug/debug-scopes Bug: Change-Id: Ib805b84dce342b317b6cace3196fd1a9690e9d7a Reviewed-on: https://chromium-review.googlesource.com/549928Reviewed-by:
Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com> Cr-Commit-Position: refs/heads/master@{#46273}
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- 20 Jun, 2017 1 commit
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mvstanton authored
These are no longer being used. BUG=v8:6408 Review-Url: https://codereview.chromium.org/2944013002 Cr-Commit-Position: refs/heads/master@{#46024}
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- 01 Jun, 2017 1 commit
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dusan.simicic authored
Add support for S1x4And, S1x4Or, S1x4Xor, S1x4Not, S1x4AnyTrue, S1x4AllTrue, S1x8And, S1x8Or, S1x8Xor, S1x8Not, S1x8AnyTrue, S1x8AllTrue, S1x16And, S1x16Or, S1x16Xor, S1x16Not, S1x16AnyTrue, S1x16AllTrue, SimdLoad, SimdStore operations for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2801683003 Cr-Commit-Position: refs/heads/master@{#45662}
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- 31 May, 2017 1 commit
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neis authored
Instead of allocating and embedding certain heap numbers into the code during code assembly, emit dummies but record the allocation requests. Later then, in Assembler::GetCode, allocate the heap numbers and patch the code by replacing the dummies with the actual objects. The RelocInfos for the embedded objects are already recorded correctly when emitting the dummies. R=jarin@chromium.org BUG=v8:6048 Review-Url: https://codereview.chromium.org/2900683002 Cr-Commit-Position: refs/heads/master@{#45635}
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- 10 May, 2017 1 commit
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Miran.Karic authored
Added support for DINSM and DINSU bit insertion instructions. Also fixed errors with bit extraction instructions, added disassembler tests and adjusted the code to make it more compact. BUG= TEST=cctest/test-assembler-mips/Dins cctest/test-disasm-mips/Type0 Review-Url: https://codereview.chromium.org/2871663002 Cr-Commit-Position: refs/heads/master@{#45226}
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- 28 Apr, 2017 1 commit
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hpayer authored
BUG=chromium:716032 Review-Url: https://codereview.chromium.org/2842303003 Cr-Commit-Position: refs/heads/master@{#44975}
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- 20 Apr, 2017 1 commit
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Ilija.Pavlovic authored
For MIPS64, many load/store operations from/to memory emit more then one instruction. This is the reason for moving them from assembler to macro-assembler. TEST= BUG= Review-Url: https://codereview.chromium.org/2829073002 Cr-Commit-Position: refs/heads/master@{#44746}
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- 12 Apr, 2017 1 commit
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dusan.simicic authored
Add support for F32x4Abs, F32x4Neg, F32x4RecipApprox, F32x4RecipRefine, F32x4RecipSqrtApprox, F32x4RecipSqrtRefine, F32x4Add, F32x4Sub, F32x4Mul, F32x4Max, F32x4Min, F32x4Eq, F32x4Ne, F32x4Lt, F32x4Le, I32x4SConvertF32x4, I32x4UConvertF32x4 operations for mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2778203002 Cr-Commit-Position: refs/heads/master@{#44597}
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- 27 Mar, 2017 1 commit
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dusan.simicic authored
This patch adds support for MIPS SIMD (MSA) instructions in Assembler and Decoder (disassembler) classes. MSA instructions are implemented for both mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2740123004 Cr-Commit-Position: refs/heads/master@{#44148}
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- 17 Mar, 2017 1 commit
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neis authored
This is a first step towards moving Turbofan code generation off the main thread. Summary of the changes: - AssemblerBase no longer has a pointer to the isolate. Instead, its constructor receives the few things that it needs from the isolate (on most architectures this is just the serializer_enabled flag). - RelocInfo no longer has a pointer to the isolate. Instead, the functions that need it take it as an argument. (There are currently still a few that implicitly access the isolate through a HeapObject.) - The MacroAssembler now explicitly holds a pointer to the isolate (before, it used to get it from the Assembler). - The jit_cookie also moved from AssemblerBase to the MacroAssemblers, since it's not used at all in the Assemblers. - A few architectures implemented parts of the Assembler with the help of a Codepatcher that is based on MacroAssembler. Since the Assembler no longer has the isolate, but the MacroAssembler still needs it, this doesn't work anymore. Instead, these Assemblers now use a new PatchingAssembler. BUG=v8:6048 Review-Url: https://codereview.chromium.org/2732273003 Cr-Commit-Position: refs/heads/master@{#43890}
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- 08 Mar, 2017 1 commit
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Ilija.Pavlovic authored
From declarations of bit() member functions (for structures Register, FPURegister and FPUControlRegister) are removed constexpr specificators. Build V8 will fail if function bit() is declared as a constant expression. TEST= BUG= Review-Url: https://codereview.chromium.org/2737143002 Cr-Commit-Position: refs/heads/master@{#43674}
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- 07 Mar, 2017 1 commit
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Clemens Hammacher authored
I originally needed this for the initialization of a constexpr array in the wasm lazy compile builtin, but since it's a bigger change, I now split it off as this separate CL. The style guide recommends constexpr over const. I thus apply the constexprificaton over all headers that I touched anyway. I also remove the ARM64_DEFINE_REG_STATICS hack. It was introduced when merging in arm64 support more than three years ago, and I don't see the purpose for this. Also, some #defines can now be constexpr definitions, which was not possible before according to the comment. R=bmeurer@chromium.org, mstarzinger@chromium.org, ishell@chromium.org Change-Id: I6d743b4462c347d363f99e28007bc9e8c84ae617 Reviewed-on: https://chromium-review.googlesource.com/451277Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Igor Sheludko <ishell@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#43637}
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- 21 Feb, 2017 1 commit
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bbudge authored
- Adds new machine types SimdBool4/8/16 for the different boolean vector types. - Adds a kSimdMaskRegisters flag for each platform. These are all false for now. - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle opcodes from the Boolean types. These are unlikely to be well supported natively, and can be synthesized using Select. - Changes the signature of Relational opcodes to return boolean vectors. - Changes the signature of Select opcodes to take boolean vectors. - Updates the ARM implementation of Relational and Select opcodes. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2700813002 Cr-Commit-Position: refs/heads/master@{#43348}
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- 09 Feb, 2017 1 commit
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Marja Hölttä authored
arguments.h is one of the headers including objects-inl.h. Files needing objects-inl.h used to innocently pull in debug.h, so that needs to be fixed now too. BUG=v8:5294 R=mstarzinger@chromium.org Change-Id: I8ce671c533ed757103ef9a3b0bf0a0509230fdd8 Reviewed-on: https://chromium-review.googlesource.com/439287Reviewed-by:
Yang Guo <yangguo@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/master@{#43054}
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- 07 Dec, 2016 1 commit
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dusan.simicic authored
This patch fixes jump_tables6 test for mips32r6 and mips64r6. This is regression from CL: https://crrev.com/d735f3ab12061f0a588b3f0538f9229cf747f818 BUG= Review-Url: https://codereview.chromium.org/2547033002 Cr-Commit-Position: refs/heads/master@{#41543}
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- 01 Dec, 2016 1 commit
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dusan.simicic authored
Trampolines are generated when the value of pc_offset is greater than next_buffer_check_ (attribute from Assembler class). This value shouldn't be incremented in bind_to() method when internal reference label is bound, because it is not decremented when the switch table is generated (dd() method from Assemler class). This patch fixes this problem. Regression test are also included for mips and mips64 arch. BUG= Review-Url: https://codereview.chromium.org/2530143002 Cr-Commit-Position: refs/heads/master@{#41423}
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- 25 Nov, 2016 1 commit
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marija.antic authored
Port 961a45da BUG= Review-Url: https://codereview.chromium.org/2505923002 Cr-Commit-Position: refs/heads/master@{#41284}
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- 22 Nov, 2016 1 commit
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neis authored
TBR=littledan@chromium.org BUG= Review-Url: https://codereview.chromium.org/2517143003 Cr-Commit-Position: refs/heads/master@{#41180}
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- 14 Nov, 2016 1 commit
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tebbi authored
This CL enables precise source positions for all V8 compilers. It merges compiler::SourcePosition and internal::SourcePosition to a single class used throughout the codebase. The new internal::SourcePosition instances store an id identifying an inlined function in addition to a script offset. SourcePosition::InliningId() refers to a the new table DeoptimizationInputData::InliningPositions(), which provides the following data for every inlining id: - The inlined SharedFunctionInfo as an offset into DeoptimizationInfo::LiteralArray - The SourcePosition of the inlining. Recursively, this yields the full inlining stack. Before the Code object is created, the same information can be found in CompilationInfo::inlined_functions(). If SourcePosition::InliningId() is SourcePosition::kNotInlined, it refers to the outer (non-inlined) function. So every SourcePosition has full information about its inlining stack, as long as the corresponding Code object is known. The internal represenation of a source position is a positive 64bit integer. All compilers create now appropriate source positions for inlined functions. In the case of Turbofan, this required using AstGraphBuilderWithPositions for inlined functions too. So this class is now moved to a header file. At the moment, the additional information in source positions is only used in --trace-deopt and --code-comments. The profiler needs to be updated, at the moment it gets the correct script offsets from the deopt info, but the wrong script id from the reconstructed deopt stack, which can lead to wrong outputs. This should be resolved by making the profiler use the new inlining information for deopts. I activated the inlined deoptimization tests in test-cpu-profiler.cc for Turbofan, changing them to a case where the deopt stack and the inlining position agree. It is currently still broken for other cases. The following additional changes were necessary: - The source position table (internal::SourcePositionTableBuilder etc.) supports now 64bit source positions. Encoding source positions in a single 64bit int together with the difference encoding in the source position table results in very little overhead for the inlining id, since only 12% of the source positions in Octane have a changed inlining id. - The class HPositionInfo was effectively dead code and is now removed. - SourcePosition has new printing and information facilities, including computing a full inlining stack. - I had to rename compiler/source-position.{h,cc} to compiler/compiler-source-position-table.{h,cc} to avoid clashes with the new src/source-position.cc file. - I wrote the new wrapper PodArray for ByteArray. It is a template working with any POD-type. This is used in DeoptimizationInputData::InliningPositions(). - I removed HInlinedFunctionInfo and HGraph::inlined_function_infos, because they were only used for the now obsolete Crankshaft inlining ids. - Crankshaft managed a list of inlined functions in Lithium: LChunk::inlined_functions. This is an analog structure to CompilationInfo::inlined_functions. So I removed LChunk::inlined_functions and made Crankshaft use CompilationInfo::inlined_functions instead, because this was necessary to register the offsets into the literal array in a uniform way. This is a safe change because LChunk::inlined_functions has no other uses and the functions in CompilationInfo::inlined_functions have a strictly longer lifespan, being created earlier (in Hydrogen already). BUG=v8:5432 Review-Url: https://codereview.chromium.org/2451853002 Cr-Commit-Position: refs/heads/master@{#40975}
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- 14 Sep, 2016 1 commit
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Ilija.Pavlovic authored
Implementation MADD.S. MSUB.fmt, MADDF.fmt, MSUBF.fmt and corresponding tests for assembler and disassembler. TEST=cctest/test-assembler-mips[64], cctest/test-disasm-mips[64] BUG= Review-Url: https://codereview.chromium.org/2313623002 Cr-Commit-Position: refs/heads/master@{#39415}
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- 18 Jul, 2016 1 commit
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bmeurer authored
So far TurboFan wasn't adding the deoptimization reasons for eager/soft deoptimization exits that can be used by either the DevTools profiler or the --trace-deopt flag. This adds basic support for deopt reasons on Deoptimize, DeoptimizeIf and DeoptimizeUnless nodes and threads through the reasons to the code generation. Also moves the DeoptReason to it's own file (to resolve include cycles) and drops unused reasons. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/2161543002 Cr-Commit-Position: refs/heads/master@{#37823}
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- 30 Jun, 2016 1 commit
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bbudge authored
-Defines SIMD128_REGISTERS for all platforms. -Adds Simd128 register information to RegisterConfiguration, and implements aliasing calculations. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2092103004 Cr-Commit-Position: refs/heads/master@{#37437}
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- 29 Jun, 2016 1 commit
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yangguo authored
R=mstarzinger@chromium.org BUG=v8:5117 Review-Url: https://codereview.chromium.org/2109613004 Cr-Commit-Position: refs/heads/master@{#37397}
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- 27 Jun, 2016 3 commits
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bbudge authored
Replaces ArchDefault method with Crankshaft and Turbofan getters. Eliminates IsAllocated method on Register, FloatRegister, DoubleRegister. Eliminates ToString method too. Changes call sites to access appropriate arch default RegisterConfiguration. LOG=N BUG= Review-Url: https://codereview.chromium.org/2092413002 Cr-Commit-Position: refs/heads/master@{#37297}
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ivica.bogosavljevic authored
BUG= Review-Url: https://codereview.chromium.org/2069933003 Cr-Commit-Position: refs/heads/master@{#37295}
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bbudge authored
- Add a const bool kSimpleFPAliasing variable for each platform so it's easier for the compiler to eliminate dead code. - Modify RegisterAllocator to use it. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2101473002 Cr-Commit-Position: refs/heads/master@{#37288}
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- 24 Jun, 2016 1 commit
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balazs.kilvady authored
Port fc59eb8a Original commit message: Moves between operands with different representations shouldn't happen, so don't test them. This makes it easier to modify canonicalization to differentiate between floating point types, which is needed to support floating point register aliasing for ARM and MIPS. This change also expands tests to include explicit FP moves (both register and stack slot). LOG=N BUG=v8:4124 BUG=chromium:622619 Review-Url: https://codereview.chromium.org/2090993002 Cr-Commit-Position: refs/heads/master@{#37241}
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- 13 May, 2016 1 commit
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mstarzinger authored
This makes the profiler reconstruct inlined function frames at eager deopt points from the deoptimization data. The main goal of this is to remove the last side-channel where Crankshaft communicates directly to the profiler. This is the last preparatory step towards deprecating the side-channel in question. R=yangguo@chromium.org Review-Url: https://codereview.chromium.org/1973993002 Cr-Commit-Position: refs/heads/master@{#36229}
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- 11 May, 2016 1 commit
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mstarzinger authored
This passes the inlining_id of deoptimization points via the relocation info instead of via a side-channel to the CPU profiler. This is one step towards deprecating the side-channel in question and avoid the need for performing a lookup of the return address of the deopt point. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/1956693002 Cr-Commit-Position: refs/heads/master@{#36177}
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- 09 May, 2016 1 commit
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bbudge authored
Changes some platform specific class names and uses typedefs to define FloatRegister, DoubleRegister, etc. This will be needed to do register allocation on ARM/MIPS where registers combine to form larger registers. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/1954953002 Cr-Commit-Position: refs/heads/master@{#36117}
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- 28 Apr, 2016 2 commits
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ivica.bogosavljevic authored
Implement unaligned access instructions, and tests for corresponding instruction BUG= Review-Url: https://codereview.chromium.org/1902743002 Cr-Commit-Position: refs/heads/master@{#35873}
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balazs.kilvady authored
TEST=mjsunit/asm/embenchen/zlib BUG= Review-Url: https://codereview.chromium.org/1925543003 Cr-Commit-Position: refs/heads/master@{#35854}
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- 19 Apr, 2016 1 commit
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akos.palfi authored
Port d412cfa2 BUG= Review URL: https://codereview.chromium.org/1899783003 Cr-Commit-Position: refs/heads/master@{#35613}
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- 30 Mar, 2016 1 commit
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Miran.Karic authored
Port of changes that replace JR and JALR instructions with JIC and JIALC for mips64r6. Macroassembler Jump and Call functions now use JIC and JIALC if branch delay slot is not used. Code patching is adjusted to work with new changes. Jr and Jalr macroassembler functions are removed. Other changes where mips32r6 uses jr/jalr are not done because mips64r6 uses j/jal instructions. BUG= Review URL: https://codereview.chromium.org/1830133002 Cr-Commit-Position: refs/heads/master@{#35141}
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- 10 Mar, 2016 1 commit
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balazs.kilvady authored
Make the low level assembler implementation exact and protected to disallow explicit usage. BUG= Review URL: https://codereview.chromium.org/1749263002 Cr-Commit-Position: refs/heads/master@{#34673}
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- 09 Mar, 2016 1 commit
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alan.li authored
Port 9d0cf920 Bug Descriptions: 1. We are missing drotr32 instruction 2. Ror Macro should also handle values less than zero or bigger than 31, as WASM instruction kExprI32Rol will generate shifting operands beyond [0 .. 31] range. 3. Same as Dror. 4. drotrv instruction in simulator is incorrect. BUG= TEST=cctest/test-run-wasm/Run_WasmInt32Binops,cctest/test-run-wasm/Run_WasmInt64Binops Review URL: https://codereview.chromium.org/1776623002 Cr-Commit-Position: refs/heads/master@{#34632}
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