- 13 Jul, 2022 1 commit
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Jacob Abraham authored
Implements an initial prototype of the Wasm Trace proposal. A custom section containing offsets to functions is decoded into trace instructions that are inserted into the function. In Liftoff, these are directly inserted. In TurboFan, these are added as StackEffect's, this is a work in progress. Traces will only be decoded and added when a flag is given to V8, currently "--experimental-wasm-instruction-tracing". If a trace is ever not valid or an error occurs, it is safe to just throw them away. Code Metadata Tool Convention: https://github.com/WebAssembly/tool-conventions/blob/main/CodeMetadata.md Design Doc: https://docs.google.com/document/d/1739a_LXbavBnek7pa0uqhHOCz8IJ56mn2C2Yvbssvkg/edit?usp=sharing Wasm Trace Proposal: https://github.com/WebAssembly/instrument-tracing Bug: chromium:1090122, chromium:1252113 Change-Id: Id4690d8deca482ff0e863761668ffabca159bd29 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3386604 Commit-Queue: Clemens Backes <clemensb@chromium.org> Reviewed-by: Tobias Tebbi <tebbi@chromium.org> Reviewed-by: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/main@{#81699}
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- 05 Jul, 2022 2 commits
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Maya Lekova authored
This is a reland of commit 84e078c6. It fixes an undefined behaviour and guards against NaNs in d8-test.cc. Original change's description: > [fastcall] Support EnforceRange annotation > > This CL implements checks in case EnforceRange is requested for a > given parameter by using TryTruncate* operators. It implements 2 such > truncations on x64 and arm64 - TryTruncateFloat64ToInt32 and > TryTruncateFloat64ToUint32. > > Bug: chromium:1052746 > Change-Id: I32f34d9dc1265af568cc576663620a8f7f8245f6 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3721618 > Reviewed-by: Toon Verwaest <verwaest@chromium.org> > Reviewed-by: Tobias Tebbi <tebbi@chromium.org> > Commit-Queue: Maya Lekova <mslekova@chromium.org> > Cr-Commit-Position: refs/heads/main@{#81512} Bug: chromium:1052746, chromium:1341851, chromium:1341891 Change-Id: I21e0e452c92cc93f8b06985a335f409855be0546 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3743518Reviewed-by: Toon Verwaest <verwaest@chromium.org> Commit-Queue: Maya Lekova <mslekova@chromium.org> Cr-Commit-Position: refs/heads/main@{#81529}
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Manos Koukoutos authored
This reverts commit 84e078c6. Reason for revert: https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Linux64%20UBSan/22000/overview Original change's description: > [fastcall] Support EnforceRange annotation > > This CL implements checks in case EnforceRange is requested for a > given parameter by using TryTruncate* operators. It implements 2 such > truncations on x64 and arm64 - TryTruncateFloat64ToInt32 and > TryTruncateFloat64ToUint32. > > Bug: chromium:1052746 > Change-Id: I32f34d9dc1265af568cc576663620a8f7f8245f6 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3721618 > Reviewed-by: Toon Verwaest <verwaest@chromium.org> > Reviewed-by: Tobias Tebbi <tebbi@chromium.org> > Commit-Queue: Maya Lekova <mslekova@chromium.org> > Cr-Commit-Position: refs/heads/main@{#81512} Bug: chromium:1052746 Change-Id: I2218681c7cb5d05dea6d8ac5347b19bc0070c1a6 No-Presubmit: true No-Tree-Checks: true No-Try: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3743514 Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: Manos Koukoutos <manoskouk@chromium.org> Owners-Override: Manos Koukoutos <manoskouk@chromium.org> Cr-Commit-Position: refs/heads/main@{#81513}
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- 04 Jul, 2022 1 commit
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Maya Lekova authored
This CL implements checks in case EnforceRange is requested for a given parameter by using TryTruncate* operators. It implements 2 such truncations on x64 and arm64 - TryTruncateFloat64ToInt32 and TryTruncateFloat64ToUint32. Bug: chromium:1052746 Change-Id: I32f34d9dc1265af568cc576663620a8f7f8245f6 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3721618Reviewed-by: Toon Verwaest <verwaest@chromium.org> Reviewed-by: Tobias Tebbi <tebbi@chromium.org> Commit-Queue: Maya Lekova <mslekova@chromium.org> Cr-Commit-Position: refs/heads/main@{#81512}
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- 01 Jul, 2022 1 commit
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Ilya Rezvov authored
Bug: v8:12946 Change-Id: I2c17c3258123417d616e7fc8a1521e006b758e08 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3731149Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Ilya Rezvov <irezvov@chromium.org> Cr-Commit-Position: refs/heads/main@{#81500}
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- 23 Jun, 2022 1 commit
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Ilya Rezvov authored
Bug: v8:12946 Change-Id: I3d9037a6dd940fe25f737efca49835b098d55081 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3691129Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Ilya Rezvov <irezvov@chromium.org> Cr-Commit-Position: refs/heads/main@{#81336}
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- 02 Jun, 2022 1 commit
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Ilya Rezvov authored
Prototype the instruction on the interpreter, and Arm64. Details of instruction lowerings on all relevant architectures can be found at: https://github.com/WebAssembly/relaxed-simd/issues/52 Bug: v8:12908 Change-Id: If8ffb82c38042191c67c9b5c23a231877d4f2159 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3679848Reviewed-by: Clemens Backes <clemensb@chromium.org> Commit-Queue: Ilya Rezvov <irezvov@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#80924}
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- 17 May, 2022 1 commit
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George Wort authored
Fix bug where AndNot(x, imm) and AndNot(imm, x) both become Bic(x, imm). Bug: chromium:1318092 Change-Id: I0ca2c65a1e5d64da0347c86346e7c4dc04943eff Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3613386Reviewed-by: Maya Lekova <mslekova@chromium.org> Reviewed-by: Andreas Haas <ahaas@chromium.org> Commit-Queue: George Wort <george.wort@arm.com> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#80600}
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- 13 May, 2022 1 commit
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Clemens Backes authored
Now that we require C++17 support, we can just use the standard static_assert without message, instead of our STATIC_ASSERT macro. R=leszeks@chromium.org Bug: v8:12425 Change-Id: I1d4e39c310b533bcd3a4af33d027827e6c083afe Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3647353Reviewed-by: Leszek Swirski <leszeks@chromium.org> Reviewed-by: Hannes Payer <hpayer@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/main@{#80524}
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- 11 May, 2022 1 commit
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Deepti Gandluri authored
Prototype the instruction on the interpreter, and Arm64. Details of instruction lowerings on all relevant architectures can be found at: https://github.com/WebAssembly/relaxed-simd/issues/40 Bug: v8:12284 Change-Id: Id4cb3889d94cf0bb7169ea068efe5ca68cfcbad9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3636365 Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Reviewed-by: Thibaud Michaud <thibaudm@chromium.org> Cr-Commit-Position: refs/heads/main@{#80475}
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- 05 May, 2022 2 commits
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Peter Kasting authored
This prevents ambiguity errors in C++20 due to ADL when casting types in std::, which gains std::bit_cast<>(). Bug: chromium:1284275 Change-Id: I25046d1952a9304852e481ad8b84049c6769c289 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3625838 Auto-Submit: Peter Kasting <pkasting@chromium.org> Reviewed-by: Adam Klein <adamk@chromium.org> Reviewed-by: Michael Lippautz <mlippautz@chromium.org> Commit-Queue: Adam Klein <adamk@chromium.org> Cr-Commit-Position: refs/heads/main@{#80378}
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jiepan authored
WASM only supports simd128, but modern CPUs support up to 256 bit vector register or more, we will add an experimental feature to do 256 bit re-vectorization in Turbofan pipeline, this patch add simd256 machine representation. Bug: v8:12716 Change-Id: I1e6a3f2afa0a457fca2c261216f4113d0ed5b818 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3534456Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Jie Pan <jie.pan@intel.com> Reviewed-by: Tobias Tebbi <tebbi@chromium.org> Cr-Commit-Position: refs/heads/main@{#80361}
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- 22 Apr, 2022 1 commit
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Deepti Gandluri authored
These were originally proposed as a part of the fixed-width SIMD proposal, and were then migrated to the relaxed-simd proposal which also deems these operations out of scope. Github issue: https://github.com/WebAssembly/relaxed-simd/issues/4 Bug: v8:12284 Change-Id: I65ceb6dfd25c43cf49bd7ec5b5ecd6b32cc3516a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3595970Reviewed-by: Thibaud Michaud <thibaudm@chromium.org> Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#80125}
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- 20 Apr, 2022 1 commit
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Liu Yu authored
Besides, enable float support on simulator. Port commit 098f31f4 Port commit a6da8161 As defined in https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html#_procedure_calling_convention Loongarch calling convention uses GP to pass floating-point arguments when no FP is available. Bug: v8:12614, chromium:1052746 Change-Id: I33d4115674604604b2b7e9178a306efb6000222b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3448195Reviewed-by: Maya Lekova <mslekova@chromium.org> Reviewed-by: Thibaud Michaud <thibaudm@chromium.org> Reviewed-by: Toon Verwaest <verwaest@chromium.org> Commit-Queue: Yu Liu <liuyu@loongson.cn> Auto-Submit: Yu Liu <liuyu@loongson.cn> Cr-Commit-Position: refs/heads/main@{#80062}
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- 19 Apr, 2022 1 commit
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Ilja Iskovs authored
Immediate version of the Bitclear instruction can be used for logical And with some immediates. It can also be used to implement And(x, Not(imm)) in a single instruction. This patch gives ~0.5% runtime improvement in one benchmark on Neoverse N1. Change-Id: Ia926c6746f0c252f81626c6fca21c4dfb41679d9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3160667Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/main@{#80015}
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- 15 Dec, 2021 1 commit
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Samuel Groß authored
This CL renames a number of things related to the V8 sandbox. Mainly, what used to be under V8_HEAP_SANDBOX is now under V8_SANDBOXED_EXTERNAL_POINTERS, while the previous V8 VirtualMemoryCage is now simply the V8 Sandbox: V8_VIRTUAL_MEMORY_CAGE => V8_SANDBOX V8_HEAP_SANDBOX => V8_SANDBOXED_EXTERNAL_POINTERS V8_CAGED_POINTERS => V8_SANDBOXED_POINTERS V8VirtualMemoryCage => Sandbox CagedPointer => SandboxedPointer fake cage => partially reserved sandbox src/security => src/sandbox This naming scheme should simplify things: the sandbox is now the large region of virtual address space inside which V8 mainly operates and which should be considered untrusted. Mechanisms like sandboxed pointers are then used to attempt to prevent escapes from the sandbox (i.e. corruption of memory outside of it). Furthermore, the new naming scheme avoids the confusion with the various other "cages" in V8, in particular, the VirtualMemoryCage class, by dropping that name entirely. Future sandbox features are developed under their own V8_SANDBOX_X flag, and will, once final, be merged into V8_SANDBOX. Current future features are sandboxed external pointers (using the external pointer table), and sandboxed pointers (pointers guaranteed to point into the sandbox, e.g. because they are encoded as offsets). This CL then also introduces a new build flag, v8_enable_sandbox_future, which enables all future features. Bug: v8:10391 Change-Id: I5174ea8f5ab40fb96a04af10853da735ad775c96 Cq-Include-Trybots: luci.v8.try:v8_linux64_heap_sandbox_dbg_ng,v8_linux_arm64_sim_heap_sandbox_dbg_ng Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3322981Reviewed-by: Hannes Payer <hpayer@chromium.org> Reviewed-by: Igor Sheludko <ishell@chromium.org> Reviewed-by: Michael Achenbach <machenbach@chromium.org> Reviewed-by: Toon Verwaest <verwaest@chromium.org> Commit-Queue: Samuel Groß <saelo@chromium.org> Cr-Commit-Position: refs/heads/main@{#78384}
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- 02 Dec, 2021 1 commit
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Samuel Groß authored
This CL turns references to ArrayBuffer backing stores from JSArrayBuffers, JSTypedArrays, and JSDataViews into CagedPointers when those are enabled. CagedPointers cannot generally represent nullptr, as NULL usually lies outside the cage. As such, nullptr backing stores are replaced with a special empty backing store value, which, in the current implementation, points to the end of the cage, right in front of the trailing guard regions. Due to this, it is no longer correct to compare a backing store pointer against nullptr. Bug: chromium:1218005 Change-Id: I4a6c7a82aabb4debcb6bb2babe4035ba2da8e79f Cq-Include-Trybots: luci.v8.try:v8_linux64_heap_sandbox_dbg_ng,v8_linux_arm64_sim_heap_sandbox_dbg_ng Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3244419 Commit-Queue: Samuel Groß <saelo@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Reviewed-by: Leszek Swirski <leszeks@chromium.org> Reviewed-by: Igor Sheludko <ishell@chromium.org> Cr-Commit-Position: refs/heads/main@{#78218}
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- 22 Nov, 2021 1 commit
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Ng Zhi An authored
Bug: v8:12284 Change-Id: Ia5dd40ffd1854ed8f1d6138a1bf40d8f2ca79793 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3272642Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#78025}
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- 20 Nov, 2021 1 commit
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Ng Zhi An authored
Bug: v8:12284 Change-Id: Iaa2b98029b46e5d22fac19bf2db5abd56f82670b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3272641Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#78004}
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- 18 Nov, 2021 1 commit
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Ng Zhi An authored
We move the mask to be the first input of the node in wasm-compiler.cc, this matches the order for S128Select, which makes code-gen for arm/arm64 simpler (directly lower to BSL with no more shuffle of inputs). This requires tweaking of input indices in the instruction selector for ia32/x64, but no change in codegen. Bug: v8:12284 Change-Id: I1f6f1a9fe0869509be77f77b6f54a0c636a0f92d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3272640 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#77958}
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- 29 Oct, 2021 1 commit
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Samuel Groß authored
A CagedPointer is guaranteed to point into the Virtual Memory Cage and will for example be used for ArrayBuffer backing stores when the heap sandbox is enabled. In the current implementation, CagedPointers are stored as offsets from the cage base, shifted to the left. Because the cage base address is usually available in a register, accessing a CagedPointer is very efficient, requiring only an additional shift and add operation. Bug: chromium:1218005 Change-Id: Ifc8c088e3862400672051a8c52840514dee2911f Cq-Include-Trybots: luci.v8.try:v8_linux64_heap_sandbox_dbg_ng,v8_linux_arm64_sim_heap_sandbox_dbg_ng Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3123417Reviewed-by: Toon Verwaest <verwaest@chromium.org> Reviewed-by: Igor Sheludko <ishell@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Commit-Queue: Samuel Groß <saelo@chromium.org> Cr-Commit-Position: refs/heads/main@{#77614}
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- 06 Oct, 2021 1 commit
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George Wort authored
This is a reland of 16df1dfa No changes have been made to this reland as previous commit was reverted due to a new test revealing an existing bug. This bug has now been fixed. Original change's description: > [arm64][wasm-simd] Use Cm(0) for integer comparison with 0 > > Use an immediate zero operand for integer comparison when possible. This > gives ~1% runtime performance improvement in some benchmarks on Neoverse > N1. > > Change-Id: I727a8104f8e6ca3d122d6b5b8b3d38d7bdd76c47 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158327 > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> > Cr-Commit-Position: refs/heads/main@{#76847} Change-Id: I77d6923d79407a83becbd39970c6a3f62d3a304d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3178482Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Rodolph Perfetta <rodolph.perfetta@arm.com> Cr-Commit-Position: refs/heads/main@{#77260}
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- 30 Sep, 2021 1 commit
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Marja Hölttä authored
It's confusing that we have CSA_CHECK and CSA_ASSERT and it's not clear from the names that the former works in release mode and the latter only in debug mode. Renaming CSA_ASSERT to CSA_DCHECK makes it clear what it does. So now we have CSA_CHECK and CSA_DCHECK and they're not confusing. This also renames assert() in Torque to dcheck(). Bug: v8:12244 Change-Id: I6f25d431ebc6eec7ebe326b6b8ad3a0ac5e9a108 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3190104Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Reviewed-by: Igor Sheludko <ishell@chromium.org> Reviewed-by: Shu-yu Guo <syg@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/main@{#77160}
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- 15 Sep, 2021 2 commits
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Clemens Backes authored
This reverts commit 16df1dfa. Reason for revert: Multiple failures, e.g. https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Linux/43844/overview Original change's description: > [arm64][wasm-simd] Use Cm(0) for integer comparison with 0 > > Use an immediate zero operand for integer comparison when possible. This > gives ~1% runtime performance improvement in some benchmarks on Neoverse > N1. > > Change-Id: I727a8104f8e6ca3d122d6b5b8b3d38d7bdd76c47 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158327 > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> > Cr-Commit-Position: refs/heads/main@{#76847} Tbr: zhin@chromium.org Change-Id: I7039106d885c59aecad24dd8dda4d151b8e1f022 No-Presubmit: true No-Tree-Checks: true No-Try: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3162053Reviewed-by: Clemens Backes <clemensb@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Auto-Submit: Clemens Backes <clemensb@chromium.org> Owners-Override: Leszek Swirski <leszeks@chromium.org> Cr-Commit-Position: refs/heads/main@{#76851}
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Ilja Iskovs authored
Use an immediate zero operand for integer comparison when possible. This gives ~1% runtime performance improvement in some benchmarks on Neoverse N1. Change-Id: I727a8104f8e6ca3d122d6b5b8b3d38d7bdd76c47 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158327Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/main@{#76847}
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- 09 Sep, 2021 1 commit
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Ilja Iskovs authored
Use an immediate zero operand for floating point comparison nodes when possible. This results in up to 20-25% runtime improvement in some microbenchmarks, as well as 1-1.5% runtime improvement in some real-use benchmarks on Cortex-A55 and Neoverse N1. Change-Id: I39d10871a08a037dbe8c0877d789d110476e1a58 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3133143Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/main@{#76749}
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- 08 Sep, 2021 1 commit
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Ng Zhi An authored
This is a reland of 65515ddd Fix is to use AddWithWraparound for signed additions to avoid UB. Original change's description: > [wasm-simd][arm64] Fuse add and extmul > > We can select a better instruction for add+extmul, using one of the > multiply-long-accumulate instruction. > > Define a helper struct to pattern match Add(x, OP(y, z)) and > Add(OP(x, y) z), and ensure that the matched OP is always on the > LHS, to simplify checking for matches. > > Bug: v8:11548 > Change-Id: I7ab488b262aa9f749785f973549ccd9fad72f4c8 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2826725 > Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Cr-Commit-Position: refs/heads/main@{#76708} Bug: v8:11548 Change-Id: I675ab8b78d9c6c30b82a8c96c8e7098a548c6a60 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3144379 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#76712}
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- 07 Sep, 2021 2 commits
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Zhi An Ng authored
This reverts commit 65515ddd. Reason for revert: https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Linux64%20UBSan/18117/overview Original change's description: > [wasm-simd][arm64] Fuse add and extmul > > We can select a better instruction for add+extmul, using one of the > multiply-long-accumulate instruction. > > Define a helper struct to pattern match Add(x, OP(y, z)) and > Add(OP(x, y) z), and ensure that the matched OP is always on the > LHS, to simplify checking for matches. > > Bug: v8:11548 > Change-Id: I7ab488b262aa9f749785f973549ccd9fad72f4c8 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2826725 > Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> > Commit-Queue: Zhi An Ng <zhin@chromium.org> > Cr-Commit-Position: refs/heads/main@{#76708} Bug: v8:11548 Change-Id: Ic1560616e7ee6df917fcedbb6ad139a1a9773d68 No-Presubmit: true No-Tree-Checks: true No-Try: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3144377 Auto-Submit: Zhi An Ng <zhin@chromium.org> Commit-Queue: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Cr-Commit-Position: refs/heads/main@{#76709}
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Ng Zhi An authored
We can select a better instruction for add+extmul, using one of the multiply-long-accumulate instruction. Define a helper struct to pattern match Add(x, OP(y, z)) and Add(OP(x, y) z), and ensure that the matched OP is always on the LHS, to simplify checking for matches. Bug: v8:11548 Change-Id: I7ab488b262aa9f749785f973549ccd9fad72f4c8 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2826725Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76708}
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- 26 Aug, 2021 1 commit
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Manos Koukoutos authored
When introducing LoadImmutable, we missed a couple of places where it can be used like Load. Change-Id: If02f6f1ad01d9b68ee757b38689e9f6336a6fb1d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3118545Reviewed-by: Georg Neis <neis@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Commit-Queue: Manos Koukoutos <manoskouk@chromium.org> Cr-Commit-Position: refs/heads/main@{#76512}
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- 23 Aug, 2021 1 commit
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Ilja Iskovs authored
We are running out of encoding space for opcodes on arm64. This patch merges some wasm simd opcodes of different simd types, encoding the lane size in the instruction code using LaneSizeField instead. This reduces the total number of opcodes on arm64 by 71. Bug: v8:12093 Change-Id: Ib4d96d1db1ff9b08fafd665974f3494a507da770 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3109676Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/main@{#76434}
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- 19 Aug, 2021 3 commits
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Shu-yu Guo authored
This is a reland of faf2208a Changes since revert: - Fix arm64 codegen for full pointer mode Original change's description: > [compiler] Support acq/rel accesses and atomic accesses on tagged > > This CL adds an AtomicMemoryOrder parameter to the various atomic load > and store operators. Currently only acquire release (kAcqRel) and > sequentially consistent (kSeqCst) orders are supported. > > Additionally, atomic loads and stores are extended to work with tagged > values. > > This CL is a pre-requisite for supporting atomic accesses in Torque, > which is in turn a pre-requisite for prototyping shared strings. > > Bug: v8:11995 > Change-Id: Ic77d2640e2dc7e5581b1211a054c93210c219355 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3101765 > Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Shu-yu Guo <syg@chromium.org> > Cr-Commit-Position: refs/heads/main@{#76393} Bug: v8:11995 Change-Id: I23577486334fec6b08fb3a2f5be1f6e5e16db11b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3107220Reviewed-by: Zhi An Ng <zhin@chromium.org> Reviewed-by: Adam Klein <adamk@chromium.org> Commit-Queue: Shu-yu Guo <syg@chromium.org> Cr-Commit-Position: refs/heads/main@{#76399}
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Nico Hartmann authored
This reverts commit faf2208a. Reason for revert: https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Linux64%20-%20arm64%20-%20sim%20-%20pointer%20compression/10870/overview Original change's description: > [compiler] Support acq/rel accesses and atomic accesses on tagged > > This CL adds an AtomicMemoryOrder parameter to the various atomic load > and store operators. Currently only acquire release (kAcqRel) and > sequentially consistent (kSeqCst) orders are supported. > > Additionally, atomic loads and stores are extended to work with tagged > values. > > This CL is a pre-requisite for supporting atomic accesses in Torque, > which is in turn a pre-requisite for prototyping shared strings. > > Bug: v8:11995 > Change-Id: Ic77d2640e2dc7e5581b1211a054c93210c219355 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3101765 > Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Shu-yu Guo <syg@chromium.org> > Cr-Commit-Position: refs/heads/main@{#76393} Bug: v8:11995 Change-Id: Id9936672f9e96c509b1cdf866de1ac5303996945 No-Presubmit: true No-Tree-Checks: true No-Try: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3107229Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> Commit-Queue: Nico Hartmann <nicohartmann@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Cr-Commit-Position: refs/heads/main@{#76394}
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Shu-yu Guo authored
This CL adds an AtomicMemoryOrder parameter to the various atomic load and store operators. Currently only acquire release (kAcqRel) and sequentially consistent (kSeqCst) orders are supported. Additionally, atomic loads and stores are extended to work with tagged values. This CL is a pre-requisite for supporting atomic accesses in Torque, which is in turn a pre-requisite for prototyping shared strings. Bug: v8:11995 Change-Id: Ic77d2640e2dc7e5581b1211a054c93210c219355 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3101765Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Shu-yu Guo <syg@chromium.org> Cr-Commit-Position: refs/heads/main@{#76393}
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- 17 Aug, 2021 1 commit
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Ilja Iskovs authored
This is a reland of 2261e053 This patch can now be relanded as some space was made for more opcodes: https://bugs.chromium.org/p/v8/issues/detail?id=12093 Original change's description: > [arm64][wasm] Use NEON S/Usra for Wasm SIMD add(shr(x, imm), y) > > A single AArch64 SIMD signed/unsigned Shift Right and Accumulate can be > used to implement Wasm SIMD add(shr(x, imm), y). This gives a 1-1.5% > improvement on some compute intensive Wasm benchmarks on Neoverse-N1. > > Mla and Adalp optimisations were refactored to match the style of the > added code. > > Change-Id: Id5959a31ca267e02b7d60e7ff6f942adb029b41e > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3089157 > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> > Cr-Commit-Position: refs/heads/master@{#76280} Change-Id: Idd166b7d3c960af33049bbce6e7276763c28f286 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3097284 Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Reviewed-by: Zhi An Ng <zhin@chromium.org> Reviewed-by: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#76340}
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- 13 Aug, 2021 5 commits
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Shu-yu Guo authored
To free up some ArchOpcode bits (especially for arm64), encode all atomic opcodes that are duplicated between 32bit and 64bit widths with a single opcode and encode the width in another field. Bug: v8:12093 Change-Id: Ide05e8f0b2aa877ea776851e47df60dd410deae2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3093257Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Shu-yu Guo <syg@chromium.org> Cr-Commit-Position: refs/heads/master@{#76289}
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Clemens Backes authored
This is identical to https://crrev.com/c/3094011, but for 16-bit values. We introduce another instruction to differentiate between 16->32 bit sign extensions and 16->64 bit sign extensions. R=ahaas@chromium.org, mslekova@chromium.org Bug: chromium:1239116 Change-Id: I2742e9d9c2b4a038fc7a0b1715faf8f25fa20b1f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3094012 Commit-Queue: Clemens Backes <clemensb@chromium.org> Reviewed-by: Maya Lekova <mslekova@chromium.org> Reviewed-by: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#76284}
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Clemens Backes authored
InstructionSelector::ZeroExtendsWord32ToWord64 assumes that a Load[kRepWord8|kTypeInt32] generates a zero-extended value. This assumption makes sense, but was not fulfilled by the instruction selector which emitted an "ldrsb" instruction which sign-extended to the full 64-bit register. This CL fixes that by introducing a separate "LdrsbW" instruction which is selected if we are sign-extending an 8-bit value to 32-bit. R=ahaas@chromium.org, mslekova@chromium.org CC=v8-arm-ports@googlegroups.com Bug: chromium:1239116 Change-Id: I2da1ad6062805acf5558f3e66b8db9a50e830302 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3094011 Commit-Queue: Clemens Backes <clemensb@chromium.org> Reviewed-by: Maya Lekova <mslekova@chromium.org> Reviewed-by: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#76283}
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Clemens Backes authored
This reverts commit 2261e053. Reason for revert: No issues with the CL, but it is taking the last two available opcodes on arm64 (we use 9 bits to encode it, so we are limited to 512 opcodes). We need to land a security fix which includes the addition of two opcodes. Before relanding this, we need to figure out a strategy to either reduce opcodes, or use one more bit to encode them. Original change's description: > [arm64][wasm] Use NEON S/Usra for Wasm SIMD add(shr(x, imm), y) > > A single AArch64 SIMD signed/unsigned Shift Right and Accumulate can be > used to implement Wasm SIMD add(shr(x, imm), y). This gives a 1-1.5% > improvement on some compute intensive Wasm benchmarks on Neoverse-N1. > > Mla and Adalp optimisations were refactored to match the style of the > added code. > > Change-Id: Id5959a31ca267e02b7d60e7ff6f942adb029b41e > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3089157 > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> > Cr-Commit-Position: refs/heads/master@{#76280} Change-Id: Ifad0625ed8a6b66e7a7a74da11ad7d60941207e5 No-Presubmit: true No-Tree-Checks: true No-Try: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3094014 Auto-Submit: Clemens Backes <clemensb@chromium.org> Commit-Queue: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Cr-Commit-Position: refs/heads/master@{#76282}
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Ilja Iskovs authored
A single AArch64 SIMD signed/unsigned Shift Right and Accumulate can be used to implement Wasm SIMD add(shr(x, imm), y). This gives a 1-1.5% improvement on some compute intensive Wasm benchmarks on Neoverse-N1. Mla and Adalp optimisations were refactored to match the style of the added code. Change-Id: Id5959a31ca267e02b7d60e7ff6f942adb029b41e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3089157Reviewed-by: Zhi An Ng <zhin@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#76280}
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