1. 07 Nov, 2018 1 commit
  2. 06 Nov, 2018 2 commits
  3. 30 Aug, 2018 1 commit
  4. 07 May, 2018 1 commit
  5. 03 May, 2018 1 commit
  6. 12 Jan, 2018 1 commit
  7. 23 Oct, 2017 1 commit
    • Clemens Hammacher's avatar
      [wasm] Liftoff: a baseline compiler for WebAssembly · 266e803e
      Clemens Hammacher authored
      This CL adds a first implementation of Liftoff, the new wasm baseline
      compiler, for x64 and ia32. It currently supports the most important
      i32 instructions and control instructions. Whenever it encounters an
      instruction it does not support yet, it aborts.
      In a subsequent CL, Liftoff will be called from the
      WasmCompilationUnit, falling back to Turbofan compilation if the
      baseline compiler bails out.
      
      R=titzer@chromium.org
      
      Bug: v8:6600
      Change-Id: Ifa78fb9d546dce72c241ff01a251dfa13cb31c1d
      Reviewed-on: https://chromium-review.googlesource.com/716480
      Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
      Reviewed-by: 's avatarBen Titzer <titzer@chromium.org>
      Cr-Commit-Position: refs/heads/master@{#48832}
      266e803e
  8. 20 Oct, 2017 1 commit
  9. 21 Aug, 2017 1 commit
  10. 04 Aug, 2017 1 commit
  11. 08 Jun, 2017 1 commit
    • bbudge's avatar
      [WASM] Eliminate SIMD boolean vector types. · 381f7da0
      bbudge authored
      - Eliminates b1x4, b1x8, and b1x16 as distinct WASM types.
      - All vector comparisons return v128 type.
      - Eliminates b1xN and, or, xor, not.
      - Selects take a v128 mask vector and are now bit-wise.
      - Adds a new test for Select, where mask is non-canonical (not 0's and -1's).
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2919203002
      Cr-Commit-Position: refs/heads/master@{#45795}
      381f7da0
  12. 22 May, 2017 1 commit
  13. 21 Feb, 2017 1 commit
    • bbudge's avatar
      [V8] Implement SIMD Boolean vector types to allow mask registers. · 9fe0b4c7
      bbudge authored
      - Adds new machine types SimdBool4/8/16 for the different boolean vector types.
      - Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
      - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
        opcodes from the Boolean types. These are unlikely to be well supported natively,
        and can be synthesized using Select.
      - Changes the signature of Relational opcodes to return boolean vectors.
      - Changes the signature of Select opcodes to take boolean vectors.
      - Updates the ARM implementation of Relational and Select opcodes.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2700813002
      Cr-Commit-Position: refs/heads/master@{#43348}
      9fe0b4c7
  14. 10 Feb, 2017 1 commit
  15. 03 Feb, 2017 2 commits
  16. 16 Dec, 2016 1 commit
  17. 09 Nov, 2016 1 commit
  18. 03 Nov, 2016 1 commit
    • bmeurer's avatar
      [turbofan] Improve representation selection for HeapObject checking. · 6322bf41
      bmeurer authored
      For lowering CheckHeapObject, always report TaggedPointer representation
      and let the RepresentationChanger come up with a reasonable conversion from
      whatever input representation to TaggedPointer. This way we no longer insert
      the useless ChangeSomethingToTagged and then check the result for HeapObject,
      i.e. mostly reduces the amount of useless code being generated.
      
      Note there are now two operators ChangeFloat64ToTaggedPointer and the old
      ChangeFloat64ToTagged, because their semantics different wrt. the strength
      reduction in the SimplifiedOperatorReducer.
      
      Also set the output MachineRepresentation::kTaggedPointer properly in
      SimplifiedLowering whenever we know that we produce a HeapObject.
      
      R=jarin@chromium.org
      BUG=v8:5267
      
      Review-Url: https://codereview.chromium.org/2476593002
      Cr-Commit-Position: refs/heads/master@{#40725}
      6322bf41
  19. 26 Oct, 2016 1 commit
    • bbudge's avatar
      [Turbofan] Add concept of FP register aliasing on ARM 32. · 09ab8e6a
      bbudge authored
      - Modifies RegisterConfiguration to specify complex aliasing on ARM 32.
      - Modifies RegisterAllocator to consider aliasing.
      - Modifies ParallelMove::PrepareInsertAfter to handle aliasing.
      - Modifies GapResolver to split wider register moves when interference
      with smaller moves is detected.
      - Modifies MoveOptimizer to handle aliasing.
      - Adds ARM 32 macro-assembler pseudo move instructions to handle cases where
        split moves don't correspond to actual s-registers.
      - Modifies CodeGenerator::AssembleMove and AssembleSwap to handle moves of
        different widths, and moves involving pseudo-s-registers.
      - Adds unit tests for FP operand interference checking and PrepareInsertAfter.
      - Adds more tests of FP for the move optimizer and register allocator.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2410673002
      Cr-Commit-Position: refs/heads/master@{#40597}
      09ab8e6a
  20. 17 Oct, 2016 1 commit
  21. 03 Oct, 2016 1 commit
  22. 26 Sep, 2016 1 commit
    • jgruber's avatar
      Enable component builds for fuzzers · 22606f0c
      jgruber authored
      V8 is collecting a growing amount of fuzzers, all of which take substantial
      space on the bots and in chromium build archives. This CL improves that
      situation by allowing component (shared library) builds for almost all fuzzers.
      
      The parser fuzzer is handled as an exception since it would require exporting a
      large number of additional functions.
      
      A component build results in about a 50-100x improvement in file size for each
      fuzzer (~50M-100M to around 1.1M).
      
      BUG=chromium:648864
      CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe
      
      Review-Url: https://codereview.chromium.org/2360983002
      Cr-Commit-Position: refs/heads/master@{#39709}
      22606f0c
  23. 20 Sep, 2016 1 commit
  24. 08 Sep, 2016 1 commit
  25. 30 Aug, 2016 1 commit
  26. 29 Aug, 2016 1 commit
    • mvstanton's avatar
      [Turbofan]: Use new MachineTypes in access-builder. · 56429fc1
      mvstanton authored
      Introduced MachineType::TaggedSigned() and TaggedPointer().
      
      The idea is to quit using the representational dimension of Type, and
      instead encode this information in the MachineRepresentation (itself
      lightly wrapped in MachineType, along with MachineSemantic).
      
      There are three parts to the whole change:
      
      1) Places that set the machine representation - constant nodes, loads nad
         stores, global object and native context specialization.
      
      2) Places that propagate type/representation - this is representation
         inference (aka simplified lowering). At the end of this process we
         expect to have a MachineRepresentation for every node. An interesting
         part of this is phi merging.
      
      3) Places that examine representation - WriteBarrier elimination does this.
         Currently it's looking at the Type representation dimension, but as
         a part of this change (or in a soon-to-follow change) it can simply
         examine the MachineRepresentation.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2258073002
      Cr-Commit-Position: refs/heads/master@{#38978}
      56429fc1
  27. 16 Aug, 2016 1 commit
  28. 22 Jul, 2016 1 commit
  29. 30 Jun, 2016 1 commit
  30. 29 Jun, 2016 1 commit
  31. 10 May, 2016 1 commit
    • bbudge's avatar
      [turbofan] Rename floating point register / slot methods. · 8c8600db
      bbudge authored
      Renames IsDouble* predicates to IsFP*.
      Adds specific IsFloat*, IsDouble*, and IsSimd128* predicates.
      Adds specific GetFloatRegister, GetDoubleRegister, and
      GetSimd128Register methods.
      
      This is mostly a mechanical renaming of IsDouble* to IsFP* methods.
      
      This shouldn't change code generation at all. All fp registers are still
      treated as double registers.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/1959763002
      Cr-Commit-Position: refs/heads/master@{#36146}
      8c8600db
  32. 17 Feb, 2016 1 commit
  33. 10 Dec, 2015 1 commit
    • jarin's avatar
      [turbofan] Make MachineType a pair of enums. · bb2a830d
      jarin authored
      MachineType is now a class with two enum fields:
      - MachineRepresentation
      - MachineSemantic
      
      Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
      - register allocator now uses just the representation.
      - Phi and Select nodes only refer to representations.
      
      Review URL: https://codereview.chromium.org/1513543003
      
      Cr-Commit-Position: refs/heads/master@{#32738}
      bb2a830d
  34. 03 Dec, 2015 1 commit
  35. 11 Aug, 2015 2 commits
  36. 10 Aug, 2015 1 commit
  37. 15 Jun, 2015 1 commit