- 04 Jan, 2022 1 commit
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Clemens Backes authored
For low-cost exception handling, it's important to be able to quickly drop frames from the stack until reaching the exception handler. The Intel shadow stack offers an instruction to avoid offending stack discipline, incsspq, which drops N values from the stack. This CL integrates that instruction for v8 exception handling. Bug: v8:11246 Change-Id: I908f0ab8bb3de6c36e6078e27b65132287328f2d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3289637Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/main@{#78469}
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- 14 Dec, 2021 1 commit
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Lu Yahan authored
Change-Id: I53234b6494887edd2b18e5d6b7d07675414d2e68 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3329802Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78356}
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- 14 Oct, 2021 1 commit
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Samuel Groß authored
This function tries to determine the number of virtual address bits available on the current CPU and with that the maximum size of the userspace address space. On x64, it can be implemented through CPUID. The result of this function is now used in two ways: first, it limits the maximum size of the virtual memory cage, currently to a quarter of the address space. Second, it influences the placement of fake cages, which are attempted to be placed into the lower half of the address space so that they are followed by large amounts of (hopefully) unused but addressable virtual memory in which pages can be allocated. Bug: chromium:1218005 Change-Id: I0edc5d241d899f16dbc47492fa1534b6aaa4aa13 Cq-Include-Trybots: luci.v8.try:v8_linux64_heap_sandbox_dbg_ng Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3220348 Commit-Queue: Samuel Groß <saelo@chromium.org> Reviewed-by:
Igor Sheludko <ishell@chromium.org> Cr-Commit-Position: refs/heads/main@{#77393}
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- 23 Jun, 2021 1 commit
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John Xu authored
These are the changes Cobalt currently has in V8's cpu related code. - Add missing Starboard CPU code - Replace some V8_OS_WIN with V8_TARGET_OS_WIN, they are found when cross-compiling for Linux platforms on Windows Bug: v8:10927 Change-Id: Id63ae8614cbe6fe0eb53df89060c8ca2c9969ef4 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2963803 Commit-Queue: John Xu <johnx@google.com> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#75318}
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- 29 Apr, 2021 1 commit
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Milad Fa authored
This CL adds Power10 recognition to Linux, AIX as well as IBMi. Enabled features include: MODULO FPR_GPR_MOV SIMD LWSYNC ISELECT VSX Change-Id: Ifc337e6497a3efe9697bcf03063a2b94471f96e9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2855041Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Junliang Yan <junyan@redhat.com> Reviewed-by:
Vasili Skurydzin <vasili.skurydzin@ibm.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#74279}
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- 07 Apr, 2021 1 commit
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Dan Elphick authored
ARM is often defined as a macro so this changes it to kArm and fixes other cases in the same file. Bug: v8:11384 Change-Id: Iab0149be03b3b0139e3335b91a25cb4bbb2f56e3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2808939 Auto-Submit: Dan Elphick <delphick@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#73826}
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- 31 Mar, 2021 1 commit
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Suraj Sharma authored
This CL replicates the logic in chromium.src to support timestampcounter. Based on: https://chromium-review.googlesource.com/c/chromium/src/+/1413055 Change-Id: I3a64d53f64d3850831ac3ff983daa8ebef1cb29c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2789013Reviewed-by:
Igor Sheludko <ishell@chromium.org> Commit-Queue: Suraj Sharma <surshar@microsoft.com> Cr-Commit-Position: refs/heads/master@{#73751}
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- 17 Dec, 2020 1 commit
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Zhi An Ng authored
- Add the appropriate cpuid checks to detect AVX2 in base/cpu - Add FLAG_enable_avx2 AVX2 depends on AVX support, + a cpuid check with eax=7. This is similar to chromium/src/base/cpu.cc check for AVX2. Bug: v8:11258 Change-Id: Ia547c22e51b03fec823f5e48ebb055139632c942 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2589050Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#71821}
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- 09 Jun, 2020 1 commit
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Ambroise Vincent authored
This includes the instruction opcode, its use in TF, its support in the simulator and the detection of the associated CPU feature. The instruction can be tested in the simulator with the new --sim-arm64-optional-features flag. Change-Id: I6047fa16696394fe0ced4535f7788d2c8716a18c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2222348Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Commit-Queue: Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#68261}
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- 27 Mar, 2017 1 commit
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dusan.simicic authored
This patch adds support for MIPS SIMD (MSA) instructions in Assembler and Decoder (disassembler) classes. MSA instructions are implemented for both mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2740123004 Cr-Commit-Position: refs/heads/master@{#44148}
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- 13 Jan, 2017 1 commit
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bjaideep authored
Enabled support for Power9 hardware and implemented P9 modulo instruction. R=joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, jochen@chromium.org BUG= LOG=n Review-Url: https://codereview.chromium.org/2625013002 Cr-Commit-Position: refs/heads/master@{#42341}
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- 07 Oct, 2016 1 commit
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jochen authored
Reland of land "Turn libbase into a component" (patchset #1 id:1 of https://codereview.chromium.org/2396933002/ ) Reason for revert: let's see whether it sticks this time Original issue's description: > Revert of Reland "Turn libbase into a component" (patchset #1 id:1 of https://codereview.chromium.org/2395553002/ ) > > Reason for revert: > Speculative revert due to very strange-looking win/dbg failures > which reference SignedDivisionByConstant: > > https://build.chromium.org/p/client.v8/builders/V8%20Win64%20-%20debug/builds/12736 > > Original issue's description: > > Reland "Turn libbase into a component" > > > > Original issue's description: > > > Turn libbase into a component > > > > > > This is a precondition for turning libplatform into a component > > > > > > BUG=v8:5412 > > > R=jgruber@chromium.org,machenbach@chromium.org > > > CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_ > > dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe > > > > > > Committed: https://crrev.com/614e615775f732d71b5ee94ed29737d8de687104 > > > Cr-Commit-Position: refs/heads/master@{#39950} > > > > BUG=v8:5412 > > TBR=jgruber@chromium.org,machenbach@chromium.org > > CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe;master.tryserver.chromium.mac:mac_chromium_compile_dbg_ng > > > > Committed: https://crrev.com/17cb51254cafa932025e9980b60f89f756d411cb > > Cr-Commit-Position: refs/heads/master@{#39969} > > TBR=jgruber@chromium.org,machenbach@chromium.org,jochen@chromium.org > # Skipping CQ checks because original CL landed less than 1 days ago. > NOPRESUBMIT=true > NOTREECHECKS=true > NOTRY=true > BUG=v8:5412 > > Committed: https://crrev.com/e75b9f6ed5da39e6c7a8d70cf48afbc9958afc85 > Cr-Commit-Position: refs/heads/master@{#40009} TBR=jgruber@chromium.org,machenbach@chromium.org,adamk@chromium.org # Not skipping CQ checks because original CL landed more than 1 days ago. BUG=v8:5412 Review-Url: https://codereview.chromium.org/2399323002 Cr-Commit-Position: refs/heads/master@{#40068}
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- 05 Oct, 2016 2 commits
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adamk authored
Revert of Reland "Turn libbase into a component" (patchset #1 id:1 of https://codereview.chromium.org/2395553002/ ) Reason for revert: Speculative revert due to very strange-looking win/dbg failures which reference SignedDivisionByConstant: https://build.chromium.org/p/client.v8/builders/V8%20Win64%20-%20debug/builds/12736 Original issue's description: > Reland "Turn libbase into a component" > > Original issue's description: > > Turn libbase into a component > > > > This is a precondition for turning libplatform into a component > > > > BUG=v8:5412 > > R=jgruber@chromium.org,machenbach@chromium.org > > CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_ > dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe > > > > Committed: https://crrev.com/614e615775f732d71b5ee94ed29737d8de687104 > > Cr-Commit-Position: refs/heads/master@{#39950} > > BUG=v8:5412 > TBR=jgruber@chromium.org,machenbach@chromium.org > CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe;master.tryserver.chromium.mac:mac_chromium_compile_dbg_ng > > Committed: https://crrev.com/17cb51254cafa932025e9980b60f89f756d411cb > Cr-Commit-Position: refs/heads/master@{#39969} TBR=jgruber@chromium.org,machenbach@chromium.org,jochen@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=v8:5412 Review-Url: https://codereview.chromium.org/2396933002 Cr-Commit-Position: refs/heads/master@{#40009}
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jochen authored
Original issue's description: > Turn libbase into a component > > This is a precondition for turning libplatform into a component > > BUG=v8:5412 > R=jgruber@chromium.org,machenbach@chromium.org > CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_ dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe > > Committed: https://crrev.com/614e615775f732d71b5ee94ed29737d8de687104 > Cr-Commit-Position: refs/heads/master@{#39950} BUG=v8:5412 TBR=jgruber@chromium.org,machenbach@chromium.org CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe;master.tryserver.chromium.mac:mac_chromium_compile_dbg_ng Review-Url: https://codereview.chromium.org/2395553002 Cr-Commit-Position: refs/heads/master@{#39969}
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- 04 Oct, 2016 2 commits
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machenbach authored
Revert of Turn libbase into a component (patchset #10 id:180001 of https://codereview.chromium.org/2381273002/ ) Reason for revert: Main suspect for roll block: https://codereview.chromium.org/2387403002/ Original issue's description: > Turn libbase into a component > > This is a precondition for turning libplatform into a component > > BUG=v8:5412 > R=jgruber@chromium.org,machenbach@chromium.org > CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe > > Committed: https://crrev.com/614e615775f732d71b5ee94ed29737d8de687104 > Cr-Commit-Position: refs/heads/master@{#39950} TBR=jgruber@chromium.org,jochen@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=v8:5412 Review-Url: https://codereview.chromium.org/2393603002 Cr-Commit-Position: refs/heads/master@{#39960}
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jochen authored
This is a precondition for turning libplatform into a component BUG=v8:5412 R=jgruber@chromium.org,machenbach@chromium.org CQ_INCLUDE_TRYBOTS=master.tryserver.chromium.linux:linux_chromium_compile_dbg_ng;master.tryserver.chromium.android:android_clang_dbg_recipe Review-Url: https://codereview.chromium.org/2381273002 Cr-Commit-Position: refs/heads/master@{#39950}
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- 01 Jun, 2016 1 commit
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lpy authored
We already implemented CPU time for OS X and POSIX, this path is a follow up for the implementation on Windows. BUG=v8:5000 LOG=n Review-Url: https://codereview.chromium.org/1977983003 Cr-Commit-Position: refs/heads/master@{#36656}
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- 16 Mar, 2016 2 commits
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mbrandy authored
This version does not modify arm64. R=jkummerow@chromium.org, michael_dawson@ca.ibm.com BUG= Review URL: https://codereview.chromium.org/1806893002 Cr-Commit-Position: refs/heads/master@{#34827}
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jkummerow authored
along with "[arm64] Fix i/d cache line size confusion typo" and "Fix a warning about inline asm source/destination mismatches..." which were building on it. This reverts the following commits: 8d7399f9 474e6a3d c3ff68b6 Reason for revert: We're getting a large number of crash reports from arm64 devices that are obviously related to cache flushing after code patching. Bisection results say that the problems started at revision c3ff68b6. Since I can't find a bug in that CL except for the typo that I've fixed in 474e6a3d (which made some of the crashes go away but not all of them), we have no choice but to revert the changes in order to get stability under control while we investigate. BUG=chromium:594646 LOG=n Review URL: https://codereview.chromium.org/1806853002 Cr-Commit-Position: refs/heads/master@{#34816}
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- 01 Feb, 2016 1 commit
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mbrandy authored
In the interest of generalization, this change: - Consolidates cache line size detection for all interested architectures under base::CPU (currently leveraged by only PPC and ARM64). - Differentiates between instruction vs data cache line sizes. R=rmcilroy@chromium.org, jochen@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com BUG= Review URL: https://codereview.chromium.org/1643363002 Cr-Commit-Position: refs/heads/master@{#33642}
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- 30 Sep, 2015 1 commit
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mstarzinger authored
This enables linter checking for "readability/namespace" violations during presubmit and instead marks the few known exceptions that we allow explicitly. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1371083003 Cr-Commit-Position: refs/heads/master@{#31019}
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- 20 Aug, 2015 1 commit
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sbonda authored
FlushICache should be NOP for Denver with part numbers 0x0, 0x1 and 0x2 only. Instruction cache needs to flushed for future versions of denver. Review URL: https://codereview.chromium.org/1287173004 Cr-Commit-Position: refs/heads/master@{#30262}
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- 20 Apr, 2015 1 commit
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Ross McIlroy authored
R=jochen@chromium.org Review URL: https://codereview.chromium.org/1088993003 Cr-Commit-Position: refs/heads/master@{#27937}
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- 08 Apr, 2015 1 commit
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jing.bao authored
BUG=v8:4015 LOG=n Review URL: https://codereview.chromium.org/1040603002 Cr-Commit-Position: refs/heads/master@{#27648}
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- 27 Jan, 2015 1 commit
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bmeurer authored
BUG=chromium:452033, v8:3846 LOG=y R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/878063002 Cr-Commit-Position: refs/heads/master@{#26288}
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- 20 Jan, 2015 1 commit
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weiliang.lin authored
Review URL: https://codereview.chromium.org/853703002 Cr-Commit-Position: refs/heads/master@{#26163}
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- 16 Jan, 2015 1 commit
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Sven Panne authored
Contribution of PowerPC port (continuation of 422063005). The inital patch covers the core changes to the common files. Subsequent patches will cover changes to common files to support AIX and to update the ppc directories so they are current with the changes in the rest of the project. This is based off of the GitHub repository https://github.com/andrewlow/v8ppc BUG= R=svenpanne@chromium.org, danno@chromium.org, sevnpanne@chromium.org Review URL: https://codereview.chromium.org/817143002 Cr-Commit-Position: refs/heads/master@{#26091}
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- 19 Dec, 2014 1 commit
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arajp authored
Denver supports a coherent cache mechanism. There is no need to clean the D cache and invalidate I cache. MTS has to check the translation anytime there is an I cache invalidate and this time can be saved by making FlushICache a NOP. The patch improves Octane by roughly 3-4% on Denver. Review URL: https://codereview.chromium.org/797233002 Cr-Commit-Position: refs/heads/master@{#25898}
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- 26 Nov, 2014 1 commit
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Weiliang Lin authored
R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/757503002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25509}
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- 02 Sep, 2014 1 commit
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bmeurer@chromium.org authored
Less useless creativity is best creativity! R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/526223002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23579 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 12 Aug, 2014 1 commit
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dusan.milosavljevic@imgtec.com authored
Fixing gclient runhooks failure caused by reverted commit r23050. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/467583002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23088 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 11 Aug, 2014 4 commits
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machenbach@chromium.org authored
This reverts commit r23050 for breaking runhooks on chromium. See e.g.: http://build.chromium.org/p/client.v8/builders/Chrome%20Linux%20Perf/builds/1438/steps/runhooks/logs/stdio TBR=jochen@chromium.org Review URL: https://codereview.chromium.org/458983003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23053 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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dusan.milosavljevic@imgtec.com authored
Original commit r23028 breaks ARM64 build due to conflicting FP64 symbolic constant definition in src/globals.h and src/arm64/constants-arm64.h. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/457313003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23050 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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jochen@chromium.org authored
Breaks compilation of ARM64. | Additional summary: | - Introduce fp64 fpu mode into mips32 port required for r6. | - Implement runtime detections for fpu mode and arch. revision to preserve | compatibility with previous architecture revisions. | | TEST= | BUG= | R=jkummerow@chromium.org, paul.lind@imgtec.com | | Review URL: https://codereview.chromium.org/453043002 BUG=none LOG=n TBR=jkummerow@chromium.org Review URL: https://codereview.chromium.org/458193002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23030 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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dusan.milosavljevic@imgtec.com authored
Additional summary: - Introduce fp64 fpu mode into mips32 port required for r6. - Implement runtime detections for fpu mode and arch. revision to preserve compatibility with previous architecture revisions. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/453043002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23028 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 30 Jun, 2014 1 commit
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jochen@chromium.org authored
Also split v8-core independent methods from checks.h to base/logging.h and merge v8checks with the rest of checks. The CPU::FlushICache method is moved to CpuFeatures::FlushICache RoundUp and related methods are moved to base/macros.h Remove all layering violations from src/libplatform BUG=none R=jkummerow@chromium.org LOG=n Review URL: https://codereview.chromium.org/358363002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22092 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 13 Jun, 2014 1 commit
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svenpanne@chromium.org authored
This should unbreak things on the Raspberry Pi. LOG=y R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/331803003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21835 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 03 Jun, 2014 1 commit
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jochen@chromium.org authored
- this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 26 May, 2014 1 commit
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jochen@chromium.org authored
It's really more an OS-level information, and this way the default platform doesn't depend on CPU-level details BUG=none R=yangguo@chromium.org LOG=n Review URL: https://codereview.chromium.org/300713002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21501 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 09 May, 2014 1 commit
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rmcilroy@chromium.org authored
Even although the Arm64 specification specifies that csp only needs to be aligned to 16 bytes if it is dereferenced, some implementations show poor performance. Also makes the following change: - Enable CPU support for arm64 to enable probing of cpu implementer and cpu part. - Add ALWAYS_ALIGN_CSP CpuFeature for Arm64 and set it based on runtime probing of the cpu imp - Rename PrepareForPush and PrepareForPop to PushPreamble and PopPostamble and move PopPostabl Original Review URL: https://codereview.chromium.org/264773004 R=ulan@chromium.org Review URL: https://codereview.chromium.org/271543004 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21221 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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