[cleanup] Change base::CPU to use kCamelCase

ARM is often defined as a macro so this changes it to kArm and fixes
other cases in the same file.

Bug: v8:11384
Change-Id: Iab0149be03b3b0139e3335b91a25cb4bbb2f56e3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2808939
Auto-Submit: Dan Elphick <delphick@chromium.org>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#73826}

src/base/cpu.cc

@@ -413,8 +413,8 @@ CPU::CPU()
       architecture_(0),
       variant_(-1),
       part_(0),
-      icache_line_size_(UNKNOWN_CACHE_LINE_SIZE),
-      dcache_line_size_(UNKNOWN_CACHE_LINE_SIZE),
+      icache_line_size_(kUnknownCacheLineSize),
+      dcache_line_size_(kUnknownCacheLineSize),
       has_fpu_(false),
       has_cmov_(false),
       has_sahf_(false),
@@ -805,40 +805,40 @@ CPU::CPU()
   part_ = -1;
   if (auxv_cpu_type) {
     if (strcmp(auxv_cpu_type, "power9") == 0) {
-      part_ = PPC_POWER9;
+      part_ = kPPCPower9;
     } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-      part_ = PPC_POWER8;
+      part_ = kPPCPower8;
     } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-      part_ = PPC_POWER7;
+      part_ = kPPCPower7;
     } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-      part_ = PPC_POWER6;
+      part_ = kPPCPower6;
     } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-      part_ = PPC_POWER5;
+      part_ = kPPCPower5;
     } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-      part_ = PPC_G5;
+      part_ = kPPCG5;
     } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-      part_ = PPC_G4;
+      part_ = kPPCG4;
     } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-      part_ = PPC_PA6T;
+      part_ = kPPCPA6T;
     }
   }
 
 #elif V8_OS_AIX
   switch (_system_configuration.implementation) {
     case POWER_9:
-      part_ = PPC_POWER9;
+      part_ = kPPCPower9;
       break;
     case POWER_8:
-      part_ = PPC_POWER8;
+      part_ = kPPCPower8;
       break;
     case POWER_7:
-      part_ = PPC_POWER7;
+      part_ = kPPCPower7;
       break;
     case POWER_6:
-      part_ = PPC_POWER6;
+      part_ = kPPCPower6;
       break;
     case POWER_5:
-      part_ = PPC_POWER5;
+      part_ = kPPCPower5;
       break;
   }
 #endif  // V8_OS_AIX

src/base/cpu.h

@@ -44,42 +44,42 @@ class V8_BASE_EXPORT CPU final {
 
   // arm implementer/part information
   int implementer() const { return implementer_; }
-  static const int ARM = 0x41;
-  static const int NVIDIA = 0x4e;
-  static const int QUALCOMM = 0x51;
+  static const int kArm = 0x41;
+  static const int kNvidia = 0x4e;
+  static const int kQualcomm = 0x51;
   int architecture() const { return architecture_; }
   int variant() const { return variant_; }
-  static const int NVIDIA_DENVER = 0x0;
+  static const int kNvidiaDenver = 0x0;
   int part() const { return part_; }
 
   // ARM-specific part codes
-  static const int ARM_CORTEX_A5 = 0xc05;
-  static const int ARM_CORTEX_A7 = 0xc07;
-  static const int ARM_CORTEX_A8 = 0xc08;
-  static const int ARM_CORTEX_A9 = 0xc09;
-  static const int ARM_CORTEX_A12 = 0xc0c;
-  static const int ARM_CORTEX_A15 = 0xc0f;
+  static const int kArmCortexA5 = 0xc05;
+  static const int kArmCortexA7 = 0xc07;
+  static const int kArmCortexA8 = 0xc08;
+  static const int kArmCortexA9 = 0xc09;
+  static const int kArmCortexA12 = 0xc0c;
+  static const int kArmCortexA15 = 0xc0f;
 
   // Denver-specific part code
-  static const int NVIDIA_DENVER_V10 = 0x002;
+  static const int kNvidiaDenverV10 = 0x002;
 
   // PPC-specific part codes
   enum {
-    PPC_POWER5,
-    PPC_POWER6,
-    PPC_POWER7,
-    PPC_POWER8,
-    PPC_POWER9,
-    PPC_G4,
-    PPC_G5,
-    PPC_PA6T
+    kPPCPower5,
+    kPPCPower6,
+    kPPCPower7,
+    kPPCPower8,
+    kPPCPower9,
+    kPPCG4,
+    kPPCG5,
+    kPPCPA6T
   };
 
   // General features
   bool has_fpu() const { return has_fpu_; }
   int icache_line_size() const { return icache_line_size_; }
   int dcache_line_size() const { return dcache_line_size_; }
-  static const int UNKNOWN_CACHE_LINE_SIZE = 0;
+  static const int kUnknownCacheLineSize = 0;
 
   // x86 features
   bool has_cmov() const { return has_cmov_; }

src/codegen/arm/assembler-arm.cc

@@ -241,9 +241,9 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Additional tuning options.
 
   // ARM Cortex-A9 and Cortex-A5 have 32 byte cachelines.
-  if (cpu.implementer() == base::CPU::ARM &&
-      (cpu.part() == base::CPU::ARM_CORTEX_A5 ||
-       cpu.part() == base::CPU::ARM_CORTEX_A9)) {
+  if (cpu.implementer() == base::CPU::kArm &&
+      (cpu.part() == base::CPU::kArmCortexA5 ||
+       cpu.part() == base::CPU::kArmCortexA9)) {
     dcache_line_size_ = 32;
   }
 #endif

src/codegen/ppc/assembler-ppc.cc

@@ -71,37 +71,37 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
 #ifndef USE_SIMULATOR
   // Probe for additional features at runtime.
   base::CPU cpu;
-  if (cpu.part() == base::CPU::PPC_POWER9) {
+  if (cpu.part() == base::CPU::kPPCPower9) {
     supported_ |= (1u << MODULO);
   }
 #if V8_TARGET_ARCH_PPC64
-  if (cpu.part() == base::CPU::PPC_POWER8 ||
-      cpu.part() == base::CPU::PPC_POWER9) {
+  if (cpu.part() == base::CPU::kPPCPower8 ||
+      cpu.part() == base::CPU::kPPCPower9) {
     supported_ |= (1u << FPR_GPR_MOV);
   }
   // V8 PPC Simd implementations need P9 at a minimum.
-  if (cpu.part() == base::CPU::PPC_POWER9) {
+  if (cpu.part() == base::CPU::kPPCPower9) {
     supported_ |= (1u << SIMD);
   }
 #endif
-  if (cpu.part() == base::CPU::PPC_POWER6 ||
-      cpu.part() == base::CPU::PPC_POWER7 ||
-      cpu.part() == base::CPU::PPC_POWER8 ||
-      cpu.part() == base::CPU::PPC_POWER9) {
+  if (cpu.part() == base::CPU::kPPCPower6 ||
+      cpu.part() == base::CPU::kPPCPower7 ||
+      cpu.part() == base::CPU::kPPCPower8 ||
+      cpu.part() == base::CPU::kPPCPower9) {
     supported_ |= (1u << LWSYNC);
   }
-  if (cpu.part() == base::CPU::PPC_POWER7 ||
-      cpu.part() == base::CPU::PPC_POWER8 ||
-      cpu.part() == base::CPU::PPC_POWER9) {
+  if (cpu.part() == base::CPU::kPPCPower7 ||
+      cpu.part() == base::CPU::kPPCPower8 ||
+      cpu.part() == base::CPU::kPPCPower9) {
     supported_ |= (1u << ISELECT);
     supported_ |= (1u << VSX);
   }
 #if V8_OS_LINUX
-  if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
+  if (!(cpu.part() == base::CPU::kPPCG5 || cpu.part() == base::CPU::kPPCG4)) {
     // Assume support
     supported_ |= (1u << FPU);
   }
-  if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
+  if (cpu.icache_line_size() != base::CPU::kUnknownCacheLineSize) {
     icache_line_size_ = cpu.icache_line_size();
   }
 #elif V8_OS_AIX