[riscv64] Implement cpu probe

Change-Id: I53234b6494887edd2b18e5d6b7d07675414d2e68
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3329802Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#78356}

src/base/cpu.cc

@@ -85,7 +85,7 @@ static V8_INLINE void __cpuid(int cpu_info[4], int info_type) {
 #endif  // !V8_LIBC_MSVCRT
 
 #elif V8_HOST_ARCH_ARM || V8_HOST_ARCH_ARM64 || V8_HOST_ARCH_MIPS || \
-    V8_HOST_ARCH_MIPS64
+    V8_HOST_ARCH_MIPS64 || V8_HOST_ARCH_RISCV64
 
 #if V8_OS_LINUX
 
@@ -354,7 +354,7 @@ static bool HasListItem(const char* list, const char* item) {
 #endif  // V8_OS_LINUX
 
 #endif  // V8_HOST_ARCH_ARM || V8_HOST_ARCH_ARM64 ||
-        // V8_HOST_ARCH_MIPS || V8_HOST_ARCH_MIPS64
+        // V8_HOST_ARCH_MIPS || V8_HOST_ARCH_MIPS64 || V8_HOST_ARCH_RISCV64
 
 #if defined(V8_OS_STARBOARD)
 
@@ -444,7 +444,8 @@ CPU::CPU()
       is_fp64_mode_(false),
       has_non_stop_time_stamp_counter_(false),
       is_running_in_vm_(false),
-      has_msa_(false) {
+      has_msa_(false),
+      has_rvv_(false) {
   memcpy(vendor_, "Unknown", 8);
 
 #if defined(V8_OS_STARBOARD)
@@ -854,7 +855,19 @@ CPU::CPU()
   }
 #endif  // V8_OS_AIX
 #endif  // !USE_SIMULATOR
-#endif  // V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
+
+#elif V8_HOST_ARCH_RISCV64
+  CPUInfo cpu_info;
+  char* features = cpu_info.ExtractField("isa");
+
+  if (HasListItem(features, "rv64imafdc")) {
+    has_fpu_ = true;
+  }
+  if (HasListItem(features, "rv64imafdcv")) {
+    has_fpu_ = true;
+    has_rvv_ = true;
+  }
+#endif  // V8_HOST_ARCH_RISCV64
 }
 
 }  // namespace base

src/base/cpu.h

@@ -127,6 +127,9 @@ class V8_BASE_EXPORT CPU final {
   bool is_fp64_mode() const { return is_fp64_mode_; }
   bool has_msa() const { return has_msa_; }
 
+  // riscv features
+  bool has_rvv() const { return has_rvv_; }
+
  private:
 #if defined(V8_OS_STARBOARD)
   bool StarboardDetectCPU();
@@ -175,6 +178,7 @@ class V8_BASE_EXPORT CPU final {
   bool has_non_stop_time_stamp_counter_;
   bool is_running_in_vm_;
   bool has_msa_;
+  bool has_rvv_;
 };
 
 }  // namespace base

src/codegen/riscv64/assembler-riscv64.cc

@@ -57,9 +57,9 @@ static unsigned CpuFeaturesImpliedByCompiler() {
   answer |= 1u << FPU;
 #endif  // def CAN_USE_FPU_INSTRUCTIONS
 
-#ifdef CAN_USE_RVV_INSTRUCTIONS
+#if (defined CAN_USE_RVV_INSTRUCTIONS) && (defined USE_SIMULATOR)
   answer |= 1u << RISCV_SIMD;
-#endif  // def CAN_USE_RVV_INSTRUCTIONS
+#endif  // def CAN_USE_RVV_INSTRUCTIONS && USE_SIMULATOR
   return answer;
 }
 
@@ -72,6 +72,7 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Probe for additional features at runtime.
   base::CPU cpu;
   if (cpu.has_fpu()) supported_ |= 1u << FPU;
+  if (cpu.has_rvv()) supported_ |= 1u << RISCV_SIMD;
   // Set a static value on whether SIMD is supported.
   // This variable is only used for certain archs to query SupportWasmSimd128()
   // at runtime in builtins using an extern ref. Other callers should use

test/cctest/test-assembler-riscv64.cc

@@ -2247,6 +2247,7 @@ UTEST_RVV_VF_VV_FORM_WITH_OP(vfdiv_vv, ARRAY_FLOAT, /)
 // between vectors
 #define UTEST_RVV_FMA_VV_FORM_WITH_RES(instr_name, array, expect_res)        \
   TEST(RISCV_UTEST_##instr_name) {                                           \
+    if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;                       \
     CcTest::InitializeVM();                                                  \
     auto fn = [](MacroAssembler& assm) {                                     \
       __ VU.set(t0, VSew::E32, Vlmul::m1);                                   \
@@ -2271,6 +2272,7 @@ UTEST_RVV_VF_VV_FORM_WITH_OP(vfdiv_vv, ARRAY_FLOAT, /)
 // between vectors and scalar
 #define UTEST_RVV_FMA_VF_FORM_WITH_RES(instr_name, array, expect_res)        \
   TEST(RISCV_UTEST_##instr_name) {                                           \
+    if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;                       \
     CcTest::InitializeVM();                                                  \
     auto fn = [](MacroAssembler& assm) {                                     \
       __ VU.set(t0, VSew::E32, Vlmul::m1);                                   \
@@ -2362,6 +2364,7 @@ static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift) {
 
 #define UTEST_RVV_VNCLIP_E32M2_E16M1(instr_name, sign)                       \
   TEST(RISCV_UTEST_##instr_name##_E32M2_E16M1) {                             \
+    if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;                       \
     constexpr RoundingMode vxrm = RNE;                                       \
     CcTest::InitializeVM();                                                  \
     Isolate* isolate = CcTest::i_isolate();                                  \
@@ -2401,6 +2404,7 @@ UTEST_RVV_VNCLIP_E32M2_E16M1(vnclip_vi, )
 #define UTEST_RVV_VI_VIE_FORM_WITH_RES(instr_name, type, width, frac_width, \
                                        array, expect_res)                   \
   TEST(RISCV_UTEST_##instr_name##_##width##_##frac_width) {                 \
+    if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;                      \
     constexpr uint32_t vlen = 128;                                          \
     constexpr uint32_t n = vlen / width;                                    \
     CcTest::InitializeVM();                                                 \
@@ -2456,6 +2460,7 @@ UTEST_RVV_VI_VIE_FORM_WITH_RES(vsext_vf2, int16_t, 16, 8, ARRAY(int8_t),
 #define UTEST_RVV_VP_VS_VI_FORM_WITH_RES(instr_name, type, width, array, \
                                          expect_res)                     \
   TEST(RISCV_UTEST_##instr_name##_##type) {                              \
+    if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;                   \
     constexpr uint32_t vlen = 128;                                       \
     constexpr uint32_t n = vlen / width;                                 \
     CcTest::InitializeVM();                                              \
@@ -2496,7 +2501,6 @@ UTEST_RVV_VP_VS_VI_FORM_WITH_RES(vslidedown_vi, uint8_t, 8, ARRAY(uint8_t),
 
 #undef UTEST_RVV_VP_VS_VI_FORM_WITH_RES
 #undef ARRAY
-
 #undef __
 
 }  // namespace internal