disasm-x64.cc 72.2 KB
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// Copyright 2011 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
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#include <assert.h>
#include <stdarg.h>
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#include <stdio.h>
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#if V8_TARGET_ARCH_X64
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#include "src/base/lazy-instance.h"
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#include "src/disasm.h"
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namespace disasm {

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enum OperandType {
  UNSET_OP_ORDER = 0,
  // Operand size decides between 16, 32 and 64 bit operands.
  REG_OPER_OP_ORDER = 1,  // Register destination, operand source.
  OPER_REG_OP_ORDER = 2,  // Operand destination, register source.
  // Fixed 8-bit operands.
  BYTE_SIZE_OPERAND_FLAG = 4,
  BYTE_REG_OPER_OP_ORDER = REG_OPER_OP_ORDER | BYTE_SIZE_OPERAND_FLAG,
  BYTE_OPER_REG_OP_ORDER = OPER_REG_OP_ORDER | BYTE_SIZE_OPERAND_FLAG
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};

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//------------------------------------------------------------------
// Tables
//------------------------------------------------------------------
struct ByteMnemonic {
  int b;  // -1 terminates, otherwise must be in range (0..255)
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  OperandType op_order_;
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  const char* mnem;
};


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static const ByteMnemonic two_operands_instr[] = {
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  { 0x00, BYTE_OPER_REG_OP_ORDER, "add" },
  { 0x01, OPER_REG_OP_ORDER,      "add" },
  { 0x02, BYTE_REG_OPER_OP_ORDER, "add" },
  { 0x03, REG_OPER_OP_ORDER,      "add" },
  { 0x08, BYTE_OPER_REG_OP_ORDER, "or" },
  { 0x09, OPER_REG_OP_ORDER,      "or" },
  { 0x0A, BYTE_REG_OPER_OP_ORDER, "or" },
  { 0x0B, REG_OPER_OP_ORDER,      "or" },
  { 0x10, BYTE_OPER_REG_OP_ORDER, "adc" },
  { 0x11, OPER_REG_OP_ORDER,      "adc" },
  { 0x12, BYTE_REG_OPER_OP_ORDER, "adc" },
  { 0x13, REG_OPER_OP_ORDER,      "adc" },
  { 0x18, BYTE_OPER_REG_OP_ORDER, "sbb" },
  { 0x19, OPER_REG_OP_ORDER,      "sbb" },
  { 0x1A, BYTE_REG_OPER_OP_ORDER, "sbb" },
  { 0x1B, REG_OPER_OP_ORDER,      "sbb" },
  { 0x20, BYTE_OPER_REG_OP_ORDER, "and" },
  { 0x21, OPER_REG_OP_ORDER,      "and" },
  { 0x22, BYTE_REG_OPER_OP_ORDER, "and" },
  { 0x23, REG_OPER_OP_ORDER,      "and" },
  { 0x28, BYTE_OPER_REG_OP_ORDER, "sub" },
  { 0x29, OPER_REG_OP_ORDER,      "sub" },
  { 0x2A, BYTE_REG_OPER_OP_ORDER, "sub" },
  { 0x2B, REG_OPER_OP_ORDER,      "sub" },
  { 0x30, BYTE_OPER_REG_OP_ORDER, "xor" },
  { 0x31, OPER_REG_OP_ORDER,      "xor" },
  { 0x32, BYTE_REG_OPER_OP_ORDER, "xor" },
  { 0x33, REG_OPER_OP_ORDER,      "xor" },
  { 0x38, BYTE_OPER_REG_OP_ORDER, "cmp" },
  { 0x39, OPER_REG_OP_ORDER,      "cmp" },
  { 0x3A, BYTE_REG_OPER_OP_ORDER, "cmp" },
  { 0x3B, REG_OPER_OP_ORDER,      "cmp" },
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  { 0x63, REG_OPER_OP_ORDER,      "movsxl" },
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  { 0x84, BYTE_REG_OPER_OP_ORDER, "test" },
  { 0x85, REG_OPER_OP_ORDER,      "test" },
  { 0x86, BYTE_REG_OPER_OP_ORDER, "xchg" },
  { 0x87, REG_OPER_OP_ORDER,      "xchg" },
  { 0x88, BYTE_OPER_REG_OP_ORDER, "mov" },
  { 0x89, OPER_REG_OP_ORDER,      "mov" },
  { 0x8A, BYTE_REG_OPER_OP_ORDER, "mov" },
  { 0x8B, REG_OPER_OP_ORDER,      "mov" },
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  { 0x8D, REG_OPER_OP_ORDER,      "lea" },
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  { -1, UNSET_OP_ORDER, "" }
};


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static const ByteMnemonic zero_operands_instr[] = {
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  { 0xC3, UNSET_OP_ORDER, "ret" },
  { 0xC9, UNSET_OP_ORDER, "leave" },
  { 0xF4, UNSET_OP_ORDER, "hlt" },
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  { 0xFC, UNSET_OP_ORDER, "cld" },
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  { 0xCC, UNSET_OP_ORDER, "int3" },
  { 0x60, UNSET_OP_ORDER, "pushad" },
  { 0x61, UNSET_OP_ORDER, "popad" },
  { 0x9C, UNSET_OP_ORDER, "pushfd" },
  { 0x9D, UNSET_OP_ORDER, "popfd" },
  { 0x9E, UNSET_OP_ORDER, "sahf" },
  { 0x99, UNSET_OP_ORDER, "cdq" },
  { 0x9B, UNSET_OP_ORDER, "fwait" },
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  { 0xA4, UNSET_OP_ORDER, "movs" },
  { 0xA5, UNSET_OP_ORDER, "movs" },
  { 0xA6, UNSET_OP_ORDER, "cmps" },
  { 0xA7, UNSET_OP_ORDER, "cmps" },
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  { -1, UNSET_OP_ORDER, "" }
};


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static const ByteMnemonic call_jump_instr[] = {
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  { 0xE8, UNSET_OP_ORDER, "call" },
  { 0xE9, UNSET_OP_ORDER, "jmp" },
  { -1, UNSET_OP_ORDER, "" }
};


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static const ByteMnemonic short_immediate_instr[] = {
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  { 0x05, UNSET_OP_ORDER, "add" },
  { 0x0D, UNSET_OP_ORDER, "or" },
  { 0x15, UNSET_OP_ORDER, "adc" },
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  { 0x1D, UNSET_OP_ORDER, "sbb" },
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  { 0x25, UNSET_OP_ORDER, "and" },
  { 0x2D, UNSET_OP_ORDER, "sub" },
  { 0x35, UNSET_OP_ORDER, "xor" },
  { 0x3D, UNSET_OP_ORDER, "cmp" },
  { -1, UNSET_OP_ORDER, "" }
};


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static const char* const conditional_code_suffix[] = {
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  "o", "no", "c", "nc", "z", "nz", "na", "a",
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  "s", "ns", "pe", "po", "l", "ge", "le", "g"
};


enum InstructionType {
  NO_INSTR,
  ZERO_OPERANDS_INSTR,
  TWO_OPERANDS_INSTR,
  JUMP_CONDITIONAL_SHORT_INSTR,
  REGISTER_INSTR,
  PUSHPOP_INSTR,  // Has implicit 64-bit operand size.
  MOVE_REG_INSTR,
  CALL_JUMP_INSTR,
  SHORT_IMMEDIATE_INSTR
};


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enum Prefixes {
  ESCAPE_PREFIX = 0x0F,
  OPERAND_SIZE_OVERRIDE_PREFIX = 0x66,
  ADDRESS_SIZE_OVERRIDE_PREFIX = 0x67,
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  VEX3_PREFIX = 0xC4,
  VEX2_PREFIX = 0xC5,
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  REPNE_PREFIX = 0xF2,
  REP_PREFIX = 0xF3,
  REPEQ_PREFIX = REP_PREFIX
};


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struct InstructionDesc {
  const char* mnem;
  InstructionType type;
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  OperandType op_order_;
  bool byte_size_operation;  // Fixed 8-bit operation.
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};


class InstructionTable {
 public:
  InstructionTable();
  const InstructionDesc& Get(byte x) const {
    return instructions_[x];
  }

 private:
  InstructionDesc instructions_[256];
  void Clear();
  void Init();
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  void CopyTable(const ByteMnemonic bm[], InstructionType type);
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  void SetTableRange(InstructionType type, byte start, byte end, bool byte_size,
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                     const char* mnem);
  void AddJumpConditionalShort();
};


InstructionTable::InstructionTable() {
  Clear();
  Init();
}


void InstructionTable::Clear() {
  for (int i = 0; i < 256; i++) {
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    instructions_[i].mnem = "(bad)";
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    instructions_[i].type = NO_INSTR;
    instructions_[i].op_order_ = UNSET_OP_ORDER;
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    instructions_[i].byte_size_operation = false;
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  }
}


void InstructionTable::Init() {
  CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
  CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
  CopyTable(call_jump_instr, CALL_JUMP_INSTR);
  CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
  AddJumpConditionalShort();
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  SetTableRange(PUSHPOP_INSTR, 0x50, 0x57, false, "push");
  SetTableRange(PUSHPOP_INSTR, 0x58, 0x5F, false, "pop");
  SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, false, "mov");
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}


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void InstructionTable::CopyTable(const ByteMnemonic bm[],
                                 InstructionType type) {
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  for (int i = 0; bm[i].b >= 0; i++) {
    InstructionDesc* id = &instructions_[bm[i].b];
    id->mnem = bm[i].mnem;
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    OperandType op_order = bm[i].op_order_;
    id->op_order_ =
        static_cast<OperandType>(op_order & ~BYTE_SIZE_OPERAND_FLAG);
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered
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    id->type = type;
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    id->byte_size_operation = ((op_order & BYTE_SIZE_OPERAND_FLAG) != 0);
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  }
}


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void InstructionTable::SetTableRange(InstructionType type,
                                     byte start,
                                     byte end,
                                     bool byte_size,
                                     const char* mnem) {
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  for (byte b = start; b <= end; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered
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    id->mnem = mnem;
    id->type = type;
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    id->byte_size_operation = byte_size;
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  }
}


void InstructionTable::AddJumpConditionalShort() {
  for (byte b = 0x70; b <= 0x7F; b++) {
    InstructionDesc* id = &instructions_[b];
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    DCHECK_EQ(NO_INSTR, id->type);  // Information not already entered
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    id->mnem = NULL;  // Computed depending on condition code.
    id->type = JUMP_CONDITIONAL_SHORT_INSTR;
  }
}


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static v8::base::LazyInstance<InstructionTable>::type instruction_table =
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    LAZY_INSTANCE_INITIALIZER;
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static const InstructionDesc cmov_instructions[16] = {
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  {"cmovo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovno", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovnc", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovnz", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovna", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmova", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
  {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
};
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//------------------------------------------------------------------------------
// DisassemblerX64 implementation.

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enum UnimplementedOpcodeAction {
  CONTINUE_ON_UNIMPLEMENTED_OPCODE,
  ABORT_ON_UNIMPLEMENTED_OPCODE
};

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// A new DisassemblerX64 object is created to disassemble each instruction.
// The object can only disassemble a single instruction.
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class DisassemblerX64 {
 public:
  DisassemblerX64(const NameConverter& converter,
                  UnimplementedOpcodeAction unimplemented_action =
                      ABORT_ON_UNIMPLEMENTED_OPCODE)
      : converter_(converter),
        tmp_buffer_pos_(0),
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        abort_on_unimplemented_(unimplemented_action ==
                                ABORT_ON_UNIMPLEMENTED_OPCODE),
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        rex_(0),
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        operand_size_(0),
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        group_1_prefix_(0),
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        vex_byte0_(0),
        vex_byte1_(0),
        vex_byte2_(0),
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        byte_size_operand_(false),
        instruction_table_(instruction_table.Pointer()) {
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    tmp_buffer_[0] = '\0';
  }

  virtual ~DisassemblerX64() {
  }

  // Writes one disassembled instruction into 'buffer' (0-terminated).
  // Returns the length of the disassembled machine instruction in bytes.
  int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);

 private:
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  enum OperandSize {
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    OPERAND_BYTE_SIZE = 0,
    OPERAND_WORD_SIZE = 1,
    OPERAND_DOUBLEWORD_SIZE = 2,
    OPERAND_QUADWORD_SIZE = 3
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  };
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  const NameConverter& converter_;
  v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
  unsigned int tmp_buffer_pos_;
  bool abort_on_unimplemented_;
  // Prefixes parsed
  byte rex_;
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  byte operand_size_;  // 0x66 or (if no group 3 prefix is present) 0x0.
  byte group_1_prefix_;  // 0xF2, 0xF3, or (if no group 1 prefix is present) 0.
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  byte vex_byte0_;       // 0xc4 or 0xc5
  byte vex_byte1_;
  byte vex_byte2_;  // only for 3 bytes vex prefix
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  // Byte size operand override.
  bool byte_size_operand_;
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  const InstructionTable* const instruction_table_;
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  void setRex(byte rex) {
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    DCHECK_EQ(0x40, rex & 0xF0);
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    rex_ = rex;
  }

  bool rex() { return rex_ != 0; }

  bool rex_b() { return (rex_ & 0x01) != 0; }

  // Actual number of base register given the low bits and the rex.b state.
  int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); }

  bool rex_x() { return (rex_ & 0x02) != 0; }

  bool rex_r() { return (rex_ & 0x04) != 0; }

  bool rex_w() { return (rex_ & 0x08) != 0; }

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  bool vex_128() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 4) != 1;
  }

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  bool vex_none() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 0;
  }

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  bool vex_66() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 1;
  }

  bool vex_f3() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 2;
  }

  bool vex_f2() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return (checked & 3) == 3;
  }

  bool vex_0f() {
    if (vex_byte0_ == VEX2_PREFIX) return true;
    return (vex_byte1_ & 3) == 1;
  }

  bool vex_0f38() {
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    if (vex_byte0_ == VEX2_PREFIX) return false;
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    return (vex_byte1_ & 3) == 2;
  }

  bool vex_0f3a() {
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    if (vex_byte0_ == VEX2_PREFIX) return false;
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    return (vex_byte1_ & 3) == 3;
  }

  int vex_vreg() {
    DCHECK(vex_byte0_ == VEX3_PREFIX || vex_byte0_ == VEX2_PREFIX);
    byte checked = vex_byte0_ == VEX3_PREFIX ? vex_byte2_ : vex_byte1_;
    return ~(checked >> 3) & 0xf;
  }

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  OperandSize operand_size() {
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    if (byte_size_operand_) return OPERAND_BYTE_SIZE;
    if (rex_w()) return OPERAND_QUADWORD_SIZE;
    if (operand_size_ != 0) return OPERAND_WORD_SIZE;
    return OPERAND_DOUBLEWORD_SIZE;
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  }

  char operand_size_code() {
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    return "bwlq"[operand_size()];
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  }

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  char float_size_code() { return "sd"[rex_w()]; }

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  const char* NameOfCPURegister(int reg) const {
    return converter_.NameOfCPURegister(reg);
  }

  const char* NameOfByteCPURegister(int reg) const {
    return converter_.NameOfByteCPURegister(reg);
  }

  const char* NameOfXMMRegister(int reg) const {
    return converter_.NameOfXMMRegister(reg);
  }

  const char* NameOfAddress(byte* addr) const {
    return converter_.NameOfAddress(addr);
  }

  // Disassembler helper functions.
  void get_modrm(byte data,
                 int* mod,
                 int* regop,
                 int* rm) {
    *mod = (data >> 6) & 3;
    *regop = ((data & 0x38) >> 3) | (rex_r() ? 8 : 0);
    *rm = (data & 7) | (rex_b() ? 8 : 0);
  }

  void get_sib(byte data,
               int* scale,
               int* index,
               int* base) {
    *scale = (data >> 6) & 3;
    *index = ((data >> 3) & 7) | (rex_x() ? 8 : 0);
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    *base = (data & 7) | (rex_b() ? 8 : 0);
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  }

  typedef const char* (DisassemblerX64::*RegisterNameMapping)(int reg) const;

  int PrintRightOperandHelper(byte* modrmp,
                              RegisterNameMapping register_name);
  int PrintRightOperand(byte* modrmp);
  int PrintRightByteOperand(byte* modrmp);
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  int PrintRightXMMOperand(byte* modrmp);
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  int PrintOperands(const char* mnem,
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                    OperandType op_order,
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                    byte* data);
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  int PrintImmediate(byte* data, OperandSize size);
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  int PrintImmediateOp(byte* data);
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  const char* TwoByteMnemonic(byte opcode);
  int TwoByteOpcodeInstruction(byte* data);
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  int F6F7Instruction(byte* data);
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  int ShiftInstruction(byte* data);
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  int JumpShort(byte* data);
  int JumpConditional(byte* data);
  int JumpConditionalShort(byte* data);
  int SetCC(byte* data);
  int FPUInstruction(byte* data);
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  int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
  int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
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  int AVXInstruction(byte* data);
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  void AppendToBuffer(const char* format, ...);

  void UnimplementedInstruction() {
    if (abort_on_unimplemented_) {
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      CHECK(false);
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    } else {
      AppendToBuffer("'Unimplemented Instruction'");
    }
  }
};


void DisassemblerX64::AppendToBuffer(const char* format, ...) {
  v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
  va_list args;
  va_start(args, format);
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  int result = v8::internal::VSNPrintF(buf, format, args);
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  va_end(args);
  tmp_buffer_pos_ += result;
}


int DisassemblerX64::PrintRightOperandHelper(
    byte* modrmp,
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    RegisterNameMapping direct_register_name) {
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  int mod, regop, rm;
  get_modrm(*modrmp, &mod, &regop, &rm);
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  RegisterNameMapping register_name = (mod == 3) ? direct_register_name :
      &DisassemblerX64::NameOfCPURegister;
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  switch (mod) {
    case 0:
      if ((rm & 7) == 5) {
        int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 1);
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        AppendToBuffer("[rip+0x%x]", disp);
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        return 5;
      } else if ((rm & 7) == 4) {
        // Codes for SIB byte.
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
          // index == rsp means no index. Only use sib byte with no index for
          // rsp and r12 base.
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          AppendToBuffer("[%s]", NameOfCPURegister(base));
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          return 2;
        } else if (base == 5) {
          // base == rbp means no base register (when mod == 0).
          int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
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          AppendToBuffer("[%s*%d%s0x%x]",
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                         NameOfCPURegister(index),
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                         1 << scale,
                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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          return 6;
        } else if (index != 4 && base != 5) {
          // [base+index*scale]
          AppendToBuffer("[%s+%s*%d]",
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                         NameOfCPURegister(base),
                         NameOfCPURegister(index),
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                         1 << scale);
          return 2;
        } else {
          UnimplementedInstruction();
          return 1;
        }
      } else {
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        AppendToBuffer("[%s]", NameOfCPURegister(rm));
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        return 1;
      }
      break;
    case 1:  // fall through
    case 2:
      if ((rm & 7) == 4) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 2)
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                              : *reinterpret_cast<int8_t*>(modrmp + 2);
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        if (index == 4 && (base & 7) == 4 && scale == 0 /*times_1*/) {
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          AppendToBuffer("[%s%s0x%x]",
                         NameOfCPURegister(base),
                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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        } else {
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          AppendToBuffer("[%s+%s*%d%s0x%x]",
                         NameOfCPURegister(base),
                         NameOfCPURegister(index),
                         1 << scale,
                         disp < 0 ? "-" : "+",
                         disp < 0 ? -disp : disp);
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        }
        return mod == 2 ? 6 : 3;
      } else {
        // No sib.
        int disp = (mod == 2) ? *reinterpret_cast<int32_t*>(modrmp + 1)
572 573 574 575 576
                              : *reinterpret_cast<int8_t*>(modrmp + 1);
        AppendToBuffer("[%s%s0x%x]",
                       NameOfCPURegister(rm),
                       disp < 0 ? "-" : "+",
                       disp < 0 ? -disp : disp);
577 578 579 580 581 582 583 584 585 586 587 588 589 590
        return (mod == 2) ? 5 : 2;
      }
      break;
    case 3:
      AppendToBuffer("%s", (this->*register_name)(rm));
      return 1;
    default:
      UnimplementedInstruction();
      return 1;
  }
  UNREACHABLE();
}


591 592 593 594
int DisassemblerX64::PrintImmediate(byte* data, OperandSize size) {
  int64_t value;
  int count;
  switch (size) {
595
    case OPERAND_BYTE_SIZE:
596 597 598
      value = *data;
      count = 1;
      break;
599
    case OPERAND_WORD_SIZE:
600 601 602
      value = *reinterpret_cast<int16_t*>(data);
      count = 2;
      break;
603
    case OPERAND_DOUBLEWORD_SIZE:
604 605 606
      value = *reinterpret_cast<uint32_t*>(data);
      count = 4;
      break;
607
    case OPERAND_QUADWORD_SIZE:
608 609 610 611 612 613 614 615
      value = *reinterpret_cast<int32_t*>(data);
      count = 4;
      break;
    default:
      UNREACHABLE();
      value = 0;  // Initialize variables on all paths to satisfy the compiler.
      count = 0;
  }
616
  AppendToBuffer("%" V8_PTR_PREFIX "x", value);
617 618 619 620
  return count;
}


621 622 623 624 625 626 627 628 629
int DisassemblerX64::PrintRightOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerX64::NameOfCPURegister);
}


int DisassemblerX64::PrintRightByteOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerX64::NameOfByteCPURegister);
630
}
631 632


633 634 635 636 637 638
int DisassemblerX64::PrintRightXMMOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerX64::NameOfXMMRegister);
}


639 640 641
// Returns number of bytes used including the current *data.
// Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
int DisassemblerX64::PrintOperands(const char* mnem,
642
                                   OperandType op_order,
643 644 645 646 647
                                   byte* data) {
  byte modrm = *data;
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int advance = 0;
648 649 650
  const char* register_name =
      byte_size_operand_ ? NameOfByteCPURegister(regop)
                         : NameOfCPURegister(regop);
651 652 653 654 655
  switch (op_order) {
    case REG_OPER_OP_ORDER: {
      AppendToBuffer("%s%c %s,",
                     mnem,
                     operand_size_code(),
656 657 658
                     register_name);
      advance = byte_size_operand_ ? PrintRightByteOperand(data)
                                   : PrintRightOperand(data);
659 660 661 662
      break;
    }
    case OPER_REG_OP_ORDER: {
      AppendToBuffer("%s%c ", mnem, operand_size_code());
663 664 665
      advance = byte_size_operand_ ? PrintRightByteOperand(data)
                                   : PrintRightOperand(data);
      AppendToBuffer(",%s", register_name);
666 667 668 669 670 671 672
      break;
    }
    default:
      UNREACHABLE();
      break;
  }
  return advance;
673
}
674 675


676 677 678
// Returns number of bytes used by machine instruction, including *data byte.
// Writes immediate instructions to 'tmp_buffer_'.
int DisassemblerX64::PrintImmediateOp(byte* data) {
679
  bool byte_size_immediate = (*data & 0x02) != 0;
680 681 682 683 684 685 686 687 688 689 690 691 692 693
  byte modrm = *(data + 1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  const char* mnem = "Imm???";
  switch (regop) {
    case 0:
      mnem = "add";
      break;
    case 1:
      mnem = "or";
      break;
    case 2:
      mnem = "adc";
      break;
694 695 696
    case 3:
      mnem = "sbb";
      break;
697 698 699 700 701 702 703 704 705 706 707 708 709 710 711
    case 4:
      mnem = "and";
      break;
    case 5:
      mnem = "sub";
      break;
    case 6:
      mnem = "xor";
      break;
    case 7:
      mnem = "cmp";
      break;
    default:
      UnimplementedInstruction();
  }
712
  AppendToBuffer("%s%c ", mnem, operand_size_code());
713
  int count = PrintRightOperand(data + 1);
714
  AppendToBuffer(",0x");
715 716
  OperandSize immediate_size =
      byte_size_immediate ? OPERAND_BYTE_SIZE : operand_size();
717 718
  count += PrintImmediate(data + 1 + count, immediate_size);
  return 1 + count;
719 720 721 722
}


// Returns number of bytes used, including *data.
723
int DisassemblerX64::F6F7Instruction(byte* data) {
724
  DCHECK(*data == 0xF7 || *data == 0xF6);
725 726 727 728 729 730 731 732 733 734 735 736 737 738 739
  byte modrm = *(data + 1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  if (mod == 3 && regop != 0) {
    const char* mnem = NULL;
    switch (regop) {
      case 2:
        mnem = "not";
        break;
      case 3:
        mnem = "neg";
        break;
      case 4:
        mnem = "mul";
        break;
740 741 742
      case 5:
        mnem = "imul";
        break;
743 744 745
      case 6:
        mnem = "div";
        break;
746 747 748 749 750 751 752 753 754 755 756 757 758
      case 7:
        mnem = "idiv";
        break;
      default:
        UnimplementedInstruction();
    }
    AppendToBuffer("%s%c %s",
                   mnem,
                   operand_size_code(),
                   NameOfCPURegister(rm));
    return 2;
  } else if (regop == 0) {
    AppendToBuffer("test%c ", operand_size_code());
759 760 761 762
    int count = PrintRightOperand(data + 1);  // Use name of 64-bit register.
    AppendToBuffer(",0x");
    count += PrintImmediate(data + 1 + count, operand_size());
    return 1 + count;
763 764 765 766 767 768 769
  } else {
    UnimplementedInstruction();
    return 2;
  }
}


770 771
int DisassemblerX64::ShiftInstruction(byte* data) {
  byte op = *data & (~1);
772
  int count = 1;
773 774
  if (op != 0xD0 && op != 0xD2 && op != 0xC0) {
    UnimplementedInstruction();
775
    return count;
776
  }
777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
  // Print mneumonic.
  {
    byte modrm = *(data + count);
    int mod, regop, rm;
    get_modrm(modrm, &mod, &regop, &rm);
    regop &= 0x7;  // The REX.R bit does not affect the operation.
    const char* mnem = NULL;
    switch (regop) {
      case 0:
        mnem = "rol";
        break;
      case 1:
        mnem = "ror";
        break;
      case 2:
        mnem = "rcl";
        break;
      case 3:
        mnem = "rcr";
        break;
      case 4:
        mnem = "shl";
        break;
      case 5:
        mnem = "shr";
        break;
      case 7:
        mnem = "sar";
        break;
      default:
        UnimplementedInstruction();
        return count + 1;
    }
810
    DCHECK_NOT_NULL(mnem);
811
    AppendToBuffer("%s%c ", mnem, operand_size_code());
812
  }
813
  count += PrintRightOperand(data + count);
814
  if (op == 0xD2) {
815
    AppendToBuffer(", cl");
816
  } else {
817 818 819 820 821 822 823 824 825
    int imm8 = -1;
    if (op == 0xD0) {
      imm8 = 1;
    } else {
      DCHECK_EQ(0xC0, op);
      imm8 = *(data + count);
      count++;
    }
    AppendToBuffer(", %d", imm8);
826
  }
827
  return count;
828 829 830 831 832
}


// Returns number of bytes used, including *data.
int DisassemblerX64::JumpShort(byte* data) {
833
  DCHECK_EQ(0xEB, *data);
834 835 836 837 838 839 840 841 842
  byte b = *(data + 1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  AppendToBuffer("jmp %s", NameOfAddress(dest));
  return 2;
}


// Returns number of bytes used, including *data.
int DisassemblerX64::JumpConditional(byte* data) {
843
  DCHECK_EQ(0x0F, *data);
844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864
  byte cond = *(data + 1) & 0x0F;
  byte* dest = data + *reinterpret_cast<int32_t*>(data + 2) + 6;
  const char* mnem = conditional_code_suffix[cond];
  AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
  return 6;  // includes 0x0F
}


// Returns number of bytes used, including *data.
int DisassemblerX64::JumpConditionalShort(byte* data) {
  byte cond = *data & 0x0F;
  byte b = *(data + 1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  const char* mnem = conditional_code_suffix[cond];
  AppendToBuffer("j%s %s", mnem, NameOfAddress(dest));
  return 2;
}


// Returns number of bytes used, including *data.
int DisassemblerX64::SetCC(byte* data) {
865
  DCHECK_EQ(0x0F, *data);
866 867 868 869 870 871 872 873
  byte cond = *(data + 1) & 0x0F;
  const char* mnem = conditional_code_suffix[cond];
  AppendToBuffer("set%s%c ", mnem, operand_size_code());
  PrintRightByteOperand(data + 2);
  return 3;  // includes 0x0F
}


874 875 876
int DisassemblerX64::AVXInstruction(byte* data) {
  byte opcode = *data;
  byte* current = data + 1;
877
  if (vex_66() && vex_0f38()) {
878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x99:
        AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xa9:
        AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xb9:
        AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x9b:
        AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xab:
        AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xbb:
        AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x9d:
        AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xad:
        AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xbd:
        AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x9f:
        AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xaf:
        AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0xbf:
        AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
                       NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
941 942 943 944 945 946
      case 0xf7:
        AppendToBuffer("shlx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
947 948 949
      default:
        UnimplementedInstruction();
    }
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986
  } else if (vex_f3() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x58:
        AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5c:
        AppendToBuffer("vsubss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5d:
        AppendToBuffer("vminss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5e:
        AppendToBuffer("vdivss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5f:
        AppendToBuffer("vmaxss %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      default:
        UnimplementedInstruction();
    }
987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005
  } else if (vex_f2() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x58:
        AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x59:
        AppendToBuffer("vmulsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x5c:
        AppendToBuffer("vsubsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1006 1007 1008 1009 1010
      case 0x5d:
        AppendToBuffer("vminsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1011 1012 1013 1014 1015
      case 0x5e:
        AppendToBuffer("vdivsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1016 1017 1018 1019 1020
      case 0x5f:
        AppendToBuffer("vmaxsd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
1021 1022
      default:
        UnimplementedInstruction();
1023
    }
1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131
  } else if (vex_none() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    const char* mnem = "?";
    switch (opcode) {
      case 0xf2:
        AppendToBuffer("andn%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
      case 0xf5:
        AppendToBuffer("bzhi%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      case 0xf7:
        AppendToBuffer("bextr%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      case 0xf3:
        switch (regop) {
          case 1:
            mnem = "blsr";
            break;
          case 2:
            mnem = "blsmsk";
            break;
          case 3:
            mnem = "blsi";
            break;
          default:
            UnimplementedInstruction();
        }
        AppendToBuffer("%s%c %s,", mnem, operand_size_code(),
                       NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        mnem = "?";
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0xf5:
        AppendToBuffer("pdep%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
      case 0xf6:
        AppendToBuffer("mulx%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
      case 0xf7:
        AppendToBuffer("shrx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f3() && vex_0f38()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0xf5:
        AppendToBuffer("pext%c %s,%s,", operand_size_code(),
                       NameOfCPURegister(regop), NameOfCPURegister(vvvv));
        current += PrintRightOperand(current);
        break;
      case 0xf7:
        AppendToBuffer("sarx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfCPURegister(vvvv));
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_f2() && vex_0f3a()) {
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0xf0:
        AppendToBuffer("rorx%c %s,", operand_size_code(),
                       NameOfCPURegister(regop));
        current += PrintRightOperand(current);
        switch (operand_size()) {
          case OPERAND_DOUBLEWORD_SIZE:
            AppendToBuffer(",%d", *current & 0x1f);
            break;
          case OPERAND_QUADWORD_SIZE:
            AppendToBuffer(",%d", *current & 0x3f);
            break;
          default:
            UnimplementedInstruction();
        }
        current += 1;
        break;
      default:
        UnimplementedInstruction();
    }
1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
  } else if (vex_none() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x2e:
        AppendToBuffer("vucomiss %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x54:
        AppendToBuffer("vandps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x57:
        AppendToBuffer("vxorps %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      default:
        UnimplementedInstruction();
    }
  } else if (vex_66() && vex_0f()) {
    int mod, regop, rm, vvvv = vex_vreg();
    get_modrm(*current, &mod, &regop, &rm);
    switch (opcode) {
      case 0x2e:
        AppendToBuffer("vucomisd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        break;
      case 0x54:
        AppendToBuffer("vandpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      case 0x57:
        AppendToBuffer("vxorpd %s,%s,", NameOfXMMRegister(regop),
                       NameOfXMMRegister(vvvv));
        current += PrintRightXMMOperand(current);
        break;
      default:
        UnimplementedInstruction();
    }

1175
  } else {
1176
    UnimplementedInstruction();
1177 1178 1179 1180 1181 1182
  }

  return static_cast<int>(current - data);
}


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// Returns number of bytes used, including *data.
int DisassemblerX64::FPUInstruction(byte* data) {
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  byte escape_opcode = *data;
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  DCHECK_EQ(0xD8, escape_opcode & 0xF8);
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  byte modrm_byte = *(data+1);

  if (modrm_byte >= 0xC0) {
    return RegisterFPUInstruction(escape_opcode, modrm_byte);
  } else {
    return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
  }
}

int DisassemblerX64::MemoryFPUInstruction(int escape_opcode,
                                           int modrm_byte,
                                           byte* modrm_start) {
  const char* mnem = "?";
  int regop = (modrm_byte >> 3) & 0x7;  // reg/op field of modrm byte.
  switch (escape_opcode) {
    case 0xD9: switch (regop) {
        case 0: mnem = "fld_s"; break;
        case 3: mnem = "fstp_s"; break;
        case 7: mnem = "fstcw"; break;
        default: UnimplementedInstruction();
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      }
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      break;

    case 0xDB: switch (regop) {
        case 0: mnem = "fild_s"; break;
        case 1: mnem = "fisttp_s"; break;
        case 2: mnem = "fist_s"; break;
        case 3: mnem = "fistp_s"; break;
        default: UnimplementedInstruction();
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      }
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      break;

    case 0xDD: switch (regop) {
        case 0: mnem = "fld_d"; break;
        case 3: mnem = "fstp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDF: switch (regop) {
        case 5: mnem = "fild_d"; break;
        case 7: mnem = "fistp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    default: UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(modrm_start);
  return count + 1;
}

int DisassemblerX64::RegisterFPUInstruction(int escape_opcode,
                                             byte modrm_byte) {
  bool has_register = false;  // Is the FPU register encoded in modrm_byte?
  const char* mnem = "?";

  switch (escape_opcode) {
    case 0xD8:
      UnimplementedInstruction();
      break;

    case 0xD9:
      switch (modrm_byte & 0xF8) {
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        case 0xC0:
          mnem = "fld";
          has_register = true;
          break;
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        case 0xC8:
          mnem = "fxch";
          has_register = true;
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          break;
        default:
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          switch (modrm_byte) {
            case 0xE0: mnem = "fchs"; break;
            case 0xE1: mnem = "fabs"; break;
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            case 0xE3: mnem = "fninit"; break;
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            case 0xE4: mnem = "ftst"; break;
            case 0xE8: mnem = "fld1"; break;
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            case 0xEB: mnem = "fldpi"; break;
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            case 0xED: mnem = "fldln2"; break;
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            case 0xEE: mnem = "fldz"; break;
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            case 0xF0: mnem = "f2xm1"; break;
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            case 0xF1: mnem = "fyl2x"; break;
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            case 0xF2: mnem = "fptan"; break;
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            case 0xF5: mnem = "fprem1"; break;
            case 0xF7: mnem = "fincstp"; break;
            case 0xF8: mnem = "fprem"; break;
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            case 0xFC: mnem = "frndint"; break;
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            case 0xFD: mnem = "fscale"; break;
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            case 0xFE: mnem = "fsin"; break;
            case 0xFF: mnem = "fcos"; break;
            default: UnimplementedInstruction();
          }
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      }
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      break;

    case 0xDA:
      if (modrm_byte == 0xE9) {
        mnem = "fucompp";
      } else {
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        UnimplementedInstruction();
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      }
      break;

    case 0xDB:
      if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomi";
        has_register = true;
      } else if (modrm_byte  == 0xE2) {
        mnem = "fclex";
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      } else if (modrm_byte == 0xE3) {
        mnem = "fninit";
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      } else {
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        UnimplementedInstruction();
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      }
      break;

    case 0xDC:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "fadd"; break;
        case 0xE8: mnem = "fsub"; break;
        case 0xC8: mnem = "fmul"; break;
        case 0xF8: mnem = "fdiv"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDD:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "ffree"; break;
        case 0xD8: mnem = "fstp"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDE:
      if (modrm_byte  == 0xD9) {
        mnem = "fcompp";
      } else {
        has_register = true;
        switch (modrm_byte & 0xF8) {
          case 0xC0: mnem = "faddp"; break;
          case 0xE8: mnem = "fsubp"; break;
          case 0xC8: mnem = "fmulp"; break;
          case 0xF8: mnem = "fdivp"; break;
          default: UnimplementedInstruction();
        }
      }
      break;

    case 0xDF:
      if (modrm_byte == 0xE0) {
        mnem = "fnstsw_ax";
      } else if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomip";
        has_register = true;
      }
      break;

    default: UnimplementedInstruction();
  }

  if (has_register) {
    AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
  } else {
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    AppendToBuffer("%s", mnem);
  }
  return 2;
}

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// Handle all two-byte opcodes, which start with 0x0F.
// These instructions may be affected by an 0x66, 0xF2, or 0xF3 prefix.
// We do not use any three-byte opcodes, which start with 0x0F38 or 0x0F3A.
int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
  byte opcode = *(data + 1);
  byte* current = data + 2;
  // At return, "current" points to the start of the next instruction.
  const char* mnemonic = TwoByteMnemonic(opcode);
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  if (operand_size_ == 0x66) {
    // 0x66 0x0F prefix.
    int mod, regop, rm;
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    if (opcode == 0x3A) {
      byte third_byte = *current;
      current = data + 3;
      if (third_byte == 0x17) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("extractps ");  // reg/m32, xmm, imm8
        current += PrintRightOperand(current);
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        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
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        current += 1;
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      } else if (third_byte == 0x0b) {
        get_modrm(*current, &mod, &regop, &rm);
         // roundsd xmm, xmm/m64, imm8
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        AppendToBuffer("roundsd %s,", NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
        AppendToBuffer(",%d", (*current) & 3);
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        current += 1;
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      } else if (third_byte == 0x16) {
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        get_modrm(*current, &mod, &rm, &regop);
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        AppendToBuffer("pextrd ");  // reg/m32, xmm, imm8
        current += PrintRightOperand(current);
        AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), (*current) & 3);
        current += 1;
      } else if (third_byte == 0x22) {
        get_modrm(*current, &mod, &regop, &rm);
        AppendToBuffer("pinsrd ");  // xmm, reg/m32, imm8
        AppendToBuffer(" %s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
        AppendToBuffer(",%d", (*current) & 3);
        current += 1;
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      } else {
        UnimplementedInstruction();
      }
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    } else {
      get_modrm(*current, &mod, &regop, &rm);
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      if (opcode == 0x1f) {
        current++;
        if (rm == 4) {  // SIB byte present.
          current++;
        }
        if (mod == 1) {  // Byte displacement.
          current += 1;
        } else if (mod == 2) {  // 32-bit displacement.
          current += 4;
        }  // else no immediate displacement.
        AppendToBuffer("nop");
      } else if (opcode == 0x28) {
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        AppendToBuffer("movapd %s,", NameOfXMMRegister(regop));
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        current += PrintRightXMMOperand(current);
      } else if (opcode == 0x29) {
        AppendToBuffer("movapd ");
        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0x6E) {
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        AppendToBuffer("mov%c %s,",
                       rex_w() ? 'q' : 'd',
                       NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
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      } else if (opcode == 0x6F) {
        AppendToBuffer("movdqa %s,",
                       NameOfXMMRegister(regop));
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        current += PrintRightXMMOperand(current);
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      } else if (opcode == 0x7E) {
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        AppendToBuffer("mov%c ",
                       rex_w() ? 'q' : 'd');
        current += PrintRightOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0x7F) {
        AppendToBuffer("movdqa ");
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        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0xD6) {
        AppendToBuffer("movq ");
        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
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      } else if (opcode == 0x50) {
        AppendToBuffer("movmskpd %s,", NameOfCPURegister(regop));
        current += PrintRightXMMOperand(current);
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      } else if (opcode == 0x72) {
        current += 1;
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        AppendToBuffer("%s %s,%d", (regop == 6) ? "pslld" : "psrld",
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                       NameOfXMMRegister(rm), *current & 0x7f);
        current += 1;
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      } else if (opcode == 0x73) {
        current += 1;
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        AppendToBuffer("%s %s,%d", (regop == 6) ? "psllq" : "psrlq",
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                       NameOfXMMRegister(rm), *current & 0x7f);
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        current += 1;
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      } else {
        const char* mnemonic = "?";
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        if (opcode == 0x54) {
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          mnemonic = "andpd";
        } else  if (opcode == 0x56) {
          mnemonic = "orpd";
        } else  if (opcode == 0x57) {
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          mnemonic = "xorpd";
        } else if (opcode == 0x2E) {
          mnemonic = "ucomisd";
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        } else if (opcode == 0x2F) {
          mnemonic = "comisd";
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        } else if (opcode == 0x76) {
          mnemonic = "pcmpeqd";
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        } else if (opcode == 0x62) {
          mnemonic = "punpckldq";
        } else if (opcode == 0x6A) {
          mnemonic = "punpckhdq";
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        } else {
          UnimplementedInstruction();
        }
        AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
        current += PrintRightXMMOperand(current);
      }
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    }
  } else if (group_1_prefix_ == 0xF2) {
    // Beginning of instructions with prefix 0xF2.

    if (opcode == 0x11 || opcode == 0x10) {
      // MOVSD: Move scalar double-precision fp to/from/between XMM registers.
      AppendToBuffer("movsd ");
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      if (opcode == 0x11) {
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        current += PrintRightXMMOperand(current);
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        AppendToBuffer(",%s", NameOfXMMRegister(regop));
      } else {
        AppendToBuffer("%s,", NameOfXMMRegister(regop));
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        current += PrintRightXMMOperand(current);
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      }
    } else if (opcode == 0x2A) {
      // CVTSI2SD: integer to XMM double conversion.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
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      current += PrintRightOperand(current);
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    } else if (opcode == 0x2C) {
      // CVTTSD2SI:
      // Convert with truncation scalar double-precision FP to integer.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("cvttsd2si%c %s,",
          operand_size_code(), NameOfCPURegister(regop));
      current += PrintRightXMMOperand(current);
    } else if (opcode == 0x2D) {
      // CVTSD2SI: Convert scalar double-precision FP to integer.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("cvtsd2si%c %s,",
          operand_size_code(), NameOfCPURegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
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      // XMM arithmetic. Mnemonic was retrieved at the start of this function.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0xC2) {
      // Intel manual 2A, Table 3-18.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      const char* const pseudo_op[] = {
        "cmpeqsd",
        "cmpltsd",
        "cmplesd",
        "cmpunordsd",
        "cmpneqsd",
        "cmpnltsd",
        "cmpnlesd",
        "cmpordsd"
      };
      AppendToBuffer("%s %s,%s",
                     pseudo_op[current[1]],
                     NameOfXMMRegister(regop),
                     NameOfXMMRegister(rm));
      current += 2;
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    } else {
      UnimplementedInstruction();
    }
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  } else if (group_1_prefix_ == 0xF3) {
    // Instructions with prefix 0xF3.
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    if (opcode == 0x11 || opcode == 0x10) {
      // MOVSS: Move scalar double-precision fp to/from/between XMM registers.
      AppendToBuffer("movss ");
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      if (opcode == 0x11) {
        current += PrintRightOperand(current);
        AppendToBuffer(",%s", NameOfXMMRegister(regop));
      } else {
        AppendToBuffer("%s,", NameOfXMMRegister(regop));
        current += PrintRightOperand(current);
      }
    } else if (opcode == 0x2A) {
      // CVTSI2SS: integer to XMM single conversion.
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
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      current += PrintRightOperand(current);
    } else if (opcode == 0x2C) {
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      // CVTTSS2SI:
      // Convert with truncation scalar single-precision FP to dword integer.
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("cvttss2si%c %s,",
          operand_size_code(), NameOfCPURegister(regop));
      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0x7E) {
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("movq %s,", NameOfXMMRegister(regop));
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      current += PrintRightXMMOperand(current);
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    } else if ((opcode & 0xF8) == 0x58 || opcode == 0x51) {
      // XMM arithmetic. Mnemonic was retrieved at the start of this function.
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      AppendToBuffer("%s %s,", mnemonic, NameOfXMMRegister(regop));
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      current += PrintRightXMMOperand(current);
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    } else if (opcode == 0xB8) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("popcnt%c %s,", operand_size_code(),
                     NameOfCPURegister(regop));
      current += PrintRightOperand(current);
    } else if (opcode == 0xBC) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("tzcnt%c %s,", operand_size_code(),
                     NameOfCPURegister(regop));
      current += PrintRightOperand(current);
    } else if (opcode == 0xBD) {
      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
      AppendToBuffer("lzcnt%c %s,", operand_size_code(),
                     NameOfCPURegister(regop));
      current += PrintRightOperand(current);
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    } else if (opcode == 0xC2) {
      // Intel manual 2A, Table 3-18.
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      int mod, regop, rm;
      get_modrm(*current, &mod, &regop, &rm);
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      const char* const pseudo_op[] = {"cmpeqss",    "cmpltss",  "cmpless",
                                       "cmpunordss", "cmpneqss", "cmpnltss",
                                       "cmpnless",   "cmpordss"};
      AppendToBuffer("%s %s,%s", pseudo_op[current[1]],
                     NameOfXMMRegister(regop), NameOfXMMRegister(rm));
      current += 2;
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    } else {
      UnimplementedInstruction();
    }
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  } else if (opcode == 0x1F) {
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    // NOP
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    current++;
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    if (rm == 4) {  // SIB byte present.
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      current++;
    }
    if (mod == 1) {  // Byte displacement.
      current += 1;
    } else if (mod == 2) {  // 32-bit displacement.
      current += 4;
    }  // else no immediate displacement.
    AppendToBuffer("nop");
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  } else if (opcode == 0x28) {
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    // movaps xmm, xmm/m128
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    AppendToBuffer("movaps %s,", NameOfXMMRegister(regop));
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    current += PrintRightXMMOperand(current);

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  } else if (opcode == 0x29) {
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    // movaps xmm/m128, xmm
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    AppendToBuffer("movaps ");
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    current += PrintRightXMMOperand(current);
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    AppendToBuffer(",%s", NameOfXMMRegister(regop));
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  } else if (opcode == 0x2e) {
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    AppendToBuffer("ucomiss %s,", NameOfXMMRegister(regop));
    current += PrintRightXMMOperand(current);
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  } else if (opcode == 0xA2) {
    // CPUID
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    AppendToBuffer("%s", mnemonic);

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  } else if ((opcode & 0xF0) == 0x40) {
    // CMOVcc: conditional move.
    int condition = opcode & 0x0F;
    const InstructionDesc& idesc = cmov_instructions[condition];
    byte_size_operand_ = idesc.byte_size_operation;
    current += PrintOperands(idesc.mnem, idesc.op_order_, current);

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  } else if (opcode >= 0x53 && opcode <= 0x5F) {
    const char* const pseudo_op[] = {
      "rcpps",
      "andps",
      "andnps",
      "orps",
      "xorps",
      "addps",
      "mulps",
      "cvtps2pd",
      "cvtdq2ps",
      "subps",
      "minps",
      "divps",
      "maxps",
    };
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    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    AppendToBuffer("%s %s,",
                   pseudo_op[opcode - 0x53],
                   NameOfXMMRegister(regop));
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    current += PrintRightXMMOperand(current);

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  } else if (opcode == 0xC6) {
    // shufps xmm, xmm/m128, imm8
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    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
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    AppendToBuffer("shufps %s, ", NameOfXMMRegister(regop));
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    current += PrintRightXMMOperand(current);
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    AppendToBuffer(", %d", (*current) & 3);
    current += 1;
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  } else if (opcode == 0x50) {
    // movmskps reg, xmm
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
1702
    AppendToBuffer("movmskps %s,", NameOfCPURegister(regop));
1703 1704
    current += PrintRightXMMOperand(current);

1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728
  } else if ((opcode & 0xF0) == 0x80) {
    // Jcc: Conditional jump (branch).
    current = data + JumpConditional(data);

  } else if (opcode == 0xBE || opcode == 0xBF || opcode == 0xB6 ||
             opcode == 0xB7 || opcode == 0xAF) {
    // Size-extending moves, IMUL.
    current += PrintOperands(mnemonic, REG_OPER_OP_ORDER, current);

  } else if ((opcode & 0xF0) == 0x90) {
    // SETcc: Set byte on condition. Needs pointer to beginning of instruction.
    current = data + SetCC(data);

  } else if (opcode == 0xAB || opcode == 0xA5 || opcode == 0xAD) {
    // SHLD, SHRD (double-precision shift), BTS (bit set).
    AppendToBuffer("%s ", mnemonic);
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    current += PrintRightOperand(current);
    if (opcode == 0xAB) {
      AppendToBuffer(",%s", NameOfCPURegister(regop));
    } else {
      AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
    }
1729 1730 1731 1732 1733 1734
  } else if (opcode == 0xBD) {
    AppendToBuffer("%s%c ", mnemonic, operand_size_code());
    int mod, regop, rm;
    get_modrm(*current, &mod, &regop, &rm);
    AppendToBuffer("%s,", NameOfCPURegister(regop));
    current += PrintRightOperand(current);
1735 1736
  } else if (opcode == 0x0B) {
    AppendToBuffer("ud2");
1737 1738 1739
  } else {
    UnimplementedInstruction();
  }
1740
  return static_cast<int>(current - data);
1741 1742 1743 1744 1745
}


// Mnemonics for two-byte opcode instructions starting with 0x0F.
// The argument is the second byte of the two-byte opcode.
1746
// Returns NULL if the instruction is not handled here.
1747 1748
const char* DisassemblerX64::TwoByteMnemonic(byte opcode) {
  switch (opcode) {
1749 1750
    case 0x1F:
      return "nop";
1751
    case 0x2A:  // F2/F3 prefix.
1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768
      return (group_1_prefix_ == 0xF2) ? "cvtsi2sd" : "cvtsi2ss";
    case 0x51:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "sqrtsd" : "sqrtss";
    case 0x58:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "addsd" : "addss";
    case 0x59:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "mulsd" : "mulss";
    case 0x5A:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "cvtsd2ss" : "cvtss2sd";
    case 0x5D:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "minsd" : "minss";
    case 0x5C:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "subsd" : "subss";
    case 0x5E:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "divsd" : "divss";
    case 0x5F:  // F2/F3 prefix.
      return (group_1_prefix_ == 0xF2) ? "maxsd" : "maxss";
1769 1770 1771 1772 1773 1774
    case 0xA2:
      return "cpuid";
    case 0xA5:
      return "shld";
    case 0xAB:
      return "bts";
1775 1776 1777 1778 1779 1780 1781 1782
    case 0xAD:
      return "shrd";
    case 0xAF:
      return "imul";
    case 0xB6:
      return "movzxb";
    case 0xB7:
      return "movzxw";
1783 1784
    case 0xBD:
      return "bsr";
1785 1786 1787 1788
    case 0xBE:
      return "movsxb";
    case 0xBF:
      return "movsxw";
1789 1790 1791 1792 1793
    default:
      return NULL;
  }
}

1794 1795

// Disassembles the instruction at instr, and writes it into out_buffer.
1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806
int DisassemblerX64::InstructionDecode(v8::internal::Vector<char> out_buffer,
                                       byte* instr) {
  tmp_buffer_pos_ = 0;  // starting to write as position 0
  byte* data = instr;
  bool processed = true;  // Will be set to false if the current instruction
                          // is not in 'instructions' table.
  byte current;

  // Scan for prefixes.
  while (true) {
    current = *data;
1807
    if (current == OPERAND_SIZE_OVERRIDE_PREFIX) {  // Group 3 prefix.
1808 1809
      operand_size_ = current;
    } else if ((current & 0xF0) == 0x40) {  // REX prefix.
1810 1811
      setRex(current);
      if (rex_w()) AppendToBuffer("REX.W ");
1812
    } else if ((current & 0xFE) == 0xF2) {  // Group 1 prefix (0xF2 or 0xF3).
1813
      group_1_prefix_ = current;
1814 1815 1816 1817 1818
    } else if (current == VEX3_PREFIX) {
      vex_byte0_ = current;
      vex_byte1_ = *(data + 1);
      vex_byte2_ = *(data + 2);
      setRex(0x40 | (~(vex_byte1_ >> 5) & 7) | ((vex_byte2_ >> 4) & 8));
1819 1820
      data += 3;
      break;  // Vex is the last prefix.
1821 1822 1823 1824
    } else if (current == VEX2_PREFIX) {
      vex_byte0_ = current;
      vex_byte1_ = *(data + 1);
      setRex(0x40 | (~(vex_byte1_ >> 5) & 4));
1825 1826
      data += 2;
      break;  // Vex is the last prefix.
1827
    } else {  // Not a prefix - an opcode.
1828 1829
      break;
    }
1830
    data++;
1831 1832
  }

1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851
  // Decode AVX instructions.
  if (vex_byte0_ != 0) {
    processed = true;
    data += AVXInstruction(data);
  } else {
    const InstructionDesc& idesc = instruction_table_->Get(current);
    byte_size_operand_ = idesc.byte_size_operation;
    switch (idesc.type) {
      case ZERO_OPERANDS_INSTR:
        if (current >= 0xA4 && current <= 0xA7) {
          // String move or compare operations.
          if (group_1_prefix_ == REP_PREFIX) {
            // REP.
            AppendToBuffer("rep ");
          }
          if (rex_w()) AppendToBuffer("REX.W ");
          AppendToBuffer("%s%c", idesc.mnem, operand_size_code());
        } else {
          AppendToBuffer("%s", idesc.mnem, operand_size_code());
1852
        }
1853 1854
        data++;
        break;
1855

1856 1857 1858 1859
      case TWO_OPERANDS_INSTR:
        data++;
        data += PrintOperands(idesc.mnem, idesc.op_order_, data);
        break;
1860

1861 1862 1863
      case JUMP_CONDITIONAL_SHORT_INSTR:
        data += JumpConditionalShort(data);
        break;
1864

1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899
      case REGISTER_INSTR:
        AppendToBuffer("%s%c %s", idesc.mnem, operand_size_code(),
                       NameOfCPURegister(base_reg(current & 0x07)));
        data++;
        break;
      case PUSHPOP_INSTR:
        AppendToBuffer("%s %s", idesc.mnem,
                       NameOfCPURegister(base_reg(current & 0x07)));
        data++;
        break;
      case MOVE_REG_INSTR: {
        byte* addr = NULL;
        switch (operand_size()) {
          case OPERAND_WORD_SIZE:
            addr =
                reinterpret_cast<byte*>(*reinterpret_cast<int16_t*>(data + 1));
            data += 3;
            break;
          case OPERAND_DOUBLEWORD_SIZE:
            addr =
                reinterpret_cast<byte*>(*reinterpret_cast<uint32_t*>(data + 1));
            data += 5;
            break;
          case OPERAND_QUADWORD_SIZE:
            addr =
                reinterpret_cast<byte*>(*reinterpret_cast<int64_t*>(data + 1));
            data += 9;
            break;
          default:
            UNREACHABLE();
        }
        AppendToBuffer("mov%c %s,%s", operand_size_code(),
                       NameOfCPURegister(base_reg(current & 0x07)),
                       NameOfAddress(addr));
        break;
1900 1901
      }

1902 1903 1904 1905 1906 1907
      case CALL_JUMP_INSTR: {
        byte* addr = data + *reinterpret_cast<int32_t*>(data + 1) + 5;
        AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
        data += 5;
        break;
      }
1908

1909 1910 1911 1912 1913 1914 1915
      case SHORT_IMMEDIATE_INSTR: {
        byte* addr =
            reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data + 1));
        AppendToBuffer("%s rax,%s", idesc.mnem, NameOfAddress(addr));
        data += 5;
        break;
      }
1916

1917 1918 1919
      case NO_INSTR:
        processed = false;
        break;
1920

1921 1922 1923
      default:
        UNIMPLEMENTED();  // This type is not implemented.
    }
1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936
  }

  // The first byte didn't match any of the simple opcodes, so we
  // need to do special processing on it.
  if (!processed) {
    switch (*data) {
      case 0xC2:
        AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data + 1));
        data += 3;
        break;

      case 0x69:  // fall through
      case 0x6B: {
1937 1938 1939 1940 1941 1942 1943 1944 1945
        int count = 1;
        count += PrintOperands("imul", REG_OPER_OP_ORDER, data + count);
        AppendToBuffer(",0x");
        if (*data == 0x69) {
          count += PrintImmediate(data + count, operand_size());
        } else {
          count += PrintImmediate(data + count, OPERAND_BYTE_SIZE);
        }
        data += count;
1946
        break;
1947
      }
1948 1949 1950 1951 1952 1953

      case 0x81:  // fall through
      case 0x83:  // 0x81 with sign extension bit set
        data += PrintImmediateOp(data);
        break;

1954 1955
      case 0x0F:
        data += TwoByteOpcodeInstruction(data);
1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004
        break;

      case 0x8F: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        if (regop == 0) {
          AppendToBuffer("pop ");
          data += PrintRightOperand(data);
        }
      }
        break;

      case 0xFF: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
        const char* mnem = NULL;
        switch (regop) {
          case 0:
            mnem = "inc";
            break;
          case 1:
            mnem = "dec";
            break;
          case 2:
            mnem = "call";
            break;
          case 4:
            mnem = "jmp";
            break;
          case 6:
            mnem = "push";
            break;
          default:
            mnem = "???";
        }
        AppendToBuffer(((regop <= 1) ? "%s%c " : "%s "),
                       mnem,
                       operand_size_code());
        data += PrintRightOperand(data);
      }
        break;

      case 0xC7:  // imm32, fall through
      case 0xC6:  // imm8
      {
        bool is_byte = *data == 0xC6;
        data++;
2005 2006 2007 2008 2009 2010 2011 2012 2013
        if (is_byte) {
          AppendToBuffer("movb ");
          data += PrintRightByteOperand(data);
          int32_t imm = *data;
          AppendToBuffer(",0x%x", imm);
          data++;
        } else {
          AppendToBuffer("mov%c ", operand_size_code());
          data += PrintRightOperand(data);
2014 2015 2016 2017 2018 2019 2020 2021 2022
          if (operand_size() == OPERAND_WORD_SIZE) {
            int16_t imm = *reinterpret_cast<int16_t*>(data);
            AppendToBuffer(",0x%x", imm);
            data += 2;
          } else {
            int32_t imm = *reinterpret_cast<int32_t*>(data);
            AppendToBuffer(",0x%x", imm);
            data += 4;
          }
2023
        }
2024 2025 2026 2027 2028 2029
      }
        break;

      case 0x80: {
        data++;
        AppendToBuffer("cmpb ");
2030
        data += PrintRightByteOperand(data);
2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043
        int32_t imm = *data;
        AppendToBuffer(",0x%x", imm);
        data++;
      }
        break;

      case 0x88:  // 8bit, fall through
      case 0x89:  // 32bit
      {
        bool is_byte = *data == 0x88;
        int mod, regop, rm;
        data++;
        get_modrm(*data, &mod, &regop, &rm);
2044 2045 2046 2047 2048 2049 2050 2051 2052
        if (is_byte) {
          AppendToBuffer("movb ");
          data += PrintRightByteOperand(data);
          AppendToBuffer(",%s", NameOfByteCPURegister(regop));
        } else {
          AppendToBuffer("mov%c ", operand_size_code());
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfCPURegister(regop));
        }
2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063
      }
        break;

      case 0x90:
      case 0x91:
      case 0x92:
      case 0x93:
      case 0x94:
      case 0x95:
      case 0x96:
      case 0x97: {
2064
        int reg = (*data & 0x7) | (rex_b() ? 8 : 0);
2065 2066 2067
        if (reg == 0) {
          AppendToBuffer("nop");  // Common name for xchg rax,rax.
        } else {
2068
          AppendToBuffer("xchg%c rax,%s",
2069
                         operand_size_code(),
2070
                         NameOfCPURegister(reg));
2071
        }
2072
        data++;
2073
      }
2074
        break;
2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096
      case 0xB0:
      case 0xB1:
      case 0xB2:
      case 0xB3:
      case 0xB4:
      case 0xB5:
      case 0xB6:
      case 0xB7:
      case 0xB8:
      case 0xB9:
      case 0xBA:
      case 0xBB:
      case 0xBC:
      case 0xBD:
      case 0xBE:
      case 0xBF: {
        // mov reg8,imm8 or mov reg32,imm32
        byte opcode = *data;
        data++;
        bool is_32bit = (opcode >= 0xB8);
        int reg = (opcode & 0x7) | (rex_b() ? 8 : 0);
        if (is_32bit) {
2097
          AppendToBuffer("mov%c %s,",
2098 2099
                         operand_size_code(),
                         NameOfCPURegister(reg));
2100
          data += PrintImmediate(data, OPERAND_DOUBLEWORD_SIZE);
2101
        } else {
2102
          AppendToBuffer("movb %s,",
2103
                         NameOfByteCPURegister(reg));
2104
          data += PrintImmediate(data, OPERAND_BYTE_SIZE);
2105 2106 2107
        }
        break;
      }
2108 2109 2110 2111
      case 0xFE: {
        data++;
        int mod, regop, rm;
        get_modrm(*data, &mod, &regop, &rm);
2112 2113
        if (regop == 1) {
          AppendToBuffer("decb ");
2114
          data += PrintRightByteOperand(data);
2115 2116 2117 2118
        } else {
          UnimplementedInstruction();
        }
        break;
2119
      }
2120 2121 2122 2123 2124 2125 2126 2127 2128 2129
      case 0x68:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data + 1));
        data += 5;
        break;

      case 0x6A:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
        data += 2;
        break;

2130 2131 2132
      case 0xA1:  // Fall through.
      case 0xA3:
        switch (operand_size()) {
2133
          case OPERAND_DOUBLEWORD_SIZE: {
2134 2135 2136
            const char* memory_location = NameOfAddress(
                reinterpret_cast<byte*>(
                    *reinterpret_cast<int32_t*>(data + 1)));
2137
            if (*data == 0xA1) {  // Opcode 0xA1
2138
              AppendToBuffer("movzxlq rax,(%s)", memory_location);
2139
            } else {  // Opcode 0xA3
2140 2141 2142 2143 2144
              AppendToBuffer("movzxlq (%s),rax", memory_location);
            }
            data += 5;
            break;
          }
2145
          case OPERAND_QUADWORD_SIZE: {
2146 2147 2148
            // New x64 instruction mov rax,(imm_64).
            const char* memory_location = NameOfAddress(
                *reinterpret_cast<byte**>(data + 1));
2149
            if (*data == 0xA1) {  // Opcode 0xA1
2150
              AppendToBuffer("movq rax,(%s)", memory_location);
2151
            } else {  // Opcode 0xA3
2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162
              AppendToBuffer("movq (%s),rax", memory_location);
            }
            data += 9;
            break;
          }
          default:
            UnimplementedInstruction();
            data += 2;
        }
        break;

2163 2164 2165 2166 2167
      case 0xA8:
        AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data + 1));
        data += 2;
        break;

2168
      case 0xA9: {
2169
        int64_t value = 0;
2170
        switch (operand_size()) {
2171
          case OPERAND_WORD_SIZE:
2172 2173 2174
            value = *reinterpret_cast<uint16_t*>(data + 1);
            data += 3;
            break;
2175
          case OPERAND_DOUBLEWORD_SIZE:
2176 2177 2178
            value = *reinterpret_cast<uint32_t*>(data + 1);
            data += 5;
            break;
2179
          case OPERAND_QUADWORD_SIZE:
2180 2181 2182 2183 2184 2185
            value = *reinterpret_cast<int32_t*>(data + 1);
            data += 5;
            break;
          default:
            UNREACHABLE();
        }
2186
        AppendToBuffer("test%c rax,0x%" V8_PTR_PREFIX "x",
2187 2188
                       operand_size_code(),
                       value);
2189
        break;
2190
      }
2191 2192 2193
      case 0xD1:  // fall through
      case 0xD3:  // fall through
      case 0xC1:
2194 2195 2196 2197 2198 2199 2200
        data += ShiftInstruction(data);
        break;
      case 0xD0:  // fall through
      case 0xD2:  // fall through
      case 0xC0:
        byte_size_operand_ = true;
        data += ShiftInstruction(data);
2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216
        break;

      case 0xD9:  // fall through
      case 0xDA:  // fall through
      case 0xDB:  // fall through
      case 0xDC:  // fall through
      case 0xDD:  // fall through
      case 0xDE:  // fall through
      case 0xDF:
        data += FPUInstruction(data);
        break;

      case 0xEB:
        data += JumpShort(data);
        break;

2217 2218
      case 0xF6:
        byte_size_operand_ = true;  // fall through
2219
      case 0xF7:
2220
        data += F6F7Instruction(data);
2221 2222
        break;

2223
      case 0x3C:
2224
        AppendToBuffer("cmp al,0x%x", *reinterpret_cast<int8_t*>(data + 1));
2225 2226 2227
        data +=2;
        break;

2228 2229
      default:
        UnimplementedInstruction();
2230
        data += 1;
2231 2232 2233 2234 2235 2236 2237
    }
  }  // !processed

  if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
    tmp_buffer_[tmp_buffer_pos_] = '\0';
  }

2238
  int instr_len = static_cast<int>(data - instr);
2239
  DCHECK(instr_len > 0);  // Ensure progress.
2240 2241 2242 2243

  int outp = 0;
  // Instruction bytes.
  for (byte* bp = instr; bp < data; bp++) {
2244
    outp += v8::internal::SNPrintF(out_buffer + outp, "%02x", *bp);
2245 2246
  }
  for (int i = 6 - instr_len; i >= 0; i--) {
2247
    outp += v8::internal::SNPrintF(out_buffer + outp, "  ");
2248 2249
  }

2250 2251
  outp += v8::internal::SNPrintF(out_buffer + outp, " %s",
                                 tmp_buffer_.start());
2252 2253 2254
  return instr_len;
}

2255

2256 2257 2258
//------------------------------------------------------------------------------


2259
static const char* const cpu_regs[16] = {
2260 2261 2262 2263 2264
  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};


2265
static const char* const byte_cpu_regs[16] = {
2266 2267 2268 2269 2270
  "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
  "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"
};


2271
static const char* const xmm_regs[16] = {
2272 2273 2274 2275 2276 2277
  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
};


const char* NameConverter::NameOfAddress(byte* addr) const {
2278
  v8::internal::SNPrintF(tmp_buffer_, "%p", addr);
2279
  return tmp_buffer_.start();
2280 2281 2282 2283 2284
}


const char* NameConverter::NameOfConstant(byte* addr) const {
  return NameOfAddress(addr);
2285
}
2286 2287


2288
const char* NameConverter::NameOfCPURegister(int reg) const {
2289 2290 2291
  if (0 <= reg && reg < 16)
    return cpu_regs[reg];
  return "noreg";
2292
}
2293 2294


2295 2296 2297 2298
const char* NameConverter::NameOfByteCPURegister(int reg) const {
  if (0 <= reg && reg < 16)
    return byte_cpu_regs[reg];
  return "noreg";
2299
}
2300 2301


2302 2303 2304 2305
const char* NameConverter::NameOfXMMRegister(int reg) const {
  if (0 <= reg && reg < 16)
    return xmm_regs[reg];
  return "noxmmreg";
2306
}
2307

2308 2309 2310 2311 2312

const char* NameConverter::NameInCode(byte* addr) const {
  // X64 does not embed debug strings at the moment.
  UNREACHABLE();
  return "";
2313 2314
}

2315

2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327
//------------------------------------------------------------------------------

Disassembler::Disassembler(const NameConverter& converter)
    : converter_(converter) { }

Disassembler::~Disassembler() { }


int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
                                    byte* instruction) {
  DisassemblerX64 d(converter_, CONTINUE_ON_UNIMPLEMENTED_OPCODE);
  return d.InstructionDecode(buffer, instruction);
2328 2329
}

2330 2331 2332 2333

// The X64 assembler does not use constant pools.
int Disassembler::ConstantPoolSizeAt(byte* instruction) {
  return -1;
2334 2335
}

2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350

void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
  NameConverter converter;
  Disassembler d(converter);
  for (byte* pc = begin; pc < end;) {
    v8::internal::EmbeddedVector<char, 128> buffer;
    buffer[0] = '\0';
    byte* prev_pc = pc;
    pc += d.InstructionDecode(buffer, pc);
    fprintf(f, "%p", prev_pc);
    fprintf(f, "    ");

    for (byte* bp = prev_pc; bp < pc; bp++) {
      fprintf(f, "%02x", *bp);
    }
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    for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
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      fprintf(f, "  ");
    }
    fprintf(f, "  %s\n", buffer.start());
  }
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}
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}  // namespace disasm
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#endif  // V8_TARGET_ARCH_X64