The {shrd} instruction was implemented with switched {src} and {dst}
registers. The only users ({ShrPair} and {SarPair}) "fixed" this by
passing switched registers again.

This CL cleans this up, and adds some DCHECKs that are required for the
logic in the pair-wise shifts to work correctly.
Also, avoid an unneccessary shift by 0 on ia32.

R=jkummerow@chromium.org

Bug: v8:9919
Change-Id: I8ec31526f5adcea68f6f6ef7c8076ac2e5589a5f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1899767Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64779}