- 05 Sep, 2016 1 commit
-
-
georgia.kouveli authored
Generate a flag-setting instruction for a binary operation when the result is tested for equality/inequality to zero. BUG= Review-Url: https://codereview.chromium.org/2315453002 Cr-Commit-Position: refs/heads/master@{#39183}
-
- 08 Aug, 2016 1 commit
-
-
ahaas authored
This CL changes the semantics of FloatXXSub to match the semantics of the semantics of FloatXXSubPreserveNan. Therefore there is no need anymore for the FloatXXSubPreserveNan operators. The optimizations in VisitFloatXXSub which are removed in this CL have already been moved to machine-operator-reducer.cc in https://codereview.chromium.org/2226663002 R=bmeurer@chromium.org Review-Url: https://codereview.chromium.org/2220973002 Cr-Commit-Position: refs/heads/master@{#38437}
-
- 05 Aug, 2016 1 commit
-
-
ahaas authored
R=bmeurer@chromium.org Review-Url: https://codereview.chromium.org/2215403002 Cr-Commit-Position: refs/heads/master@{#38399}
-
- 22 Jul, 2016 1 commit
-
-
bmeurer authored
So far we don't have a useful way to inline Math.max or Math.min in TurboFan optimized code. This adds new operators NumberMax and NumberMin and changes the Float64Max/Float64Min operators to have JavaScript semantics instead of the C++ semantics that it had previously. This also removes support for recognizing the tenary case in the CommonOperatorReducer, since that doesn't seem to have any positive impact (and actually doesn't show up in regular JavaScript, where people use Math.max/Math.min instead). Drive-by-fix: Also nuke the unused Float32Max/Float32Min operators. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/2170343002 Cr-Commit-Position: refs/heads/master@{#37971}
-
- 18 Jul, 2016 1 commit
-
-
georgia.kouveli authored
Based on 317dc057. BUG= Review-Url: https://codereview.chromium.org/2152253002 Cr-Commit-Position: refs/heads/master@{#37828}
-
- 27 May, 2016 1 commit
-
-
georgia.kouveli authored
Adding optional operators for FNeg for WebAssembly, as the current implementation was significantly suboptimal for ARM. Review-Url: https://codereview.chromium.org/2011303002 Cr-Commit-Position: refs/heads/master@{#36544}
-
- 19 May, 2016 2 commits
-
-
pierre.langlois authored
This patch is a follow up to https://codereview.chromium.org/1972103002/ adding support for the `Operand_R_LSL_I` addressing mode to loads and stores for ARM. Just as the ARM64 implementation, the shift + load/store pattern is only really relevant to the interpreter. For this reason, this patch does not add support for the other addressing modes (`R_LSR_I`, `R_ASR_I` and `R_ROR_I`) as I haven't seen those pattern being generated. Additionally, the optimization is restricted 32 bit loads and stores. kind = BYTECODE_HANDLER name = Star compiler = turbofan Instructions (size = 40) 0x22a5f860 0 e2851001 add r1, r5, #1 0x22a5f864 4 e19610d1 ldrsb r1, [r6, +r1] 0x22a5f868 8 e1a0200b mov r2, fp 0x22a5f86c 12 e7820101 str r0, [r2, +r1, lsl #2] ^^^^^^^^^^^^^^^^^^^^^^^^^ 0x22a5f870 16 e2855002 add r5, r5, #2 0x22a5f874 20 e7d61005 ldrb r1, [r6, +r5] 0x22a5f878 24 e7981101 ldr r1, [r8, +r1, lsl #2] ^^^^^^^^^^^^^^^^^^^^^^^^^ 0x22a5f87c 28 e12fff11 bx r1 BUG= Review-Url: https://codereview.chromium.org/1974263002 Cr-Commit-Position: refs/heads/master@{#36381}
-
jacob.bramley authored
The MLS instruction is available in all ARMv7 devices, and in no ARMv6 devices, aside from the usual ARMv6T2 caveat. We don't need a separate feature flag for it. BUG= Review-Url: https://codereview.chromium.org/1988133004 Cr-Commit-Position: refs/heads/master@{#36378}
-
- 06 Apr, 2016 1 commit
-
-
jacob.bramley authored
BUG= Review URL: https://codereview.chromium.org/1862993002 Cr-Commit-Position: refs/heads/master@{#35292}
-
- 16 Feb, 2016 1 commit
-
-
martyn.capewell authored
Support SBFX in the instruction selector for sign-extension patterns like Sar(Shl(x, a), b), where a and b are immediate values. BUG= Review URL: https://codereview.chromium.org/1695293002 Cr-Commit-Position: refs/heads/master@{#34029}
-
- 15 Feb, 2016 1 commit
-
-
martyn.capewell authored
Improve instruction selector for mask and shift operations by using cheaper instructions where possible, in preference to UBFX. Reverted because it was suspected of causing a couple of flaky tests to fail, but investigation suggests this is unlikely. Original review: https://codereview.chromium.org/1677023002 BUG= Review URL: https://codereview.chromium.org/1684073006 Cr-Commit-Position: refs/heads/master@{#33988}
-
- 12 Feb, 2016 1 commit
-
-
epertoso authored
This was causing code like: REX.W cmpq r9,r8 setzl r8l movzxbl r8,r8 REX.W cmpq r8,0x0 jz 185 (note the cmpq instead of cmpl above) on x64 instead of: REX.W cmpq r9,r8 jnz 149 http://crrev.com/1677503002 is now obsolete and has been reverted. Review URL: https://codereview.chromium.org/1685183003 Cr-Commit-Position: refs/heads/master@{#33934}
-
- 09 Feb, 2016 2 commits
-
-
martyn.capewell authored
Revert of [turbofan] ARM: Improve AND instruction selection (patchset #1 id:1 of https://codereview.chromium.org/1677023002/ ) Reason for revert: Possibly causing Mozilla test failures - will investigate. Original issue's description: > [turbofan] ARM: Improve AND instruction selection > > Improve instruction selector for mask and shift operations by using cheaper > instructions where possible, in preference to UBFX. > > BUG= > > Committed: https://crrev.com/53d9c12977f07f55b6f2a72128b8d02c4c857845 > Cr-Commit-Position: refs/heads/master@{#33843} TBR=bmeurer@chromium.org,jarin@chromium.org,danno@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review URL: https://codereview.chromium.org/1681953003 Cr-Commit-Position: refs/heads/master@{#33850}
-
martyn.capewell authored
Improve instruction selector for mask and shift operations by using cheaper instructions where possible, in preference to UBFX. BUG= Review URL: https://codereview.chromium.org/1677023002 Cr-Commit-Position: refs/heads/master@{#33843}
-
- 11 Dec, 2015 1 commit
-
-
jarin authored
Review URL: https://codereview.chromium.org/1513383003 Cr-Commit-Position: refs/heads/master@{#32803}
-
- 10 Dec, 2015 1 commit
-
-
jarin authored
MachineType is now a class with two enum fields: - MachineRepresentation - MachineSemantic Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably: - register allocator now uses just the representation. - Phi and Select nodes only refer to representations. Review URL: https://codereview.chromium.org/1513543003 Cr-Commit-Position: refs/heads/master@{#32738}
-
- 30 Nov, 2015 1 commit
-
-
vogelheim authored
R=bmeurer@chromium.org, mstarzinger@chromium.org BUG=chromium:508898 LOG=Y Review URL: https://codereview.chromium.org/1477413002 Cr-Commit-Position: refs/heads/master@{#32400}
-
- 29 Oct, 2015 1 commit
-
-
mstarzinger authored
R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1424983003 Cr-Commit-Position: refs/heads/master@{#31646}
-
- 26 Oct, 2015 1 commit
-
-
rmcilroy authored
Adds support for loading from and storing to outer context variables. Also adds support for declaring functions on contexts and locals. Finally, fixes a couple of issues with StaContextSlot where we weren't emitting the write barrier and therefore would crash in the GC. Also added code so that --print-bytecode will output the function name before the bytecodes, and replaces MachineType with StoreRepresentation in RawMachineAssembler::Store and updates tests. BUG=v8:4280 LOG=N Review URL: https://codereview.chromium.org/1425633002 Cr-Commit-Position: refs/heads/master@{#31584}
-
- 24 Sep, 2015 1 commit
-
-
pierre.langlois authored
This patch checks the type of the lhs operand of a floating point comparison for ARM, and commutes the operands if it is #0.0. It allows us to optimize a comparison with zero, as the vcmp instruction accepts #0.0 as rhs operand. Code before for "0.0 < 0.123": ------------------------------ movw ip, #29360 movt ip, #37224 movw r9, #31981 movt r9, #16319 vmov d0, ip, r9 mov ip, #0 vmov d1, ip, ip vcmp.f64 d1, d0 vmrs APSR, FPSCR bcc +12 Code after: ----------- movw ip, #29360 movt ip, #37224 movw r9, #31981 movt r9, #16319 vmov d0, ip, r9 vcmp.f64 d0, #0.0 vmrs APSR, FPSCR bgt +12 BUG= Review URL: https://codereview.chromium.org/1361913003 Cr-Commit-Position: refs/heads/master@{#30911}
-
- 08 Apr, 2015 1 commit
-
-
Benedikt Meurer authored
These operators compute the absolute floating point value of some arbitrary input, and are implemented without any branches (i.e. using vabs on arm, and andps/andpd on x86). R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/1066393002 Cr-Commit-Position: refs/heads/master@{#27662}
-
- 30 Mar, 2015 1 commit
-
-
bmeurer authored
This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
-
- 20 Mar, 2015 1 commit
-
-
Benedikt Meurer authored
R=dcarney@chromium.org, yangguo@chromium.org BUG=v8:3952 LOG=n Review URL: https://codereview.chromium.org/1021183002 Cr-Commit-Position: refs/heads/master@{#27329}
-
- 15 Jan, 2015 1 commit
-
-
baptiste.afsa authored
R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/850073002 Cr-Commit-Position: refs/heads/master@{#26066}
-
- 26 Nov, 2014 3 commits
-
-
Benedikt Meurer authored
TEST=mjsunit,unittests R=svenpanne@chromium.org Committed: https://chromium.googlesource.com/v8/v8/+/2aed882fe74dbf9210159babe30fedccd900e7cf Review URL: https://codereview.chromium.org/762493006 Cr-Commit-Position: refs/heads/master@{#25515}
-
machenbach authored
Revert of [arm] Fix recognition of VNEG. (patchset #3 id:40001 of https://codereview.chromium.org/762493006/) Reason for revert: Breaks arm compilation. Original issue's description: > [arm] Fix recognition of VNEG. > > TEST=mjsunit,unittests > R=svenpanne@chromium.org > > Committed: https://chromium.googlesource.com/v8/v8/+/2aed882fe74dbf9210159babe30fedccd900e7cf TBR=svenpanne@chromium.org,bmeurer@chromium.org NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/751653004 Cr-Commit-Position: refs/heads/master@{#25514}
-
Benedikt Meurer authored
TEST=mjsunit,unittests R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/762493006 Cr-Commit-Position: refs/heads/master@{#25513}
-
- 10 Nov, 2014 1 commit
-
-
bmeurer@chromium.org authored
TEST=cctest,msjunit/asm,unittests R=jarin@chromium.org Review URL: https://codereview.chromium.org/709123005 Cr-Commit-Position: refs/heads/master@{#25228} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 03 Nov, 2014 1 commit
-
-
bmeurer@chromium.org authored
TEST=cctest,mjsunit,unittests R=jarin@chromium.org Review URL: https://codereview.chromium.org/697663003 Cr-Commit-Position: refs/heads/master@{#25061} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25061 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 23 Oct, 2014 1 commit
-
-
bmeurer@chromium.org authored
TEST=cctest,unittests R=dcarney@chromium.org Review URL: https://codereview.chromium.org/669133004 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24832 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 17 Oct, 2014 1 commit
-
-
bmeurer@chromium.org authored
BFC requires same register for input and output and causes introduction of some unneccesary gap moves. TEST=unittests,mjsunit R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/658283003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24678 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 14 Oct, 2014 1 commit
-
-
bmeurer@chromium.org authored
TEST=cctest,mjsunit,unittests R=dcarney@chromium.org, svenpanne@chromium.org Review URL: https://codereview.chromium.org/654833002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24595 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 01 Oct, 2014 2 commits
-
-
titzer@chromium.org authored
R=bmeurer@chromium.org, mstarzinger@chromium.org BUG= Review URL: https://codereview.chromium.org/620773003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24356 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
bmeurer@chromium.org authored
As per discussion on the V8 team, this is the place we want them to live, not following the Chrome Style Guide for this. BUG=v8:3489 LOG=y R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/615393002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24350 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 30 Sep, 2014 1 commit
-
-
bmeurer@chromium.org authored
Review URL: https://codereview.chromium.org/618643002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24319 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 24 Sep, 2014 1 commit
-
-
bmeurer@chromium.org authored
LOG=n BUG=v8:3589 TEST=compiler-unittests,cctest R=titzer@chromium.org Review URL: https://codereview.chromium.org/596703004 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24179 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 01 Sep, 2014 1 commit
-
-
bmeurer@chromium.org authored
BUG=v8:3489 LOG=n R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/530693002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23551 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 27 Aug, 2014 1 commit
-
-
jarin@chromium.org authored
BUG= R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/505133002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23467 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 26 Aug, 2014 1 commit
-
-
bmeurer@chromium.org authored
This is the bare minimum required to support typed arrays. Support for working with float32 values will be added based on this. TEST=compiler-unittests,cctest R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/500343002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23386 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-
- 25 Aug, 2014 1 commit
-
-
bmeurer@chromium.org authored
Also rename the arch opcodes to match their native counterparts. TEST=compiler-unittests,cctest R=jarin@chromium.org Review URL: https://codereview.chromium.org/505713002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23345 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
-