1. 05 Sep, 2016 1 commit
  2. 08 Aug, 2016 1 commit
  3. 05 Aug, 2016 1 commit
  4. 22 Jul, 2016 1 commit
    • bmeurer's avatar
      [turbofan] Change Float64Max/Float64Min to JavaScript semantics. · ba092fb0
      bmeurer authored
      So far we don't have a useful way to inline Math.max or Math.min in
      TurboFan optimized code. This adds new operators NumberMax and NumberMin
      and changes the Float64Max/Float64Min operators to have JavaScript
      semantics instead of the C++ semantics that it had previously.
      
      This also removes support for recognizing the tenary case in the
      CommonOperatorReducer, since that doesn't seem to have any positive
      impact (and actually doesn't show up in regular JavaScript, where
      people use Math.max/Math.min instead).
      
      Drive-by-fix: Also nuke the unused Float32Max/Float32Min operators.
      
      R=jarin@chromium.org
      
      Review-Url: https://codereview.chromium.org/2170343002
      Cr-Commit-Position: refs/heads/master@{#37971}
      ba092fb0
  5. 18 Jul, 2016 1 commit
  6. 27 May, 2016 1 commit
  7. 19 May, 2016 2 commits
    • pierre.langlois's avatar
      [turbofan] ARM: Support shifted indexes in loads and stores · 11b661f4
      pierre.langlois authored
      This patch is a follow up to https://codereview.chromium.org/1972103002/
      adding support for the `Operand_R_LSL_I` addressing mode to loads and
      stores for ARM.
      
      Just as the ARM64 implementation, the shift + load/store pattern is only
      really relevant to the interpreter. For this reason, this patch does not
      add support for the other addressing modes (`R_LSR_I`, `R_ASR_I` and
      `R_ROR_I`) as I haven't seen those pattern being generated. Additionally,
      the optimization is restricted 32 bit loads and stores.
      
      kind = BYTECODE_HANDLER
      name = Star
      compiler = turbofan
      Instructions (size = 40)
      0x22a5f860     0  e2851001       add r1, r5, #1
      0x22a5f864     4  e19610d1       ldrsb r1, [r6, +r1]
      0x22a5f868     8  e1a0200b       mov r2, fp
      0x22a5f86c    12  e7820101       str r0, [r2, +r1, lsl #2]
                                       ^^^^^^^^^^^^^^^^^^^^^^^^^
      0x22a5f870    16  e2855002       add r5, r5, #2
      0x22a5f874    20  e7d61005       ldrb r1, [r6, +r5]
      0x22a5f878    24  e7981101       ldr r1, [r8, +r1, lsl #2]
                                       ^^^^^^^^^^^^^^^^^^^^^^^^^
      0x22a5f87c    28  e12fff11       bx r1
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/1974263002
      Cr-Commit-Position: refs/heads/master@{#36381}
      11b661f4
    • jacob.bramley's avatar
      [arm] Remove CpuFeature::MLS. · feeaac40
      jacob.bramley authored
      The MLS instruction is available in all ARMv7 devices, and in no ARMv6
      devices, aside from the usual ARMv6T2 caveat. We don't need a separate
      feature flag for it.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/1988133004
      Cr-Commit-Position: refs/heads/master@{#36378}
      feeaac40
  8. 06 Apr, 2016 1 commit
  9. 16 Feb, 2016 1 commit
  10. 15 Feb, 2016 1 commit
  11. 12 Feb, 2016 1 commit
  12. 09 Feb, 2016 2 commits
  13. 11 Dec, 2015 1 commit
  14. 10 Dec, 2015 1 commit
    • jarin's avatar
      [turbofan] Make MachineType a pair of enums. · bb2a830d
      jarin authored
      MachineType is now a class with two enum fields:
      - MachineRepresentation
      - MachineSemantic
      
      Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
      - register allocator now uses just the representation.
      - Phi and Select nodes only refer to representations.
      
      Review URL: https://codereview.chromium.org/1513543003
      
      Cr-Commit-Position: refs/heads/master@{#32738}
      bb2a830d
  15. 30 Nov, 2015 1 commit
  16. 29 Oct, 2015 1 commit
  17. 26 Oct, 2015 1 commit
    • rmcilroy's avatar
      [Interpreter] Add support for loading from / storing to outer context variables. · c0c214da
      rmcilroy authored
      Adds support for loading from and storing to outer context
      variables. Also adds support for declaring functions on contexts and
      locals. Finally, fixes a couple of issues with StaContextSlot where
      we weren't emitting the write barrier and therefore would crash in the
      GC.
      
      Also added code so that --print-bytecode will output the
      function name before the bytecodes, and replaces MachineType with StoreRepresentation in RawMachineAssembler::Store and updates tests.
      
      BUG=v8:4280
      LOG=N
      
      Review URL: https://codereview.chromium.org/1425633002
      
      Cr-Commit-Position: refs/heads/master@{#31584}
      c0c214da
  18. 24 Sep, 2015 1 commit
    • pierre.langlois's avatar
      [arm] Optimize vcmp when lhs operand is #0.0 · d1472d65
      pierre.langlois authored
      This patch checks the type of the lhs operand of a floating point
      comparison for ARM, and commutes the operands if it is #0.0.  It allows
      us to optimize a comparison with zero, as the vcmp instruction
      accepts #0.0 as rhs operand.
      
      Code before for "0.0 < 0.123":
      ------------------------------
      movw ip, #29360
      movt ip, #37224
      movw r9, #31981
      movt r9, #16319
      vmov d0, ip, r9
      mov ip, #0
      vmov d1, ip, ip
      vcmp.f64 d1, d0
      vmrs APSR, FPSCR
      bcc +12
      
      Code after:
      -----------
      movw ip, #29360
      movt ip, #37224
      movw r9, #31981
      movt r9, #16319
      vmov d0, ip, r9
      vcmp.f64 d0, #0.0
      vmrs APSR, FPSCR
      bgt +12
      
      BUG=
      
      Review URL: https://codereview.chromium.org/1361913003
      
      Cr-Commit-Position: refs/heads/master@{#30911}
      d1472d65
  19. 08 Apr, 2015 1 commit
  20. 30 Mar, 2015 1 commit
    • bmeurer's avatar
      [turbofan] Add backend support for float32 operations. · 8dad78cd
      bmeurer authored
      This adds the basics necessary to support float32 operations in TurboFan.
      The actual functionality required to detect safe float32 operations will
      be added based on this later. Therefore this does not affect production
      code except for some cleanup/refactoring.
      
      In detail, this patchset contains the following features:
      - Add support for float32 operations to arm, arm64, ia32 and x64
        backends.
      - Add float32 machine operators.
      - Add support for float32 constants to simplified lowering.
      - Handle float32 representation for phis in simplified lowering.
      
      In addition, contains the following (related) cleanups:
      - Fix/unify naming of backend instructions.
      - Use AVX comparisons when available.
      - Extend ArchOpcodeField to 9 bits (required for arm64).
      - Refactor some code duplication in instruction selectors.
      
      BUG=v8:3589
      LOG=n
      R=dcarney@chromium.org
      
      Review URL: https://codereview.chromium.org/1044793002
      
      Cr-Commit-Position: refs/heads/master@{#27509}
      8dad78cd
  21. 20 Mar, 2015 1 commit
  22. 15 Jan, 2015 1 commit
  23. 26 Nov, 2014 3 commits
  24. 10 Nov, 2014 1 commit
  25. 03 Nov, 2014 1 commit
  26. 23 Oct, 2014 1 commit
  27. 17 Oct, 2014 1 commit
  28. 14 Oct, 2014 1 commit
  29. 01 Oct, 2014 2 commits
  30. 30 Sep, 2014 1 commit
  31. 24 Sep, 2014 1 commit
  32. 01 Sep, 2014 1 commit
  33. 27 Aug, 2014 1 commit
  34. 26 Aug, 2014 1 commit
  35. 25 Aug, 2014 1 commit