- 14 Nov, 2016 1 commit
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tebbi authored
This CL enables precise source positions for all V8 compilers. It merges compiler::SourcePosition and internal::SourcePosition to a single class used throughout the codebase. The new internal::SourcePosition instances store an id identifying an inlined function in addition to a script offset. SourcePosition::InliningId() refers to a the new table DeoptimizationInputData::InliningPositions(), which provides the following data for every inlining id: - The inlined SharedFunctionInfo as an offset into DeoptimizationInfo::LiteralArray - The SourcePosition of the inlining. Recursively, this yields the full inlining stack. Before the Code object is created, the same information can be found in CompilationInfo::inlined_functions(). If SourcePosition::InliningId() is SourcePosition::kNotInlined, it refers to the outer (non-inlined) function. So every SourcePosition has full information about its inlining stack, as long as the corresponding Code object is known. The internal represenation of a source position is a positive 64bit integer. All compilers create now appropriate source positions for inlined functions. In the case of Turbofan, this required using AstGraphBuilderWithPositions for inlined functions too. So this class is now moved to a header file. At the moment, the additional information in source positions is only used in --trace-deopt and --code-comments. The profiler needs to be updated, at the moment it gets the correct script offsets from the deopt info, but the wrong script id from the reconstructed deopt stack, which can lead to wrong outputs. This should be resolved by making the profiler use the new inlining information for deopts. I activated the inlined deoptimization tests in test-cpu-profiler.cc for Turbofan, changing them to a case where the deopt stack and the inlining position agree. It is currently still broken for other cases. The following additional changes were necessary: - The source position table (internal::SourcePositionTableBuilder etc.) supports now 64bit source positions. Encoding source positions in a single 64bit int together with the difference encoding in the source position table results in very little overhead for the inlining id, since only 12% of the source positions in Octane have a changed inlining id. - The class HPositionInfo was effectively dead code and is now removed. - SourcePosition has new printing and information facilities, including computing a full inlining stack. - I had to rename compiler/source-position.{h,cc} to compiler/compiler-source-position-table.{h,cc} to avoid clashes with the new src/source-position.cc file. - I wrote the new wrapper PodArray for ByteArray. It is a template working with any POD-type. This is used in DeoptimizationInputData::InliningPositions(). - I removed HInlinedFunctionInfo and HGraph::inlined_function_infos, because they were only used for the now obsolete Crankshaft inlining ids. - Crankshaft managed a list of inlined functions in Lithium: LChunk::inlined_functions. This is an analog structure to CompilationInfo::inlined_functions. So I removed LChunk::inlined_functions and made Crankshaft use CompilationInfo::inlined_functions instead, because this was necessary to register the offsets into the literal array in a uniform way. This is a safe change because LChunk::inlined_functions has no other uses and the functions in CompilationInfo::inlined_functions have a strictly longer lifespan, being created earlier (in Hydrogen already). BUG=v8:5432 Review-Url: https://codereview.chromium.org/2451853002 Cr-Commit-Position: refs/heads/master@{#40975}
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- 11 Nov, 2016 1 commit
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ulan authored
BUG=v8:5614 Review-Url: https://codereview.chromium.org/2493173002 Cr-Commit-Position: refs/heads/master@{#40916}
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- 23 Sep, 2016 1 commit
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jacob.bramley authored
CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
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- 08 Sep, 2016 1 commit
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martyn.capewell authored
Reason for revert: Breaks g++ build. Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} BUG= Review-Url: https://codereview.chromium.org/2314043002 Cr-Commit-Position: refs/heads/master@{#39264}
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- 06 Sep, 2016 4 commits
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machenbach authored
Revert of [turbofan] ARM: Implement vswp and use in gap resolver (patchset #2 id:20001 of https://codereview.chromium.org/2313803003/ ) Reason for revert: Breaks arm compilation: https://build.chromium.org/p/client.v8.ports/builders/V8%20Arm%20-%20builder/builds/3549 Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} TBR=bmeurer@chromium.org,epertoso@chromium.org,martyn.capewell@arm.com # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review-Url: https://codereview.chromium.org/2314003003 Cr-Commit-Position: refs/heads/master@{#39210}
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martyn.capewell authored
Use vswp to switch double-precision registers in the gap resolver, with fall back temp register-based code if NEON is not available. BUG= Review-Url: https://codereview.chromium.org/2313803003 Cr-Commit-Position: refs/heads/master@{#39209}
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jacob.bramley authored
ARMv6 has the same basic barriers as ARMv7+, but they are accessed using the CP15 coprocessor. This patch allows the assembler to select the appropriate instruction. This also fixes TurboFan's atomic loads and stores for ARMv6 platforms. BUG= Review-Url: https://codereview.chromium.org/2318553002 Cr-Commit-Position: refs/heads/master@{#39203}
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jacob.bramley authored
These are ARMv8 instructions that will be used in a follow-up patch. BUG= Review-Url: https://codereview.chromium.org/2273003002 Cr-Commit-Position: refs/heads/master@{#39193}
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- 18 Jul, 2016 1 commit
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bmeurer authored
So far TurboFan wasn't adding the deoptimization reasons for eager/soft deoptimization exits that can be used by either the DevTools profiler or the --trace-deopt flag. This adds basic support for deopt reasons on Deoptimize, DeoptimizeIf and DeoptimizeUnless nodes and threads through the reasons to the code generation. Also moves the DeoptReason to it's own file (to resolve include cycles) and drops unused reasons. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/2161543002 Cr-Commit-Position: refs/heads/master@{#37823}
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- 30 Jun, 2016 1 commit
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bbudge authored
-Defines SIMD128_REGISTERS for all platforms. -Adds Simd128 register information to RegisterConfiguration, and implements aliasing calculations. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2092103004 Cr-Commit-Position: refs/heads/master@{#37437}
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- 29 Jun, 2016 1 commit
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yangguo authored
R=mstarzinger@chromium.org BUG=v8:5117 Review-Url: https://codereview.chromium.org/2109613004 Cr-Commit-Position: refs/heads/master@{#37397}
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- 27 Jun, 2016 2 commits
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bbudge authored
Replaces ArchDefault method with Crankshaft and Turbofan getters. Eliminates IsAllocated method on Register, FloatRegister, DoubleRegister. Eliminates ToString method too. Changes call sites to access appropriate arch default RegisterConfiguration. LOG=N BUG= Review-Url: https://codereview.chromium.org/2092413002 Cr-Commit-Position: refs/heads/master@{#37297}
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bbudge authored
- Add a const bool kSimpleFPAliasing variable for each platform so it's easier for the compiler to eliminate dead code. - Modify RegisterAllocator to use it. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2101473002 Cr-Commit-Position: refs/heads/master@{#37288}
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- 24 Jun, 2016 1 commit
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balazs.kilvady authored
Port fc59eb8a Original commit message: Moves between operands with different representations shouldn't happen, so don't test them. This makes it easier to modify canonicalization to differentiate between floating point types, which is needed to support floating point register aliasing for ARM and MIPS. This change also expands tests to include explicit FP moves (both register and stack slot). LOG=N BUG=v8:4124 BUG=chromium:622619 Review-Url: https://codereview.chromium.org/2090993002 Cr-Commit-Position: refs/heads/master@{#37241}
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- 08 Jun, 2016 1 commit
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mtrofin authored
This improves maintainability. The Compile and Wasm benchmarks, tracking compile time, show no regression. BUG= Review-Url: https://codereview.chromium.org/2044283003 Cr-Commit-Position: refs/heads/master@{#36834}
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- 03 Jun, 2016 1 commit
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bbudge authored
- Adds names for float registers to RegisterConfiguration and uses them when we have the MachineRepresentation. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2030143002 Cr-Commit-Position: refs/heads/master@{#36712}
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- 01 Jun, 2016 1 commit
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bbudge authored
Adds instructions for ARM to push floats. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2024443002 Cr-Commit-Position: refs/heads/master@{#36654}
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- 19 May, 2016 1 commit
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binji authored
R=jarin@chromium.org,bmeurer@chromium.org Review-Url: https://codereview.chromium.org/1993033002 Cr-Commit-Position: refs/heads/master@{#36380}
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- 13 May, 2016 1 commit
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mstarzinger authored
This makes the profiler reconstruct inlined function frames at eager deopt points from the deoptimization data. The main goal of this is to remove the last side-channel where Crankshaft communicates directly to the profiler. This is the last preparatory step towards deprecating the side-channel in question. R=yangguo@chromium.org Review-Url: https://codereview.chromium.org/1973993002 Cr-Commit-Position: refs/heads/master@{#36229}
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- 11 May, 2016 1 commit
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mstarzinger authored
This passes the inlining_id of deoptimization points via the relocation info instead of via a side-channel to the CPU profiler. This is one step towards deprecating the side-channel in question and avoid the need for performing a lookup of the return address of the deopt point. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/1956693002 Cr-Commit-Position: refs/heads/master@{#36177}
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- 09 May, 2016 1 commit
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bbudge authored
Changes some platform specific class names and uses typedefs to define FloatRegister, DoubleRegister, etc. This will be needed to do register allocation on ARM/MIPS where registers combine to form larger registers. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/1954953002 Cr-Commit-Position: refs/heads/master@{#36117}
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- 06 Apr, 2016 1 commit
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jacob.bramley authored
BUG= Review URL: https://codereview.chromium.org/1862993002 Cr-Commit-Position: refs/heads/master@{#35292}
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- 02 Mar, 2016 1 commit
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rmcilroy authored
Add support to log source position offsets to the profiler. As part of this change PositionsRecorder is split into two, with the subset needed by log.cc moved into log.h and the remainder kept in assembler.h as AssemblerPositionsRecorder. The interpreter's source position table builder is updated to log positions when the profiler is active. BUG=v8:4766 LOG=N Review URL: https://codereview.chromium.org/1737043002 Cr-Commit-Position: refs/heads/master@{#34416}
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- 17 Feb, 2016 2 commits
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binji authored
This is not currently implemented in the simulator, just the assembler and disassembler. BUG=v8:4614 LOG=y Review URL: https://codereview.chromium.org/1699173003 Cr-Commit-Position: refs/heads/master@{#34093}
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bbudge authored
Adds kSimd128 to MachineRepresentation. Adds a Simd128Register concept that's platform independent. Adds UntaggedSimd128 to types.h. LOG=N BUG=v8:4124 Review URL: https://codereview.chromium.org/1693963004 Cr-Commit-Position: refs/heads/master@{#34089}
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- 16 Feb, 2016 1 commit
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rodolph.perfetta authored
Let me know if this is not the right approach Review URL: https://codereview.chromium.org/1698483002 Cr-Commit-Position: refs/heads/master@{#34028}
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- 06 Feb, 2016 2 commits
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jing.bao authored
BUG= Review URL: https://codereview.chromium.org/1627263002 Cr-Commit-Position: refs/heads/master@{#33797}
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jing.bao authored
BUG= Review URL: https://codereview.chromium.org/1628133002 Cr-Commit-Position: refs/heads/master@{#33796}
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- 16 Jan, 2016 1 commit
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ahaas authored
The new operator converts a float32 input to int32 through truncation. I provide implementations of the new operator for x64, ia32, arm, arm64, mips, mips64, and x87. @v8-ppc-ports, can you please take care of the ppc implementation? R=titzer@chromium.org, v8-arm-ports@googlegroups.com, v8-mips-ports@googlegroups.com, weiliang.lin@intel.com Review URL: https://codereview.chromium.org/1583323004 Cr-Commit-Position: refs/heads/master@{#33346}
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- 15 Jan, 2016 1 commit
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mstarzinger authored
This splits out the SourcePosition class into a separate header file. Reason for this refactoring is that said class is mostly used by the Crankshaft compiler and not needed for all compilers. Also having the assembler depend on the class creates a dependency cycle. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1581083009 Cr-Commit-Position: refs/heads/master@{#33325}
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- 02 Dec, 2015 1 commit
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yangguo authored
The new step-in implementation no longer tries to predict the step-in target, so we don't need the arguments count nor call type anymore. R=verwaest@chromium.org Review URL: https://codereview.chromium.org/1484893003 Cr-Commit-Position: refs/heads/master@{#32516}
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- 27 Nov, 2015 1 commit
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jochen authored
Requires passing an explicit Isolate* to a bunch of static Assembler methods. BUG=v8:2487 R=yangguo@chromium.org,jkummerow@chromium.org LOG=n Review URL: https://codereview.chromium.org/1474323002 Cr-Commit-Position: refs/heads/master@{#32376}
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- 25 Nov, 2015 3 commits
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ahaas authored
The Float32RoundTruncate operator rounds float32 numbers towards zero. The operator is currently implemented on x64, ia32, arm, and arm64. Additionally I added support for the float32 vrintz, vrintn, and vrinta instructions to the arm simulator. R=titzer@chromium.org Review URL: https://codereview.chromium.org/1468303005 Cr-Commit-Position: refs/heads/master@{#32301}
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ahaas authored
The Float32RoundUp operator rounds float32 numbers towards infinity. The operator is currently implemented on x64, ia32, arm, and arm64. R=titzer@chromium.org Review URL: https://codereview.chromium.org/1474963002 Cr-Commit-Position: refs/heads/master@{#32262}
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ahaas authored
I implemented the optional Float32RoundDown operator on x64, ia32, arm, and arm64. For arm I also had to adjust the simulator. R=titzer@chromium.org Review URL: https://codereview.chromium.org/1471913006 Cr-Commit-Position: refs/heads/master@{#32261}
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- 07 Oct, 2015 1 commit
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mstarzinger authored
This removes the include of compiler.h from all our assemblers, which was only needed for the SourcePosition class. R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/1397493002 Cr-Commit-Position: refs/heads/master@{#31157}
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- 02 Oct, 2015 3 commits
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf Cr-Commit-Position: refs/heads/master@{#31075} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31087}
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danno authored
Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on MIPS Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} > > Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf > Cr-Commit-Position: refs/heads/master@{#31075} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1380863004 Cr-Commit-Position: refs/heads/master@{#31083}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31075}
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- 30 Sep, 2015 1 commit
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mstarzinger authored
This enables linter checking for "readability/namespace" violations during presubmit and instead marks the few known exceptions that we allow explicitly. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1371083003 Cr-Commit-Position: refs/heads/master@{#31019}
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