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  1. 14 Oct, 2021 1 commit
  3. 07 Oct, 2021 1 commit
  5. 21 Sep, 2021 1 commit
  7. 20 Sep, 2021 1 commit
    • Ng Zhi An's avatar
      [wasm-simd][liftoff] Fix i64x2.mul codegen bug · f7ac5a29
      Ng Zhi An authored 
      When dst != lhs, we moved lhs to dst, but dst can be == rhs, so we would
overwrite rhs, and end up comparing lhs with itself, always returning
false. We handle the different aliasing cases in the macro-assembler
function I64x2GtS, to simplify the checks in Liftoff a little bit.
TurboFan does not need to change as it will require dst == lhs when AVX
is not supported.

Bug: v8:12237
Change-Id: Icefa6eb79083c003e93dbbd11ccc419aae4b15d3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3169312Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#76945}
      f7ac5a29
  9. 17 Sep, 2021 1 commit
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  15. 07 Sep, 2021 1 commit
  17. 26 Aug, 2021 2 commits
  19. 24 Aug, 2021 2 commits
  21. 19 Aug, 2021 3 commits
  23. 17 Aug, 2021 2 commits
  25. 13 Aug, 2021 1 commit
  27. 12 Aug, 2021 3 commits
  29. 10 Aug, 2021 1 commit
    • Ng Zhi An's avatar
      [wasm-simd] Optimize i64x2.shr_s · 10d4418f
      Ng Zhi An authored 
      Use logical shifts to emulate arithmetic shift, by first adding a bias
to make all signed values unsigned, then subtracting the shifted bias.
Details are in code comments for SharedTurboAssembler::I64x2ShrS.

Also refactor ia32 (which was already using this algorithm) to use the
shared macro-assembler function. And convert Liftoff's implementation as
well.

Bug: v8:12058
Change-Id: Ia1fd5fe5a9a0b7a7f31c426d4112256c8bf7021b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3083291
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Cr-Commit-Position: refs/heads/master@{#76209}
      10d4418f
  31. 12 May, 2021 1 commit
    • Ng Zhi An's avatar
      Reland "[wasm-simd][x64][ia32] Factor f64x2.replace_lane into shared code" · f9a2435a
      Ng Zhi An authored 
      This is a reland of 3356078a.

The fix is in PS2:
- fix the DCHECK to be triggered only if dst != src, the dcheck
  is meant to prevent rep from being overwritten, which happens only
  if dst != src
- fix instruction selector for f64x2.replace_lane, require SameAsFirst
  only for non-AVX, which makes dst == src, saving a move
- on x64 we also require all registers, since the macro-assembler
  helper only handles registers

Original change's description:
> [wasm-simd][x64][ia32] Factor f64x2.replace_lane into shared code
>
> This pblendw/movlhps combination has lower latency and requires less
> unop than pinsrq (1 v.s. 2).
>
> Bug: v8:11589
> Change-Id: I770b0c20a286774afefbac5ef0adffe463318f21
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2828871
> Reviewed-by: Bill Budge <bbudge@chromium.org>
> Commit-Queue: Zhi An Ng <zhin@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#74049}

Bug: v8:11589
Change-Id: I51cba0539d5241242dc4d7d971ede1940b9ac1fd
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2842264
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: 's avatarBill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#74545}
      f9a2435a
  33. 10 May, 2021 2 commits
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  53. 25 Mar, 2021 3 commits