Commit 61203cb9 authored by Ng Zhi An's avatar Ng Zhi An Committed by V8 LUCI CQ

[ia32][x64] Enable CPU feature in Assembler if supported

x64 already had logic to enable a lower CPU extension if a higher
level one was supported. Add this to ia32. And also add SSSE3->SSE3
logic.

Drive-by cleanup to remove an extra CpuFeatureScope.

Bug: v8:11154
Change-Id: I12e3aa990cc07149da213911c624468a39f4e1a3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3212811Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#77291}
parent fed33f90
......@@ -324,6 +324,15 @@ Assembler::Assembler(const AssemblerOptions& options,
std::unique_ptr<AssemblerBuffer> buffer)
: AssemblerBase(options, std::move(buffer)) {
reloc_info_writer.Reposition(buffer_start_ + buffer_->size(), pc_);
if (CpuFeatures::IsSupported(SSE4_2)) {
EnableCpuFeature(SSE4_1);
}
if (CpuFeatures::IsSupported(SSE4_1)) {
EnableCpuFeature(SSSE3);
}
if (CpuFeatures::IsSupported(SSSE3)) {
EnableCpuFeature(SSE3);
}
}
void Assembler::GetCode(Isolate* isolate, CodeDesc* desc,
......
......@@ -1139,7 +1139,6 @@ void SharedTurboAssembler::S128Load8Splat(XMMRegister dst, Operand src,
vpshufb(dst, dst, scratch);
} else {
CpuFeatureScope ssse4_scope(this, SSE4_1);
CpuFeatureScope ssse3_scope(this, SSSE3);
pinsrb(dst, src, uint8_t{0});
xorps(scratch, scratch);
pshufb(dst, scratch);
......
......@@ -347,6 +347,9 @@ Assembler::Assembler(const AssemblerOptions& options,
if (CpuFeatures::IsSupported(SSE4_1)) {
EnableCpuFeature(SSSE3);
}
if (CpuFeatures::IsSupported(SSSE3)) {
EnableCpuFeature(SSE3);
}
#if defined(V8_OS_WIN_X64)
if (options.collect_win64_unwind_info) {
......
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