BUG=v8:3007
LOG=N
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/88303003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@18097 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Revert "ConstantPoolSizeAt() should return number of Instructions instead, otherwise, some of the code will be treated as constant pool when printing code in ARM disassembler."

This reverts commit r16419 for breaking the ARM simulator tests.

TEST=mjsunit/regress/regress-2624
R=machenbach@chromium.org

Review URL: https://codereview.chromium.org/23531013

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16441 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

ConstantPoolSizeAt() should return number of Instructions instead, otherwise, some of the code will be treated as constant pool when printing code in ARM disassembler.

BUG=none

TEST=none
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/23654005

Patch from Bangfu Tao <bangfu.tao@samsung.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16419 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Don't check for WIN32 define. Use V8_OS_* macros whenever
possible, and if not use _WIN32.

BUG=v8:2300
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/23687003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16380 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This patch prevents taking the low/high part of a double-precision VFP register that has no corresponding single-precision VFP registers.

BUG=none
TEST=Added to test-disasm-arm.cc, test-assembler-arm.cc

Review URL: https://codereview.chromium.org/19560003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15885 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Add support for a few NEON and ARM SIMD instructions and use them for various
memcpy operations.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/17858002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/18509003

Patch from Haitao Feng <haitao.feng@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15510 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/18037002

Patch from Haitao Feng <haitao.feng@intel.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15391 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Refactoring:
 * consistent use of SmiTag/Untag
 * added a few Smi macros and helpers
Improvements
 * small optimisations (e.g. merging untag and cmp #0)
 * added fixed point to double conversion instructions for simpler conversions

More on the last point: a Smi can be seen as a fixed point number with the
a one bit fractional part. Fixed to double instructions allow us to convert
a Smi to a double without untagging.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/15085026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14724 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ulan@chromium.org
BUG=

Review URL: https://chromiumcodereview.appspot.com/13986003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14204 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=sven@chromium.org
BUG=

Review URL: https://chromiumcodereview.appspot.com/13811020

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14200 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Previously, we would disassemble some VFP instructions like this:

  vmla.f64eq d16, d17, d18

This patch moves the condition to the right place:

  vmlaeq.f64 d16, d17, d18

Spotted by Rodolph Perfetta!

BUG=none

Review URL: https://chromiumcodereview.appspot.com/12335129
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=none

Review URL: https://chromiumcodereview.appspot.com/12319113
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13748 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: https://chromiumcodereview.appspot.com/11428137
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: https://chromiumcodereview.appspot.com/11293061
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12958 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The previously-used instruction isn't guaranteed to always be undefined,
and the encoding used was conditional (failing the condition on an
undefined instruction is itself undefined and not guaranteed to
fault!). I would have like to use a more clever encoding (see bug 2963),
but we need the extra bits to encode the size of the constant pool.

BUG=security
R=ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11242002
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12791 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ulan@chromium.org

Review URL: https://chromiumcodereview.appspot.com/11116011
Patch from JF Bastien <jfb@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12737 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Also added support for the runtime detection to check if hardware supports SDIV/UDIV
Other new opportunities to exploit SDIV/UDIV will be done in separate issues.

Review URL: https://chromiumcodereview.appspot.com/10977051
Patch from Subrato K De <subratokde@codeaurora.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12646 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/9228006
Patch from Martyn Capewell <m.m.capewell@googlemail.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10498 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/9231009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10407 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=vegorov@chromium.org

Review URL: http://codereview.chromium.org/7491052

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8843 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

The constant pool was not taken into account in the test test-compiler/SplitConstantsInFullCompiler which caused random failures.

This also reverts the test code added in r8469 and r8471.

R=ricow@chromium.org

BUG=none
TEST=test-compiler/SplitConstantsInFullCompiler

Review URL: http://codereview.chromium.org//7308001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8520 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ricow@chromium.org

BUG=none
TEST=none

Review URL: http://codereview.chromium.org//7250002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@8469 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Patch from ARM Ltd.

BUG=none
TEST=added to test/cctest/test-disasm-arm.cc

Original review at http://codereview.chromium.org/7013024/.

Review URL: http://codereview.chromium.org/7013027

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This patch
- removes the unimplemented code crash when rendering invalid/unknown instructions and prints "unknown" instead.
- prints the beginning of the constant pool marker.
- adds "da" as a shortcut for "disasm".
- print hexadecimal representation of double and single registers. This makes it easier to debug move/conversion code that uses temporary int32 values in floating point registers.
- annotates the stack with short prints of the values (HeapObjects and smis),
- makes disasm take an address or a register as second argument without a third argument, which defaults to printing ten instructions.

Review URL: http://codereview.chromium.org/6676042

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7279 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7271 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7269 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Review URL: http://codereview.chromium.org/6685088

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Adds vabs instruction to simulator, assembler, disassembler and tests.

BUG=none
TEST=Added to cctest.

Review URL: http://codereview.chromium.org/6366016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

First stab at a general ARM cleanup patch. It merges ARM constants so that they can be used across simulator, assembler and disassembler, and tidies up some syntax and ambiguities.

BUG=none
TEST=none

Review URL: http://codereview.chromium.org/6274009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6483 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Improve support for vmrs/vmsr in ARM disassembler.  This is a commit of http://codereview.chromium.org/4904001 for Martyn Capewell.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5824 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Fix the ARM simulator, the ARM disassembler and extend the stop feature. 
The stop feature in the simulator now support enabling, disabling and 
counting. 

BUG=None 
TEST=None 

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5723 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr.  This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Upgraded the CodeGenerator::ToBoolean() function in the ARM backend to use complete JIT code generation and not make runtime calls to ToBool (when VFP is enabled). 

This change also includes the vcmp VFP instruction that supports a constant 0.0 as the second operand. 

Patch by Subrato K De <subratokde@codeaurora.org>



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5267 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each.
Review URL: http://codereview.chromium.org/2885002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00