- 25 Sep, 2017 1 commit
-
-
Clemens Hammacher authored
Use the (D)CHECK_{EQ,NE,GT,...} macros instead of (D)CHECK with an embedded comparison. This gives better error messages and also does the right comparison for signed/unsigned mismatches. This will allow us to reenable the readability/check cpplint check. R=jarin@chromium.org Bug: v8:6837 Change-Id: I712580c2a4326e06ee3d6d0eb4ff8c7d24f5fdb9 Reviewed-on: https://chromium-review.googlesource.com/671227 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#48135}
-
- 04 Aug, 2017 1 commit
-
-
Tobias Tebbi authored
Bug: Cq-Include-Trybots: master.tryserver.v8:v8_linux_noi18n_rel_ng Change-Id: I2e1b36303f8b9ad4a3dc4e488123e6e4ce8b02ec Reviewed-on: https://chromium-review.googlesource.com/533033 Commit-Queue: Tobias Tebbi <tebbi@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#47149}
-
- 03 Aug, 2017 1 commit
-
-
Michael Starzinger authored
This removes the obsolete {Crankshaft} factory method as it returns the same configuration as the {Turbofan} factory by now. We now consistently use {RegisterConfiguration::Default} everywhere. R=jkummerow@chromium.org BUG=v8:6408 Change-Id: I6be25774aa6714ef4dc1ef6856bb6dbc95593a29 Reviewed-on: https://chromium-review.googlesource.com/597858Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47109}
-
- 14 Jul, 2017 1 commit
-
-
Enrico Bacis authored
Returning a double from ToFloat64 could lead to problems. If value_ has the bit representation of a signaling NaN (sNaN), then returning it as double can cause the signaling bit to flip, and value_ is returned as a quiet NaN (qNaN). The usage of the Double wrapper also, makes the function ToFloat64AsInt redundant, since the Double wrapper already has the AsUint64() method, which returns an uint64_t. R=ahaas@chromium.org Change-Id: I1e627b97b2fb6110fc702fe58f2b83eb343e9ca2 Reviewed-on: https://chromium-review.googlesource.com/563215 Commit-Queue: Enrico Bacis <enricobacis@google.com> Reviewed-by:
Martyn Capewell <martyn.capewell@arm.com> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#46680}
-
- 13 Jul, 2017 1 commit
-
-
Georg Neis authored
In debug mode (SLOW_DCHECK), Handle<T>::cast accesses the object to check its type. Obviously we can no longer do that now that we run on a background thread. NOTE: I think there are other parts of TF that suffer from the same problem. I will look into fixing those as well. Bug: v8:6048, v8:6590 Change-Id: I9abfdf30f1899cdb0c8b9078b0cf71463d608251 Reviewed-on: https://chromium-review.googlesource.com/570054Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Commit-Queue: Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#46641}
-
- 30 Jun, 2017 1 commit
-
-
Leszek Swirski authored
With FCG no longer able to deoptimize, we can remove the "push" version of output frame state combine, as deoptimisation to bytecode is always the PokeAt variant. Bug: v8:6409 Change-Id: I9b6d38a7441ca834835615c238228fa8a75a027b Reviewed-on: https://chromium-review.googlesource.com/557866 Commit-Queue: Leszek Swirski <leszeks@chromium.org> Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#46355}
-
- 08 Jun, 2017 1 commit
-
-
bbudge authored
- Eliminates b1x4, b1x8, and b1x16 as distinct WASM types. - All vector comparisons return v128 type. - Eliminates b1xN and, or, xor, not. - Selects take a v128 mask vector and are now bit-wise. - Adds a new test for Select, where mask is non-canonical (not 0's and -1's). LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2919203002 Cr-Commit-Position: refs/heads/master@{#45795}
-
- 22 May, 2017 1 commit
-
-
Wiktor Garbacz authored
Change-Id: I20ed35a7fb5104a9cc66bb54fa8966589c43d7f9 Reviewed-on: https://chromium-review.googlesource.com/507287Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Daniel Clifford <danno@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Marja Hölttä <marja@chromium.org> Reviewed-by:
Jochen Eisinger <jochen@chromium.org> Commit-Queue: Wiktor Garbacz <wiktorg@google.com> Cr-Commit-Position: refs/heads/master@{#45458}
-
- 23 Feb, 2017 1 commit
-
-
Marja Hölttä authored
BUG=v8:5294 Change-Id: If45f25aae8de526027b7851cb4efe0ccf4a7c4b1 Reviewed-on: https://chromium-review.googlesource.com/444226 Commit-Queue: Marja Hölttä <marja@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Yang Guo <yangguo@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#43388}
-
- 21 Feb, 2017 1 commit
-
-
bbudge authored
- Adds new machine types SimdBool4/8/16 for the different boolean vector types. - Adds a kSimdMaskRegisters flag for each platform. These are all false for now. - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle opcodes from the Boolean types. These are unlikely to be well supported natively, and can be synthesized using Select. - Changes the signature of Relational opcodes to return boolean vectors. - Changes the signature of Select opcodes to take boolean vectors. - Updates the ARM implementation of Relational and Select opcodes. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2700813002 Cr-Commit-Position: refs/heads/master@{#43348}
-
- 10 Feb, 2017 1 commit
-
-
verwaest authored
BUG= Review-Url: https://codereview.chromium.org/2682143002 Cr-Original-Commit-Position: refs/heads/master@{#43065} Committed: https://chromium.googlesource.com/v8/v8/+/193a0c118845d068ab386b5c90d04daaa64e1e86 Review-Url: https://codereview.chromium.org/2682143002 Cr-Commit-Position: refs/heads/master@{#43085}
-
- 09 Feb, 2017 2 commits
-
-
machenbach authored
Revert of [compiler] Pass deoptimization_kind through DeoptimizeParameters and FlagsContinuation (patchset #3 id:40001 of https://codereview.chromium.org/2682143002/ ) Reason for revert: cfi failure: https://build.chromium.org/p/client.v8/builders/V8%20Linux64%20-%20cfi/builds/8635 Original issue's description: > [compiler] Pass deoptimization_kind through DeoptimizeParameters and FlagsContinuation > > BUG= > > Review-Url: https://codereview.chromium.org/2682143002 > Cr-Commit-Position: refs/heads/master@{#43065} > Committed: https://chromium.googlesource.com/v8/v8/+/193a0c118845d068ab386b5c90d04daaa64e1e86 TBR=jarin@chromium.org,verwaest@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review-Url: https://codereview.chromium.org/2683203002 Cr-Commit-Position: refs/heads/master@{#43070}
-
verwaest authored
BUG= Review-Url: https://codereview.chromium.org/2682143002 Cr-Commit-Position: refs/heads/master@{#43065}
-
- 23 Dec, 2016 1 commit
-
-
ivica.bogosavljevic authored
Reland 0cf56232 The original patch got reverted because testing RegisterConfiguration was overwritten by turbofan RegisterConfiguration. This caused some test cases not being properly tested. The new patch uses correct RegisterConfiguration. Original commit message: Test InstructionSequenceTest has been initialized with a testing RegisterConfiguration instance defined in instruction-sequence-unittest.h, whereas class ExplicitOperand which is being tested used RegisterConfiguration from instruction.cc. In case these two instances are different, the tests would fail. The issue is fixed by using the same instance of RegisterConfiguration both for test code and code under test. Additionally, the tests in register-allocator-unittest.cc use hardcoded values for register and begin failing is the hardcoded register is not available for allocation. Fix by forcing the use of allocatable registers only. TEST=unittests.MoveOptimizerTest.RemovesRedundantExplicit,unittests.RegisterAllocatorTest.SpillPhi BUG= Review-Url: https://codereview.chromium.org/2595293002 Cr-Commit-Position: refs/heads/master@{#41938}
-
- 16 Dec, 2016 1 commit
-
-
mtrofin authored
Revert of MIPS: Fix bad RegisterConfiguration usage in InstructionSequence unit tests. (patchset #3 id:40001 of https://codereview.chromium.org/2433093002/ ) Reason for revert: This change rendered InstructionSequenceTest::SetNumRegs ineffectual, thus loosening the tests that were using that API to ensure correct register allocation under intentionally constrained setups. For the problem stated in this CL, a solution needs to continue supporting the intentionally set-up test configuration. Original issue's description: > MIPS: Fix bad RegisterConfiguration usage in InstructionSequence unit tests. > > Test InstructionSequenceTest has been initialized with a testing RegisterConfiguration > instance defined in instruction-sequence-unittest.h, whereas class ExplicitOperand which > is being tested used RegisterConfiguration from instruction.cc. In case these two > instances are different, the tests would fail. The issue is fixed by using the same > instance of RegisterConfiguration both for test code and code under test. > > Additionally, the tests in register-allocator-unittest.cc use hardcoded values > for register and begin failing is the hardcoded register is not available for > allocation. Fix by forcing the use of allocatable registers only. > > TEST=unittests.MoveOptimizerTest.RemovesRedundantExplicit,unittests.RegisterAllocatorTest.SpillPhi > BUG= > > Committed: https://crrev.com/0cf56232209d4c9c669b8426680de18806f6c29a > Cr-Commit-Position: refs/heads/master@{#40862} TBR=dcarney@chromium.org,bmeurer@chromium.org,mstarzinger@chromium.org,vogelheim@chromium.org,titzer@chromium.org,ivica.bogosavljevic@imgtec.com # Not skipping CQ checks because original CL landed more than 1 days ago. BUG= Review-Url: https://codereview.chromium.org/2587593002 Cr-Commit-Position: refs/heads/master@{#41777}
-
- 15 Dec, 2016 1 commit
-
-
ahaas authored
Some instructions in WebAssembly trap for some inputs, which means that the execution is terminated and (at least at the moment) a JavaScript exception is thrown. Examples for traps are out-of-bounds memory accesses, or integer divisions by zero. Without the TrapIf and TrapUnless operators trap check in WebAssembly introduces 5 TurboFan nodes (branch, if_true, if_false, trap-reason constant, trap-position constant), in addition to the trap condition itself. Additionally, each WebAssembly function has four TurboFan nodes (merge, effect_phi, 2 phis) whose number of inputs is linear to the number of trap checks in the function. Especially for functions with high numbers of trap checks we observe a significant slowdown in compilation time, down to 0.22 MiB/s in the sqlite benchmark instead of the average of 3 MiB/s in other benchmarks. By introducing a TrapIf common operator only a single node is necessary per trap check, in addition to the trap condition. Also the nodes which are shared between trap checks (merge, effect_phi, 2 phis) would disappear. First measurements suggest a speedup of 30-50% on average. This CL only implements TrapIf and TrapUnless on x64. The implementation is also hidden behind the --wasm-trap-if flag. Please take a special look at how the source position is transfered from the instruction selector to the code generator, and at the context that is used for the runtime call. R=titzer@chromium.org Review-Url: https://codereview.chromium.org/2562393002 Cr-Commit-Position: refs/heads/master@{#41720}
-
- 09 Nov, 2016 2 commits
-
-
bbudge authored
- Track representations of virtual registers in InstructionSequence. - Skip extra aliasing work when no floats or SIMD registers are used. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2468233004 Cr-Commit-Position: refs/heads/master@{#40870}
-
ivica.bogosavljevic authored
Test InstructionSequenceTest has been initialized with a testing RegisterConfiguration instance defined in instruction-sequence-unittest.h, whereas class ExplicitOperand which is being tested used RegisterConfiguration from instruction.cc. In case these two instances are different, the tests would fail. The issue is fixed by using the same instance of RegisterConfiguration both for test code and code under test. Additionally, the tests in register-allocator-unittest.cc use hardcoded values for register and begin failing is the hardcoded register is not available for allocation. Fix by forcing the use of allocatable registers only. TEST=unittests.MoveOptimizerTest.RemovesRedundantExplicit,unittests.RegisterAllocatorTest.SpillPhi BUG= Review-Url: https://codereview.chromium.org/2433093002 Cr-Commit-Position: refs/heads/master@{#40862}
-
- 26 Oct, 2016 1 commit
-
-
bbudge authored
- Modifies RegisterConfiguration to specify complex aliasing on ARM 32. - Modifies RegisterAllocator to consider aliasing. - Modifies ParallelMove::PrepareInsertAfter to handle aliasing. - Modifies GapResolver to split wider register moves when interference with smaller moves is detected. - Modifies MoveOptimizer to handle aliasing. - Adds ARM 32 macro-assembler pseudo move instructions to handle cases where split moves don't correspond to actual s-registers. - Modifies CodeGenerator::AssembleMove and AssembleSwap to handle moves of different widths, and moves involving pseudo-s-registers. - Adds unit tests for FP operand interference checking and PrepareInsertAfter. - Adds more tests of FP for the move optimizer and register allocator. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2410673002 Cr-Commit-Position: refs/heads/master@{#40597}
-
- 11 Oct, 2016 1 commit
-
-
mtrofin authored
Treat allocation of splintered ranges differently, by optimizing for move counts (i.e. try to have less move counts), rather than optimizing for quality of moves (which is what normal allocation does). We can see reductions in code size in the benchmarks that measure it (e.g. Unity) BUG= Review-Url: https://codereview.chromium.org/2347563004 Cr-Commit-Position: refs/heads/master@{#40178}
-
- 19 Sep, 2016 1 commit
-
-
jarin authored
Review-Url: https://codereview.chromium.org/2349983002 Cr-Commit-Position: refs/heads/master@{#39492}
-
- 06 Sep, 2016 1 commit
-
-
mtrofin authored
The Print APIs on the instruction model are for debugging. At debug time, we cannot (easily) synthesize an output stream, hence the choice of directing to stdout in those APIs. The concern in https://codereview.chromium.org/2293413004/ is addressed by the changes in pipeline.cc, using the various operator<<, and does not require the changes in instruction.{h|cc}, and the generalization of the Print APIs. BUG= Review-Url: https://codereview.chromium.org/2304423002 Cr-Commit-Position: refs/heads/master@{#39190}
-
- 01 Sep, 2016 1 commit
-
-
ofrobots authored
On larger workloads, lots of output on stdout becomes unwieldy. R=bmeurer@chromium.org BUG= Review-Url: https://codereview.chromium.org/2293413004 Cr-Commit-Position: refs/heads/master@{#39111}
-
- 16 Aug, 2016 1 commit
-
-
mvstanton authored
These new representations aren't used yet. BUG= Review-Url: https://codereview.chromium.org/2216383002 Cr-Commit-Position: refs/heads/master@{#38657}
-
- 29 Jul, 2016 1 commit
-
-
bbudge authored
- Changes register allocation to only use even numbered registers on Arm. - Turns on float32 testing in test-gap-resolver.cc. This is effectively a revert of: https://codereview.chromium.org/2086653003/ LOG=N BUG=V8:4124, V8:5202 Review-Url: https://codereview.chromium.org/2176173003 Cr-Commit-Position: refs/heads/master@{#38151}
-
- 18 Jul, 2016 1 commit
-
-
bmeurer authored
So far TurboFan wasn't adding the deoptimization reasons for eager/soft deoptimization exits that can be used by either the DevTools profiler or the --trace-deopt flag. This adds basic support for deopt reasons on Deoptimize, DeoptimizeIf and DeoptimizeUnless nodes and threads through the reasons to the code generation. Also moves the DeoptReason to it's own file (to resolve include cycles) and drops unused reasons. R=jarin@chromium.org Review-Url: https://codereview.chromium.org/2161543002 Cr-Commit-Position: refs/heads/master@{#37823}
-
- 04 Jul, 2016 1 commit
-
-
bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2116203002 Cr-Commit-Position: refs/heads/master@{#37498}
-
- 30 Jun, 2016 1 commit
-
-
ahaas authored
The call to String::Flatten can cause garbage collection and in general adds complexity to the code generation. It also blocks the way to run code generation on worker threads. The call to String::Flatten in Constant::ToHeapObject() seems not to be necessary for correctness. If removing this call affects performance negatively, we can revert this CL. Review-Url: https://codereview.chromium.org/2107243002 Cr-Commit-Position: refs/heads/master@{#37422}
-
- 29 Jun, 2016 2 commits
-
-
georgia.kouveli authored
Perform the following transformation: | Before | After | |------------------+---------------------| | add w2, w0, w1 | adds w2, w0, w1 | | cmp w2, #0x0 | b.<cond'> <addr> | | b.<cond> <addr> | | |------------------+---------------------| | add w2, w0, w1 | adds w2, w0, w1 | | cmp #0x0, w2 | b.<cond'> <addr> | | b.<cond> <addr> | | and the same for and instructions instead of add. When the result of the add/and is not used, generate cmn/tst instead. We need to take care with which conditions we can handle and what new condition we map them to. BUG= Review-Url: https://codereview.chromium.org/2065243005 Cr-Commit-Position: refs/heads/master@{#37400}
-
bbudge authored
- Changes InstructionOperand canonicalization to map all FP operands to kFloat64 on Intel and other platforms with simple aliasing. - Bypass expensive interference calculations and fixed FP live range processing for platforms with simple aliasing. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2101653003 Cr-Commit-Position: refs/heads/master@{#37388}
-
- 27 Jun, 2016 1 commit
-
-
bbudge authored
Replaces ArchDefault method with Crankshaft and Turbofan getters. Eliminates IsAllocated method on Register, FloatRegister, DoubleRegister. Eliminates ToString method too. Changes call sites to access appropriate arch default RegisterConfiguration. LOG=N BUG= Review-Url: https://codereview.chromium.org/2092413002 Cr-Commit-Position: refs/heads/master@{#37297}
-
- 24 Jun, 2016 2 commits
-
-
bbudge authored
- Adds the concept of FP register aliasing to RegisterConfiguration. - Changes RegisterAllocator to distinguish between FP representations when allocating. - Changes LinearScanAllocator to detect interference when FP register aliasing is combining, as on ARM. - Changes ARM code generation to allow all registers s0 - s31 to be accessed. - Adds unit tests for RegisterConfiguration, mostly to test aliasing calculations. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2086653003 Cr-Commit-Position: refs/heads/master@{#37251}
-
balazs.kilvady authored
Port fc59eb8a Original commit message: Moves between operands with different representations shouldn't happen, so don't test them. This makes it easier to modify canonicalization to differentiate between floating point types, which is needed to support floating point register aliasing for ARM and MIPS. This change also expands tests to include explicit FP moves (both register and stack slot). LOG=N BUG=v8:4124 BUG=chromium:622619 Review-Url: https://codereview.chromium.org/2090993002 Cr-Commit-Position: refs/heads/master@{#37241}
-
- 15 Jun, 2016 1 commit
-
-
bbudge authored
Review-Url: https://codereview.chromium.org/2054343002 Cr-Commit-Position: refs/heads/master@{#37013}
-
- 03 Jun, 2016 1 commit
-
-
bbudge authored
- Adds names for float registers to RegisterConfiguration and uses them when we have the MachineRepresentation. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2030143002 Cr-Commit-Position: refs/heads/master@{#36712}
-
- 27 May, 2016 1 commit
-
-
bbudge authored
- Renames UnallocatedOperandenum values to reflect the fact that there are multiple FP machine representations. - Renames enum values for RegisterAllocatorVerifier enum. - Template-izes DefineAsFixed and UseFixed methods to handle multiple FP register types. BUG=v8:4124 Review-Url: https://codereview.chromium.org/2017733002 Cr-Commit-Position: refs/heads/master@{#36558}
-
- 10 May, 2016 1 commit
-
-
bbudge authored
Renames IsDouble* predicates to IsFP*. Adds specific IsFloat*, IsDouble*, and IsSimd128* predicates. Adds specific GetFloatRegister, GetDoubleRegister, and GetSimd128Register methods. This is mostly a mechanical renaming of IsDouble* to IsFP* methods. This shouldn't change code generation at all. All fp registers are still treated as double registers. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/1959763002 Cr-Commit-Position: refs/heads/master@{#36146}
-
- 04 May, 2016 1 commit
-
-
gdeepti authored
Add new relocation type WASM_MEMORY_SIZE_REFERENCE, use relocatable pointers to update wasm memory size references in generated code. - Add new RelocInfo mode WASM_MEMORY_SIZE_REFERENCE in the assembler and add relocation information to immediates in compare instructions. - Use relocatable constants for MemSize/BoundsCheck in the wasm compiler R=titzer@chromium.org, yangguo@chromium.org, bradnelson@chromium.org Review-Url: https://codereview.chromium.org/1921203002 Cr-Commit-Position: refs/heads/master@{#36044}
-
- 30 Apr, 2016 1 commit
-
-
bmeurer authored
Further refactor the pipeline to even run the first scheduler (part of the effect control linearization) concurrently. This temporarily disables most of the write barrier elimination, but we will get back to that later. Drive-by-fix: Remove the dead code from ChangeLowering, and stack allocate the Typer in the pipeline. Also migrate the AllocateStub to a native code builtin, so that we have the code object + a handle to it available all the time. CQ_INCLUDE_TRYBOTS=tryserver.v8:v8_linux64_tsan_rel R=mstarzinger@chromium.org BUG=v8:4969 LOG=n Review-Url: https://codereview.chromium.org/1926023002 Cr-Commit-Position: refs/heads/master@{#35918}
-
- 28 Apr, 2016 1 commit
-
-
machenbach authored
Revert of [turbofan] Run everything after representation selection concurrently. (patchset #2 id:20001 of https://codereview.chromium.org/1926023002/ ) Reason for revert: [Sheriff] Flaky crashed here and there: https://build.chromium.org/p/client.v8/builders/V8%20Linux/builds/9867 https://build.chromium.org/p/client.v8/builders/V8%20Linux64/builds/9589 https://build.chromium.org/p/client.v8/builders/V8%20Mac/builds/7679 Original issue's description: > [turbofan] Run everything after representation selection concurrently. > > Further refactor the pipeline to even run the first scheduler (part of > the effect control linearization) concurrently. This temporarily > disables most of the write barrier elimination, but we will get back to > that later. TBR=mstarzinger@chromium.org,bmeurer@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review-Url: https://codereview.chromium.org/1925073002 Cr-Commit-Position: refs/heads/master@{#35863}
-