- 13 Oct, 2017 1 commit
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Mathias Bynens authored
New code should use nullptr instead of NULL. This patch updates existing use of NULL to nullptr where applicable, making the code base more consistent. BUG=v8:6928,v8:6921 Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng Change-Id: I4687f5b96fcfd88b41fa970a2b937b4f6538777c Reviewed-on: https://chromium-review.googlesource.com/718338 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Ulan Degenbaev <ulan@chromium.org> Reviewed-by:
Toon Verwaest <verwaest@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Yang Guo <yangguo@chromium.org> Cr-Commit-Position: refs/heads/master@{#48557}
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- 27 Mar, 2017 1 commit
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dusan.simicic authored
This patch adds support for MIPS SIMD (MSA) instructions in Assembler and Decoder (disassembler) classes. MSA instructions are implemented for both mips32 and mips64 architectures. BUG= Review-Url: https://codereview.chromium.org/2740123004 Cr-Commit-Position: refs/heads/master@{#44148}
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- 23 Sep, 2016 1 commit
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balazs.kilvady authored
The running time of optdebug.quickcheck is improved by 8% while a more strict DCHECKing is kept in simulator. Review-Url: https://codereview.chromium.org/1349403003 Cr-Commit-Position: refs/heads/master@{#39667}
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- 18 Jan, 2016 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1593713002 Cr-Commit-Position: refs/heads/master@{#33361}
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- 10 Nov, 2015 1 commit
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balazs.kilvady authored
Jic and jialc compact branch ops are fixed as they does not have 'forbidden slot' restriction. Also COP1 branches (CTI instructions) added to IsForbiddenAfterBranchInstr(). TEST=cctest/test-disasm-mips/Type0 BUG= Review URL: https://codereview.chromium.org/1423493006 Cr-Commit-Position: refs/heads/master@{#31922}
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- 03 Nov, 2015 1 commit
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balazs.kilvady authored
BUG= Review URL: https://codereview.chromium.org/1396133002 Cr-Commit-Position: refs/heads/master@{#31761}
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- 04 Sep, 2015 1 commit
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balazs.kilvady authored
The patch decreases the calls of huge switch instructions making the DecodeType*() functions to work in one phase and optimizing Instruction::InstructionType(). Speed gain in release full check is about 33% (6:13 s -> 4:09 s) and in optdebug full test is about 50% (12:29 -> 6:17) BUG= Review URL: https://codereview.chromium.org/1310883005 Cr-Commit-Position: refs/heads/master@{#30596}
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- 17 Aug, 2015 1 commit
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mstarzinger authored
R=yangguo@chromium.org Review URL: https://codereview.chromium.org/1299563003 Cr-Commit-Position: refs/heads/master@{#30187}
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- 19 Jun, 2015 1 commit
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Ilija.Pavlovic authored
Added: JIC, BEQZC, JIALC, LDPC, LWPC, ALUIPC, ADDIUPC, ALIGN/DAILGN, LWUPC, AUIPC, BC, BALC. Additional fixed compact branch offset. TEST=test-assembler-mips[64]/r6_align, r6_dalign, r6_aluipc, r6_lwpc, r6_jic, r6_beqzc, r6_jialc, r6_addiupc, r6_ldpc, r6_lwupc, r6_auipc, r6_bc, r6_balc BUG= Review URL: https://codereview.chromium.org/1195793002 Cr-Commit-Position: refs/heads/master@{#29143}
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- 01 Jun, 2015 1 commit
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erikcorry authored
When compiling on a laptop I like to concatenate the small test files. This makes a big difference to compile times. These changes make that easier. R=ulan@chromium.org BUG= Review URL: https://codereview.chromium.org/1163803002 Cr-Commit-Position: refs/heads/master@{#28742}
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- 22 May, 2015 1 commit
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Djordje.Pesic authored
Implement assembler, disassembler tests for all instructions for mips32 and mips64. Additionally, add missing single precision float instructions for r2 and r6 architecture variants in assembler, simulator and disassembler with corresponding tests. Review URL: https://codereview.chromium.org/1145223002 Cr-Commit-Position: refs/heads/master@{#28595}
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- 06 Apr, 2015 1 commit
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dusan.milosavljevic authored
- Fixed single float register type instruction en[de]coding in assembler and disassembler. - Added max and min instructions for r6 and corresponding tests. - Fixed selection instruction for boundary cases in simulator. - Update assembler tests to be more thorough wrt boundary cases. TEST=cctest/test-assembler-mips64/MIPS17, MIPS18 cctest/test-disasm-mips64/Type1 cctest/test-assembler-mips/MIPS16, MIPS17 cctest/test-disasm-mips/Type1 BUG= Review URL: https://codereview.chromium.org/1057323002 Cr-Commit-Position: refs/heads/master@{#27601}
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- 30 Mar, 2015 1 commit
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dusan.milosavljevic authored
TEST= BUG= Review URL: https://codereview.chromium.org/1046873004 Cr-Commit-Position: refs/heads/master@{#27530}
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- 12 Aug, 2014 1 commit
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dusan.milosavljevic@imgtec.com authored
Fixing gclient runhooks failure caused by reverted commit r23050. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/467583002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23088 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 11 Aug, 2014 4 commits
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machenbach@chromium.org authored
This reverts commit r23050 for breaking runhooks on chromium. See e.g.: http://build.chromium.org/p/client.v8/builders/Chrome%20Linux%20Perf/builds/1438/steps/runhooks/logs/stdio TBR=jochen@chromium.org Review URL: https://codereview.chromium.org/458983003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23053 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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dusan.milosavljevic@imgtec.com authored
Original commit r23028 breaks ARM64 build due to conflicting FP64 symbolic constant definition in src/globals.h and src/arm64/constants-arm64.h. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/457313003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23050 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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jochen@chromium.org authored
Breaks compilation of ARM64. | Additional summary: | - Introduce fp64 fpu mode into mips32 port required for r6. | - Implement runtime detections for fpu mode and arch. revision to preserve | compatibility with previous architecture revisions. | | TEST= | BUG= | R=jkummerow@chromium.org, paul.lind@imgtec.com | | Review URL: https://codereview.chromium.org/453043002 BUG=none LOG=n TBR=jkummerow@chromium.org Review URL: https://codereview.chromium.org/458193002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23030 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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dusan.milosavljevic@imgtec.com authored
Additional summary: - Introduce fp64 fpu mode into mips32 port required for r6. - Implement runtime detections for fpu mode and arch. revision to preserve compatibility with previous architecture revisions. TEST= BUG= R=jkummerow@chromium.org, paul.lind@imgtec.com Review URL: https://codereview.chromium.org/453043002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@23028 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 03 Jun, 2014 1 commit
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jochen@chromium.org authored
- this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 09 May, 2014 1 commit
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ishell@chromium.org authored
1) runtime/references checks temporarily disabled (56 items left) 2) other errors fixed R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/277913002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21222 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 29 Apr, 2014 1 commit
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bmeurer@chromium.org authored
R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/259183002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@21035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 05 Jul, 2013 1 commit
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yangguo@chromium.org authored
R=yangguo@chromium.org Review URL: https://codereview.chromium.org/18509003 Patch from Haitao Feng <haitao.feng@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15510 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 28 Jun, 2013 1 commit
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jkummerow@chromium.org authored
R=jkummerow@chromium.org Review URL: https://codereview.chromium.org/18037002 Patch from Haitao Feng <haitao.feng@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15391 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 09 Jan, 2013 1 commit
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yangguo@chromium.org authored
Based on commit r12958 (04586adf). BUG= TEST= Review URL: https://chromiumcodereview.appspot.com/11783049 Patch from Akos Palfi <palfia@homejinni.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13342 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 16 Jan, 2012 1 commit
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erik.corry@gmail.com authored
Review URL: http://codereview.chromium.org/9231009 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10407 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 13 Sep, 2011 1 commit
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danno@chromium.org authored
Highlights: - assembler.h adds FPU definitions used for Crankshaft. - Support optimization of mips call: jalr->jal - includes changes to set_target_address_at(), support routines. - Add 2nd use of Apply() to update target addresses. - Minor debugging improvement in simulator. BUG= TEST= Review URL: http://codereview.chromium.org/7888003 Patch from Paul Lind <plind44@gmail.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@9259 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 09 May, 2011 1 commit
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sgjesse@chromium.org authored
- Merge to current tip of tree, fix build problems. - Remove deprecated source files. - Add cctest test-disasm-mips - Consistently use single-reg push()/pop() (remove uppercase variants) - Add assembler field accessors. - More style fixes. BUG= TEST= Review URL: http://codereview.chromium.org//6965006 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7825 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 28 Mar, 2011 1 commit
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sgjesse@chromium.org authored
This commit adds current working versions of assembler, macro-assembler, disassembler, and simulator. All other mips arch files are replaced with stubbed-out versions that will build. Arch independent files are updated as needed to support building and running mips. The only test is cctest/test-assembler-mips, and this passes on the simulator and on mips hardware. TEST=none BUG=none Patch by Paul Lind from MIPS. Review URL: http://codereview.chromium.org/6730029/ git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7388 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 17 May, 2010 1 commit
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mark@chromium.org authored
Chromium build. v8.gyp no longer sets any V8_TARGET_ARCH_* macro on the Mac. Instead, the proper V8_TARGET_ARCH_* macro will be set by src/globals.h in the same way as the V8_HOST_ARCH_* macro when it detects that no target macro is currently defined. The Mac build will attempt to compile all ia32 and x86_64 .cc files. #ifdef guards in each of these target-specific source files prevent their compilation when the associated target is not selected. For completeness, these #ifdef guards are also provided for the arm and mips .cc files. BUG=706 TEST=x86_64 Mac GYP/Xcode-based Chromium build (still depends on other changes) Review URL: http://codereview.chromium.org/2133003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4666 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 04 Feb, 2010 1 commit
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sgjesse@chromium.org authored
This is the first step in the MIPS port of V8. It adds assembler, disassembler and simulator for the MIPS32 architecture. Contains stubbed out implementation of all the compiler/code generator infrastructure to make it all build. Patch by Alexandre Rames from Sigma Designs Inc. This is the landing of http://codereview.chromium.org/543161. Review URL: http://codereview.chromium.org/561072 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3799 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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