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  1. 13 Jan, 2017 1 commit
  3. 12 Jan, 2017 1 commit
  5. 10 Jan, 2017 1 commit
  7. 18 Aug, 2016 1 commit
  9. 29 Jun, 2016 1 commit
  11. 28 Jun, 2016 1 commit
    • bjaideep's avatar
      PPC/s390: Reland [heap] Avoid the use of cells to point from code to new-space objects. · 85cebe73
      bjaideep authored 
      Port 5e058540

Original commit message:

    The reason for reverting is: This breaks gc-stress bot:
    https://chromegw.corp.google.com/i/client.v8/builders/V8%20Linux64%20GC%20Stress%20-%20custom%20snapshot

    Abortion of compaction could cause duplicate entries in the typed-old-to-new remembered set.
    These duplicates could cause a DCHECK to trigger which checks that slots recorded in the
    remembered set never point to to-space. This reland-CL allows duplicates in the remembered
    set by removing the DCHECK, and additionally clears entries in the remembered set if objects are moved.

    Original issue's description:

    Cells were needed originally because there was no typed remembered set to
    record direct pointers from code space to new space. A previous
    CL (https://codereview.chromium.org/2003553002/) already introduced
    the remembered set, this CL uses it.

    This CL
    * stores direct pointers in code objects, even if the target is in new space,
    * records the slot of the pointer in typed-old-to-new remembered set,
    * adds a list which stores weak code-to-new-space references,
    * adds a test to test-heap.cc for weak code-to-new-space references,
    * removes prints in tail-call-megatest.js

R=ahaas@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=
LOG=N

Review-Url: https://codereview.chromium.org/2108673003
Cr-Commit-Position: refs/heads/master@{#37346}
      85cebe73
  13. 27 Jun, 2016 1 commit
    • ssanfilippo's avatar
      This commit is the first step towards emitting unwinding information in · 7d073b03
      ssanfilippo authored 
      the .eh_frame format as part of the jitdump generated when
FLAG_perf_prof is enabled. The final goal is allowing precise unwinding
of callchains that include JITted code when profiling V8 using perf.

Unwinding information is stored in the body of code objects after the
code itself, prefixed with its length and aligned to a 8-byte boundary.
A boolean flag in the header signals its presence, resulting in zero
memory overhead when the generation of unwinding info is disabled or
no such information was attached to the code object.

A new jitdump record type (with id 4) is introduced for specifying
optional unwinding information for code load records. The EhFrameHdr
struct is also introduced, together with a constructor to initialise it
from the associated code object.

At this stage no unwinding information is written to the jitdump, but
the infrastructure for doing so is ready in place.

BUG=v8:4899
LOG=N

Review-Url: https://codereview.chromium.org/1993653003
Cr-Commit-Position: refs/heads/master@{#37296}
      7d073b03
  15. 20 Jun, 2016 2 commits
    • bjaideep's avatar
      PPC/s390: [wasm] Separate compilation from instantiation · 8071e21c
      bjaideep authored 
      Port c1d01aea

Original commit message:

    Compilation of wasm functions happens before instantiation. Imports are linked afterwards, at instantiation time. Globals and memory are also
    allocated and then tied in via relocation at instantiation time.

    This paves the way for implementing Wasm.compile, a prerequisite to
    offering the compiled code serialization feature.

    Currently, the WasmModule::Compile method just returns a fixed array
    containing the code objects. More appropriate modeling of the compiled module to come.

    Opportunistically centralized the logic on how to update memory
    references, size, and globals, since that logic is the exact same on each
    architecture, except for the actual storing of values back in the
    instruction stream.

R=mtrofin@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=v8:5072
LOG=N

Review-Url: https://codereview.chromium.org/2087453002
Cr-Commit-Position: refs/heads/master@{#37116}
      8071e21c
    • yangguo's avatar
      Simplify AssemblerPositionsRecorder. · 9c3d730d
      yangguo authored 
      R=bmeurer@chromium.org, jgruber@chromium.org

Review-Url: https://codereview.chromium.org/2072963003
Cr-Commit-Position: refs/heads/master@{#37089}
      9c3d730d
  17. 16 Jun, 2016 1 commit
  19. 05 May, 2016 1 commit
    • bjaideep's avatar
      PPC: Add new relocation type WASM_MEMORY_SIZE_REFERENCE, use relocatable... · a870cf3a
      bjaideep authored 
      PPC: Add new relocation type WASM_MEMORY_SIZE_REFERENCE, use relocatable pointers to update wasm memory size references in generated code.

Port 117a56b7

Original commit message:

     - Add new RelocInfo mode WASM_MEMORY_SIZE_REFERENCE in the assembler and add relocation information to immediates in compare instructions.
     - Use relocatable constants for MemSize/BoundsCheck in the wasm compiler

R=gdeepti@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=
LOG=N

Review-Url: https://codereview.chromium.org/1948263003
Cr-Commit-Position: refs/heads/master@{#36054}
      a870cf3a
  21. 16 Mar, 2016 3 commits
    • mbrandy's avatar
      Reland PPC portion of "Detect cache line size on Linux for PPC hosts." · 042f09a9
      mbrandy authored 
      This version does not modify arm64.

R=jkummerow@chromium.org, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1806893002

Cr-Commit-Position: refs/heads/master@{#34827}
      042f09a9
    • mbrandy's avatar
      PPC: [wasm] Int64Lowering of Int64Sub. · eb0a2324
      mbrandy authored 
      Port 33c08596

Original commit message:
    Int64Sub is lowered to a new turbofan operator, Int32SubPair. The new
    operator takes 4 inputs an generates 2 outputs. The inputs are the low
    word of the left input, high word of the left input, the low word of the
    right input, and high word of the right input. The ouputs are the low
    and high word of the result of the subtraction.

    The implementation is very similar to the implementation of Int64Add.

R=ahaas@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1812473002

Cr-Commit-Position: refs/heads/master@{#34821}
      eb0a2324
    • jkummerow's avatar
      Revert "Detect cache line size on Linux for PPC hosts." · 5d62db74
      jkummerow authored 
      along with "[arm64] Fix i/d cache line size confusion typo"
and "Fix a warning about inline asm source/destination mismatches..."
which were building on it.

This reverts the following commits:
8d7399f9
474e6a3d
c3ff68b6

Reason for revert: We're getting a large number of crash reports from
arm64 devices that are obviously related to cache flushing after code
patching. Bisection results say that the problems started at revision
c3ff68b6. Since I can't find a bug in that CL except for the typo that
I've fixed in 474e6a3d (which made some of the crashes go away but not
all of them), we have no choice but to revert the changes in order to
get stability under control while we investigate.

BUG=chromium:594646
LOG=n

Review URL: https://codereview.chromium.org/1806853002

Cr-Commit-Position: refs/heads/master@{#34816}
      5d62db74
  23. 15 Mar, 2016 1 commit
    • mbrandy's avatar
      PPC: [wasm] Int64Lowering of Int64Add. · 0548cf49
      mbrandy authored 
      Port 1b230799

Original commit message:
    Int64Add is lowered to a new turbofan operator, Int32AddPair. The new
    operator takes 4 inputs an generates 2 outputs. The inputs are the low
    word of the left input, high word of the left input, the low word of the
    right input, and high word of the right input. The ouputs are the low
    and high word of the result of the addition.

R=ahaas@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1803113002

Cr-Commit-Position: refs/heads/master@{#34797}
      0548cf49
  25. 01 Feb, 2016 1 commit
    • mbrandy's avatar
      Detect cache line size on Linux for PPC hosts. · c3ff68b6
      mbrandy authored 
      In the interest of generalization, this change:
- Consolidates cache line size detection for all interested
  architectures under base::CPU (currently leveraged by only
  PPC and ARM64).
- Differentiates between instruction vs data cache line sizes.

R=rmcilroy@chromium.org, jochen@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1643363002

Cr-Commit-Position: refs/heads/master@{#33642}
      c3ff68b6
  27. 20 Jan, 2016 1 commit
  29. 09 Dec, 2015 1 commit
    • mbrandy's avatar
      PPC64: [turbofan] Changed TruncateFloat64ToInt64 to TryTruncateFloat64ToInt64. · b9f92c15
      mbrandy authored 
      Port 95844d94

Original commit message:
    The new operator provides a second output which indicates whether the
    conversion from float64 to int64 was successful or not. The second
    output returns 0 if the conversion fails. If the conversion succeeds,
    then the second output is differs from 0.

    The second output can be ignored, which means that the operator can be
    used the same way as the original operator.

R=ahaas@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1515603002

Cr-Commit-Position: refs/heads/master@{#32724}
      b9f92c15
  31. 27 Nov, 2015 3 commits
  33. 23 Nov, 2015 1 commit
  35. 17 Nov, 2015 1 commit
  37. 11 Nov, 2015 2 commits
  39. 10 Nov, 2015 1 commit
  41. 16 Oct, 2015 1 commit
  43. 05 Oct, 2015 1 commit
    • mbrandy's avatar
      PPC: Remove register index/code indirection · f53fda63
      mbrandy authored 
      Port 5cf1c0bc

Original commit message:
    Previous to this patch, both the lithium and TurboFan register
    allocators tracked allocated registers by "indices", rather than
    the register codes used elsewhere in the runtime. This patch
    ensures that codes are used everywhere, and in the process cleans
    up a bunch of redundant code and adds more structure to how the
    set of allocatable registers is defined.

    Some highlights of changes:

    * TurboFan's RegisterConfiguration class moved to V8's top level
      so that it can be shared with Crankshaft.
    * Various "ToAllocationIndex" and related methods removed.
    * Code that can be easily shared between Register classes on
      different platforms is now shared.
    * The list of allocatable registers on each platform is declared
      as a list rather than implicitly via the register index <->
      code mapping.

R=danno@chromium.org, bmeurer@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, dstence@us.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1381383002

Cr-Commit-Position: refs/heads/master@{#31114}
      f53fda63
  45. 03 Sep, 2015 1 commit
  47. 17 Aug, 2015 1 commit
  49. 30 Jul, 2015 1 commit
  51. 14 Jul, 2015 1 commit
    • mbrandy's avatar
      PPC: Limit unbound label tracking to branch references. · 7b1d583d
      mbrandy authored 
      Labels which are not associated with branches (e.g. labels which
record the location of the embedded constant pool or jump tables)
should not be tracked for the purpose of trampoline generation.

This also improves management of the high water mark in the buffer
which triggers trampoline generation such that it is reset whenever
the number of tracked branches drops to zero.

These changes should help minimize unnecessary trampoline and
(subsequent) slow branch generation.

R=dstence@us.ibm.com, michael_dawson@ca.ibm.com
BUG=

Review URL: https://codereview.chromium.org/1237213002

Cr-Commit-Position: refs/heads/master@{#29659}
      7b1d583d
  53. 13 Jul, 2015 1 commit
  55. 02 Jul, 2015 1 commit
  57. 24 Jun, 2015 1 commit
  59. 09 Jun, 2015 1 commit
    • mbrandy's avatar
      Fix issues with Arm's use of embedded constant pools · e3d76269
      mbrandy authored 
      - Introduce Assembler::DataAlign for table alignment in code object
- Fix several misuses of r8 (alias of the pool pointer register, pp)
- Fix calculation of pp in OSR/handler entry invocation
- Enable missing cases in deserializer
- Fix references to ool constant pools in comments.

R=rmcilroy@chromium.org, michael_dawson@ca.ibm.com
BUG=chromium:497180
LOG=N

Review URL: https://codereview.chromium.org/1155673005

Cr-Commit-Position: refs/heads/master@{#28873}
      e3d76269
  61. 04 Jun, 2015 1 commit
    • mbrandy's avatar
      Add support for Embedded Constant Pools for PPC and Arm · eac7f046
      mbrandy authored 
      Embed constant pools within their corresponding Code
objects.

This removes support for out-of-line constant pools in favor
of the new approach -- the main advantage being that it
eliminates the need to allocate and manage separate constant
pool array objects.

Currently supported on PPC and ARM.  Enabled by default on
PPC only.

This yields a 6% improvment in Octane on PPC64.

R=bmeurer@chromium.org, rmcilroy@chromium.org, michael_dawson@ca.ibm.com
BUG=chromium:478811
LOG=Y

Review URL: https://codereview.chromium.org/1162993006

Cr-Commit-Position: refs/heads/master@{#28801}
      eac7f046
  63. 03 Jun, 2015 1 commit
  65. 02 Jun, 2015 1 commit
    • mbrandy's avatar
      Add support for Embedded Constant Pools for PPC and Arm · a9404029
      mbrandy authored 
      Embed constant pools within their corresponding Code
objects.

This removes support for out-of-line constant pools in favor
of the new approach -- the main advantage being that it
eliminates the need to allocate and manage separate constant
pool array objects.

Currently supported on PPC and ARM.  Enabled by default on
PPC only.

This yields a 6% improvment in Octane on PPC64.

R=danno@chromium.org, svenpanne@chromium.org, bmeurer@chromium.org, rmcilroy@chromium.org, dstence@us.ibm.com, michael_dawson@ca.ibm.com
BUG=chromium:478811
LOG=Y

Review URL: https://codereview.chromium.org/1131783003

Cr-Commit-Position: refs/heads/master@{#28770}
      a9404029
  67. 01 Jun, 2015 1 commit