1. 18 Oct, 2017 1 commit
  2. 16 Oct, 2017 3 commits
    • Junliang Yan's avatar
      Reland "PPC/s390: Fix arguement handling" · 11291891
      Junliang Yan authored
      This is a reland of af49af00
      Original change's description:
      > PPC/s390: Fix arguement handling
      > 
      > 1. in AssembleMove and AssembleSwap, we need to distinguish Double and Float
      > 2. in 32-bit mode, double needs to be counted as 2 slots in stack
      > 
      > R=joransiu@ca.ibm.com, jbarboza@ca.ibm.com, michael_dawson@ca.ibm.com, mmallick@ca.ibm.com
      > 
      > Bug: 
      > Change-Id: Iffe1844aa72e9d4c9492034c3df9a994e1304a27
      > Reviewed-on: https://chromium-review.googlesource.com/720676
      > Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
      > Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
      > Cr-Commit-Position: refs/heads/master@{#48593}
      
      Change-Id: If91125e71b82c92f54f537345e4c213bd185e786
      Reviewed-on: https://chromium-review.googlesource.com/721419Reviewed-by: 's avatarJoran Siu <joransiu@ca.ibm.com>
      Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
      Cr-Commit-Position: refs/heads/master@{#48610}
      11291891
    • Junliang Yan's avatar
      Revert "PPC/s390: Fix arguement handling" · 34ba7e94
      Junliang Yan authored
      This reverts commit af49af00.
      
      Reason for revert: <INSERT REASONING HERE>
      
      There is a mistake in codegen to cause error in snapshot.
      
      Original change's description:
      > PPC/s390: Fix arguement handling
      > 
      > 1. in AssembleMove and AssembleSwap, we need to distinguish Double and Float
      > 2. in 32-bit mode, double needs to be counted as 2 slots in stack
      > 
      > R=​joransiu@ca.ibm.com, jbarboza@ca.ibm.com, michael_dawson@ca.ibm.com, mmallick@ca.ibm.com
      > 
      > Bug: 
      > Change-Id: Iffe1844aa72e9d4c9492034c3df9a994e1304a27
      > Reviewed-on: https://chromium-review.googlesource.com/720676
      > Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
      > Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
      > Cr-Commit-Position: refs/heads/master@{#48593}
      
      TBR=michael_dawson@ca.ibm.com,jyan@ca.ibm.com,joransiu@ca.ibm.com,jbarboza@ca.ibm.com,mmallick@ca.ibm.com
      
      Change-Id: I76b7eb96e7bfc15e3d2b07474543e996b9ea5f86
      No-Presubmit: true
      No-Tree-Checks: true
      No-Try: true
      Reviewed-on: https://chromium-review.googlesource.com/721140Reviewed-by: 's avatarJoran Siu <joransiu@ca.ibm.com>
      Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
      Cr-Commit-Position: refs/heads/master@{#48600}
      34ba7e94
    • Junliang Yan's avatar
      PPC/s390: Fix arguement handling · af49af00
      Junliang Yan authored
      1. in AssembleMove and AssembleSwap, we need to distinguish Double and Float
      2. in 32-bit mode, double needs to be counted as 2 slots in stack
      
      R=joransiu@ca.ibm.com, jbarboza@ca.ibm.com, michael_dawson@ca.ibm.com, mmallick@ca.ibm.com
      
      Bug: 
      Change-Id: Iffe1844aa72e9d4c9492034c3df9a994e1304a27
      Reviewed-on: https://chromium-review.googlesource.com/720676Reviewed-by: 's avatarJoran Siu <joransiu@ca.ibm.com>
      Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
      Cr-Commit-Position: refs/heads/master@{#48593}
      af49af00
  3. 13 Oct, 2017 1 commit
  4. 25 Sep, 2017 1 commit
  5. 24 Aug, 2017 1 commit
  6. 03 Aug, 2017 1 commit
  7. 13 Jul, 2017 1 commit
  8. 12 Jul, 2017 1 commit
  9. 08 Jun, 2017 1 commit
    • bbudge's avatar
      [WASM] Eliminate SIMD boolean vector types. · 381f7da0
      bbudge authored
      - Eliminates b1x4, b1x8, and b1x16 as distinct WASM types.
      - All vector comparisons return v128 type.
      - Eliminates b1xN and, or, xor, not.
      - Selects take a v128 mask vector and are now bit-wise.
      - Adds a new test for Select, where mask is non-canonical (not 0's and -1's).
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2919203002
      Cr-Commit-Position: refs/heads/master@{#45795}
      381f7da0
  10. 22 May, 2017 1 commit
  11. 16 May, 2017 1 commit
  12. 09 May, 2017 2 commits
  13. 12 Apr, 2017 1 commit
  14. 11 Apr, 2017 1 commit
  15. 05 Apr, 2017 1 commit
  16. 04 Apr, 2017 1 commit
  17. 31 Mar, 2017 1 commit
  18. 21 Mar, 2017 1 commit
  19. 16 Mar, 2017 2 commits
  20. 13 Mar, 2017 1 commit
  21. 10 Mar, 2017 1 commit
  22. 08 Mar, 2017 1 commit
  23. 01 Mar, 2017 1 commit
  24. 21 Feb, 2017 1 commit
    • bbudge's avatar
      [V8] Implement SIMD Boolean vector types to allow mask registers. · 9fe0b4c7
      bbudge authored
      - Adds new machine types SimdBool4/8/16 for the different boolean vector types.
      - Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
      - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
        opcodes from the Boolean types. These are unlikely to be well supported natively,
        and can be synthesized using Select.
      - Changes the signature of Relational opcodes to return boolean vectors.
      - Changes the signature of Select opcodes to take boolean vectors.
      - Updates the ARM implementation of Relational and Select opcodes.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2700813002
      Cr-Commit-Position: refs/heads/master@{#43348}
      9fe0b4c7
  25. 17 Feb, 2017 2 commits
  26. 10 Feb, 2017 2 commits
  27. 09 Feb, 2017 2 commits
  28. 02 Feb, 2017 1 commit
  29. 01 Feb, 2017 1 commit
  30. 31 Jan, 2017 1 commit
    • bjaideep's avatar
      PPC/s390: [Turbofan]: Use new MachineTypes in access-builder. · 7c982e7e
      bjaideep authored
      Port 56429fc1
      
      Original Commit Message:
      
          Introduced MachineType::TaggedSigned() and TaggedPointer().
      
          The idea is to quit using the representational dimension of Type, and
          instead encode this information in the MachineRepresentation (itself
          lightly wrapped in MachineType, along with MachineSemantic).
      
          There are three parts to the whole change:
      
          1) Places that set the machine representation - constant nodes, loads nad
             stores, global object and native context specialization.
      
          2) Places that propagate type/representation - this is representation
             inference (aka simplified lowering). At the end of this process we
             expect to have a MachineRepresentation for every node. An interesting
             part of this is phi merging.
      
          3) Places that examine representation - WriteBarrier elimination does this.
             Currently it's looking at the Type representation dimension, but as
             a part of this change (or in a soon-to-follow change) it can simply
             examine the MachineRepresentation.
      
      R=mvstanton@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
      BUG=
      LOG=N
      
      Review-Url: https://codereview.chromium.org/2662223003
      Cr-Commit-Position: refs/heads/master@{#42817}
      7c982e7e
  31. 30 Jan, 2017 2 commits
    • bjaideep's avatar
      PPC/s390: [wasm] TrapIf and TrapUnless TurboFan operators implemented on arm. · 544308b8
      bjaideep authored
      Port ca8d3ba7
      
      Original Commit Message:
      
          Original commit message:
          [wasm] Introduce the TrapIf and TrapUnless operators to generate trap code.
      
          Some instructions in WebAssembly trap for some inputs, which means that the
          execution is terminated and (at least at the moment) a JavaScript exception is
          thrown. Examples for traps are out-of-bounds memory accesses, or integer
          divisions by zero.
      
          Without the TrapIf and TrapUnless operators trap check in WebAssembly introduces 5
          TurboFan nodes (branch, if_true, if_false, trap-reason constant, trap-position
          constant), in addition to the trap condition itself. Additionally, each
          WebAssembly function has four TurboFan nodes (merge, effect_phi, 2 phis) whose
          number of inputs is linear to the number of trap checks in the function.
          Especially for functions with high numbers of trap checks we observe a
          significant slowdown in compilation time, down to 0.22 MiB/s in the sqlite
          benchmark instead of the average of 3 MiB/s in other benchmarks. By introducing
          a TrapIf common operator only a single node is necessary per trap check, in
          addition to the trap condition. Also the nodes which are shared between trap
          checks (merge, effect_phi, 2 phis) would disappear. First measurements suggest a
          speedup of 30-50% on average.
      
          This CL only implements TrapIf and TrapUnless on x64. The implementation is also
          hidden behind the --wasm-trap-if flag.
      
          Please take a special look at how the source position is transfered from the
          instruction selector to the code generator, and at the context that is used for
          the runtime call.
      
      R=ahaas@chromium.org, titzer@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com
      BUG=
      LOG=N
      
      Review-Url: https://codereview.chromium.org/2666433002
      Cr-Commit-Position: refs/heads/master@{#42793}
      544308b8
    • jyan's avatar
      s390: TF Optimize 32-bit Mul/Div/Mod/Popcnt · 0d9b0dcf
      jyan authored
      R=joransiu@ca.ibm.com, bjaideep@ca.ibm.com
      BUG=
      
      Review-Url: https://codereview.chromium.org/2662963002
      Cr-Commit-Position: refs/heads/master@{#42791}
      0d9b0dcf
  32. 25 Jan, 2017 1 commit
    • jyan's avatar
      s390: TF Codegen Optimization · f7a3ede0
      jyan authored
      List of items:
        1. Avoid zero-extending for subsequent 32-bit operations if current operation does not change upper 32-bit or does zero-extending.
        2. Match complex address mode for binary operation where possible (eg. use Add R,MEM).
        3. Detect instruction forms in selector. Eg. kAllowRRR, kAllowRM
        4. Optimize sequence for Int32MulWithOverflow, Int32Div, etc.
        5. Remove Not32/Not64 which is the same as XOR
      
      R=bjaideep@ca.ibm.com, joransiu@ca.ibm.com
      BUG=
      
      Review-Url: https://codereview.chromium.org/2649113007
      Cr-Commit-Position: refs/heads/master@{#42669}
      f7a3ede0