- 27 Oct, 2021 1 commit
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Hao Xu authored
Drive-by fix: Fix some typos in comments. Bug: v8:12319 Change-Id: Ieb4f9ab26bd4e07125ff17df9c048681733cf758 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3222263Reviewed-by:
Nico Hartmann <nicohartmann@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Commit-Queue: Hao A Xu <hao.a.xu@intel.com> Cr-Commit-Position: refs/heads/main@{#77570}
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- 25 Oct, 2021 1 commit
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Nico Hartmann authored
Bug: chromium:1254189 Change-Id: I77854c767cf5c5748999fdd40a4a42e25dff3f79 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3236989Reviewed-by:
Maya Lekova <mslekova@chromium.org> Reviewed-by:
Victor Gomes <victorgomes@chromium.org> Commit-Queue: Victor Gomes <victorgomes@chromium.org> Commit-Queue: Nico Hartmann <nicohartmann@chromium.org> Cr-Commit-Position: refs/heads/main@{#77516}
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- 21 Oct, 2021 1 commit
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Michael Lippautz authored
Bug: chromium:1260621 Change-Id: Iddfd5ee70ce9479209ff81f41197805e738298e0 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3236990Reviewed-by:
Michael Stanton <mvstanton@chromium.org> Commit-Queue: Michael Lippautz <mlippautz@chromium.org> Cr-Commit-Position: refs/heads/main@{#77501}
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- 18 Oct, 2021 1 commit
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Lei Zhang authored
Avoid generating switch statements with only a default case. Instead, when there are no instructions that can trap, simply have HasMemoryAccessMode() return false. This avoids a MSVC warning when doing a 32-bit build. To do this, remove empty TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST definitions from instruction-codes-$arch.h files. Change-Id: Ifed76eb9cbca169f30c188c1999e1e9be0b2c6aa Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3224807Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Maya Lekova <mslekova@chromium.org> Commit-Queue: Lei Zhang <thestig@chromium.org> Cr-Commit-Position: refs/heads/main@{#77441}
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- 01 Oct, 2021 1 commit
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Maya Lekova authored
This CL adds support for handling calls to C functions with arbitrary signatures on native arm64. It introduces a new ExternalReference type FAST_C_CALL. The CL also splits the 10 bits used by kArchCallCFunction instruction to store the total number of parameters into two 5-bit values, representing the number of general purpose and floating point parameters. Design doc: https://docs.google.com/document/d/1ZxOF3GSyNmtU0C0YJvrsydPJj35W_tTJZymeXwfDxoI/edit This CL is partially based on the previous attempt: https://chromium-review.googlesource.com/c/v8/v8/+/2343072 Bug: chromium:1052746 Change-Id: Ib508626d57da26ec3c9186ee8fc46356e3c87f3a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3182232Reviewed-by:
Georg Neis <neis@chromium.org> Reviewed-by:
Toon Verwaest <verwaest@chromium.org> Commit-Queue: Maya Lekova <mslekova@chromium.org> Cr-Commit-Position: refs/heads/main@{#77198}
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- 30 Sep, 2021 1 commit
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Marja Hölttä authored
It's confusing that we have CSA_CHECK and CSA_ASSERT and it's not clear from the names that the former works in release mode and the latter only in debug mode. Renaming CSA_ASSERT to CSA_DCHECK makes it clear what it does. So now we have CSA_CHECK and CSA_DCHECK and they're not confusing. This also renames assert() in Torque to dcheck(). Bug: v8:12244 Change-Id: I6f25d431ebc6eec7ebe326b6b8ad3a0ac5e9a108 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3190104Reviewed-by:
Nico Hartmann <nicohartmann@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Igor Sheludko <ishell@chromium.org> Reviewed-by:
Shu-yu Guo <syg@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/main@{#77160}
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- 24 Sep, 2021 2 commits
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Jakob Kummerow authored
Bug: v8:12244,v8:12245 Change-Id: I3d9223f32bdc0d1cf7e5083996bc5707ab361e52 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3183162 Commit-Queue: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Auto-Submit: Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#77062}
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Georg Neis authored
Because these instructions can trap, we don't want them to be reordered as freely as unprotected accesses. As part of this, make explicit which opcodes support a MemoryAccessMode. Bug: v8:12018 Change-Id: I9db3053d7d62ffce6d3c95d62adce71ae40dae62 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3172770Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/main@{#77031}
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- 23 Sep, 2021 1 commit
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Ng Zhi An authored
Similar optimization to the one for x64 at https://crrev.com/c/3154347. There is a change to VisitLoad, which should call GetEffectiveAddressMemoryOperand on the value node. This allows us to match the input operands to the value (S128Load64Zero node), while emitting instructions for the node (F64x2PromoteLowF32x4 node). Bug: v8:12189 Change-Id: I30ca09b567c12a43f7f3bbb4811bae53006bedaf Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3171979Reviewed-by:
Georg Neis <neis@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#77019}
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- 17 Sep, 2021 1 commit
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Ng Zhi An authored
Optimize i64x2mul when AVX is supported to elide some moves. Bug: v8:11589 Change-Id: Ide0bba502a35cbb632e3fc311c9697c5f54f9d82 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3163280Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76889}
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- 14 Sep, 2021 1 commit
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Ng Zhi An authored
Change them to use macro-assembler functions so they will emit AVX if supported. Rename the opcodes since they are no longer SSE specific. Bug: v8:12148 Change-Id: Iaa2aa54dde9f9b41304394f98b8ed18dbb65715b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3158679Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76825}
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- 13 Sep, 2021 2 commits
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Ng Zhi An authored
We move the implementation in Liftoff (which is the most general and handles AVX/SSE and also register aliasing) into shared-macro-assembler. Also consolidate SSE/AVX for ia32. No functionality change is expected. Bug: v8:11589 Bug: v8:11217 Change-Id: I64cc71791f04332dd3505055f4672430c2daf5ac Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131373Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76805}
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Ng Zhi An authored
Move this from macro-assembler-x64 to shared-macro-assembler, and use this implementation for ia32 (TurboFan and Liftoff). Bug: v8:11589 Change-Id: If851560c8db1293924ca024725609c399c553a4a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3124099 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#76803}
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- 10 Sep, 2021 2 commits
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Ng Zhi An authored
This is a follow-up on https://crrev.com/c/3131374 to support more instructions, float32 sqrt, cmp, round, float64 cmp. Rename the opcodes since they are no longer SSE specific. Bug: v8:12148 Change-Id: Ie5f74bc1b4510092cbfbcb7e420ef82cb1c39a14 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3154983Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76777}
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Ng Zhi An authored
In https://crrev.com/c/3131374 we switched some instructions to use macro-assembler functions which can handle AVX and SSE. However for Cvtsi2ss and Cvtsi2sd, the behavior subtly changed. The old behavior directly called cvtsi2ss/cvtsi2sd in the code-generator. The new behavior used the macro-assembler functions, which xor the dst operand. This led to more instructions and larger code size in some benchmarks. The xor is supposed to help reduce dependence chain length (see comments on Cvtsi2ss), but doesn't seem to have helped in this benchmark. So, partially revert the changes, and rename all affected IA32 opcodes back to SSE. Bug: chromium:1248509 Change-Id: Ie700e2980fe9ed083c1160bda3a28f64e1e43041 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3154349 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Adam Klein <adamk@chromium.org> Cr-Commit-Position: refs/heads/main@{#76775}
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- 09 Sep, 2021 1 commit
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Ng Zhi An authored
By delegating to the macro-assembler, emit AVX instructions for some float opcodes (float sqrt, round, conversions to and from int, extract/insert/load word). Since they now support AVX, we rename the instruction ops to remove the SSE prefix, changing it to be IA32. Bug: v8:12148 Change-Id: Ib488f03928756e7d85ab78e6cb28eb869e0641f9 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131374Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76755}
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- 08 Sep, 2021 3 commits
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Ng Zhi An authored
No functionality change is expected. Bug: v8:11217 Change-Id: I131d52794e4de24ec838cc23f15828edbfc656ff Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131372Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76738}
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Ng Zhi An authored
Merge the SSE and AVX opcodes for I16x8Eq and I16x8GtS. We delegate to the macro-assembler to check for AVX. No functionality change is expected. Bug: v8:11217 Change-Id: I873b261d6f949bfc6755fe4c0e09b964a02c3684 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3131371 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Adam Klein <adamk@chromium.org> Cr-Commit-Position: refs/heads/main@{#76737}
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Ng Zhi An authored
Combine the SSE and AVX versions, delegate to the macro-assembler functions to check for AVX support. Change Pand, Por, Pxor to generate the *ps version of the instruction when AVX is not supported. The *ps versions are 1 byte shorter, and have no performance difference on SSE-only processors. Bug: v8:11589 Bug: v8:11217 Change-Id: I9d51054359dcc909efcbb2c3d3bb63d399cd6721 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3124101Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76733}
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- 07 Sep, 2021 2 commits
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Ng Zhi An authored
Bug: v8:12094 Change-Id: Ibefce881cbfcd4445485197a4a2615bdf0599ada Fixed: v8:12094 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3123638 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#76706}
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Patrick Thier authored
The receiver is now always included in the actual argument count and the formal parameter count. kDontAdaptArgumentsSentinel is changed from UINT16_MAX to 0 to preserve the maximum allowed declared parameters. The build flag activating the changes is not set for any architecture yet. Bug: v8:11112 Change-Id: I48a4969137949a1b4d1f47545209bb22b64e7e05 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3140608 Commit-Queue: Patrick Thier <pthier@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Leszek Swirski <leszeks@chromium.org> Reviewed-by:
Omer Katz <omerkatz@chromium.org> Reviewed-by:
Nico Hartmann <nicohartmann@chromium.org> Reviewed-by:
Thibaud Michaud <thibaudm@chromium.org> Cr-Commit-Position: refs/heads/main@{#76699}
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- 24 Aug, 2021 3 commits
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Ng Zhi An authored
These instructions are all single instruction lowering, so it's a matter of changing the code-gen to call macro-assembler functions (that will do the AVX check). Bug: v8:11217 Change-Id: I472eacf74933f4b504299fc85f63fd07062db320 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3114602Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76476}
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Ng Zhi An authored
We also set these operations to explicitly require Register for the second operand (rhs) even if AVX is supported. Although AVX instructions support unaligned operands, there is potentially a performance hit, especially on older hardware. This matches the x64 instruction selector as well. Bug: v8:11217 Change-Id: Iae11ec23cc607842a034250028f7667fb2fcb0d0 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3114601Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76474}
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Ng Zhi An authored
This removes 4 arch opcodes. Bug: v8:11217 Change-Id: Idff04fb205c7d7d1577ce123cc2160d678dfe39a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3114599Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76473}
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- 23 Aug, 2021 1 commit
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Ng Zhi An authored
This removes 8 arch opcodes. Bug: v8:11217 Change-Id: I2c7a73b032ba5fa21f9843ebb4325e226a22550a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3114590Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76442}
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- 19 Aug, 2021 4 commits
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Shu-yu Guo authored
This is a reland of faf2208a Changes since revert: - Fix arm64 codegen for full pointer mode Original change's description: > [compiler] Support acq/rel accesses and atomic accesses on tagged > > This CL adds an AtomicMemoryOrder parameter to the various atomic load > and store operators. Currently only acquire release (kAcqRel) and > sequentially consistent (kSeqCst) orders are supported. > > Additionally, atomic loads and stores are extended to work with tagged > values. > > This CL is a pre-requisite for supporting atomic accesses in Torque, > which is in turn a pre-requisite for prototyping shared strings. > > Bug: v8:11995 > Change-Id: Ic77d2640e2dc7e5581b1211a054c93210c219355 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3101765 > Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Shu-yu Guo <syg@chromium.org> > Cr-Commit-Position: refs/heads/main@{#76393} Bug: v8:11995 Change-Id: I23577486334fec6b08fb3a2f5be1f6e5e16db11b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3107220Reviewed-by:
Zhi An Ng <zhin@chromium.org> Reviewed-by:
Adam Klein <adamk@chromium.org> Commit-Queue: Shu-yu Guo <syg@chromium.org> Cr-Commit-Position: refs/heads/main@{#76399}
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Nico Hartmann authored
This reverts commit faf2208a. Reason for revert: https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Linux64%20-%20arm64%20-%20sim%20-%20pointer%20compression/10870/overview Original change's description: > [compiler] Support acq/rel accesses and atomic accesses on tagged > > This CL adds an AtomicMemoryOrder parameter to the various atomic load > and store operators. Currently only acquire release (kAcqRel) and > sequentially consistent (kSeqCst) orders are supported. > > Additionally, atomic loads and stores are extended to work with tagged > values. > > This CL is a pre-requisite for supporting atomic accesses in Torque, > which is in turn a pre-requisite for prototyping shared strings. > > Bug: v8:11995 > Change-Id: Ic77d2640e2dc7e5581b1211a054c93210c219355 > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3101765 > Reviewed-by: Nico Hartmann <nicohartmann@chromium.org> > Reviewed-by: Zhi An Ng <zhin@chromium.org> > Commit-Queue: Shu-yu Guo <syg@chromium.org> > Cr-Commit-Position: refs/heads/main@{#76393} Bug: v8:11995 Change-Id: Id9936672f9e96c509b1cdf866de1ac5303996945 No-Presubmit: true No-Tree-Checks: true No-Try: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3107229Reviewed-by:
Nico Hartmann <nicohartmann@chromium.org> Commit-Queue: Nico Hartmann <nicohartmann@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Cr-Commit-Position: refs/heads/main@{#76394}
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Shu-yu Guo authored
This CL adds an AtomicMemoryOrder parameter to the various atomic load and store operators. Currently only acquire release (kAcqRel) and sequentially consistent (kSeqCst) orders are supported. Additionally, atomic loads and stores are extended to work with tagged values. This CL is a pre-requisite for supporting atomic accesses in Torque, which is in turn a pre-requisite for prototyping shared strings. Bug: v8:11995 Change-Id: Ic77d2640e2dc7e5581b1211a054c93210c219355 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3101765Reviewed-by:
Nico Hartmann <nicohartmann@chromium.org> Reviewed-by:
Zhi An Ng <zhin@chromium.org> Commit-Queue: Shu-yu Guo <syg@chromium.org> Cr-Commit-Position: refs/heads/main@{#76393}
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Ng Zhi An authored
Move optimized implementation (accounts for AVX2) into shared-macro-assembler, and use it everywhere. Drive-by fix in liftoff-assembler-ia32.h to use Movss and Movsd macro-assembler functions to that they emit AVX when supported. Bug: v8:11589 Change-Id: Ibc4f2709d323d5b835bcac175a32b422d47d3355 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3095008 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#76372}
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- 17 Aug, 2021 2 commits
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Ng Zhi An authored
Change i16x8.splat to use Punpcklqdq instead of Pshufd as the final step to move low 32 bits to all lanes. Move this implementation to shared-macro-assembler and use it everywhere. Bug: v8:11589,v8:12090 Change-Id: I968b1dca5a262e4e67875caea18c5c09828cb33a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3092558 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/main@{#76353}
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Ng Zhi An authored
The optimal implementation is in TurboFan x64 codegen, move it into shared-macro-assembler, and have TurboFan ia32 and Liftoff use it. The optimal implementation accounts for AVX2 support. We add a couple of AVX2 instruction to ia32 in sse-instr.h, not all of them are used, but follow-up patches will use them, so we add support (including diassembly and test) in this change. Drive-by clean up to test-disasm-x64.cc to merge 2 AVX2 test sections. Bug: v8:11589 Change-Id: I1c8d7deb0f8bb70b29e7a680e5dbcfb09ca5505b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3092555Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/main@{#76352}
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- 16 Aug, 2021 1 commit
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Nico Weber authored
Bug: chromium:1066980 Change-Id: I03a6b5253043bfb9825a1a64a1d9b060958e5a98 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3094866 Auto-Submit: Nico Weber <thakis@chromium.org> Commit-Queue: Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#76293}
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- 13 Aug, 2021 2 commits
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Shu-yu Guo authored
To free up some ArchOpcode bits (especially for arm64), encode all atomic opcodes that are duplicated between 32bit and 64bit widths with a single opcode and encode the width in another field. Bug: v8:12093 Change-Id: Ide05e8f0b2aa877ea776851e47df60dd410deae2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3093257Reviewed-by:
Zhi An Ng <zhin@chromium.org> Commit-Queue: Shu-yu Guo <syg@chromium.org> Cr-Commit-Position: refs/heads/master@{#76289}
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Ng Zhi An authored
We no longer require dst == src (output = input[0]) in all cases, only when AVX is not supported. This can help remove an extra move when AVX is supported. Also in many cases (when input[0] is an immediate), we require less temporary registers. Bug: v8:11589 Change-Id: I0d272df12de54f55b4c7a0a330c38ccaca82e927 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3092553Reviewed-by:
Clemens Backes <clemensb@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#76286}
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- 12 Aug, 2021 5 commits
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Ng Zhi An authored
Use punpcklqdq/punpckhqdq instead of pshufd. Bug: v8:12075 Change-Id: I0260136d3727fde7bae4359df015d2b0090e8b29 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3092554Reviewed-by:
Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Zhi An Ng <zhin@chromium.org> Cr-Commit-Position: refs/heads/master@{#76272}
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Ng Zhi An authored
Move the implementation into shared macro-assembler. TurboFan and Liftoff for both ia32 and x64 can now share the implementation. No functionality change expected. Bug: v8:11589 Change-Id: Ia1f680ba139fca627e82e7dc0a9cf1c833e483cf Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3088513 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#76268}
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Ng Zhi An authored
Move the implementation into shared macro-assembler. TurboFan and Liftoff for both ia32 and x64 can now share the implementation. No functionality change expected. Bug: v8:11589 Change-Id: I8d3567ef6e4a430fe8e007e44d5d55cf8e8a6a7a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3088273 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#76264}
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Ross McIlroy authored
These are no longer enabled, so remove the code mitigation logic from the codebase. BUG=chromium:1003890 Change-Id: I536bb1732e8463281c21da446bbba8f47ede8ebe Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3045704 Commit-Queue: Ross McIlroy <rmcilroy@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#76256}
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Ng Zhi An authored
Move I32x4SConvertF32x4 into shared implementation, and takes care of both AVX and no-AVX implementation. Instruction selector still requires dst == src to save a move in codegen. Bug: v8:11589 Change-Id: Ie982682b3002192ab27700bf73f8c1e66aeba492 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3086732 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#76243}
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- 10 Aug, 2021 1 commit
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Ng Zhi An authored
Use logical shifts to emulate arithmetic shift, by first adding a bias to make all signed values unsigned, then subtracting the shifted bias. Details are in code comments for SharedTurboAssembler::I64x2ShrS. Also refactor ia32 (which was already using this algorithm) to use the shared macro-assembler function. And convert Liftoff's implementation as well. Bug: v8:12058 Change-Id: Ia1fd5fe5a9a0b7a7f31c426d4112256c8bf7021b Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3083291 Commit-Queue: Zhi An Ng <zhin@chromium.org> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#76209}
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