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    • plind44@gmail.com's avatar
      MIPS: Avoid flushing the icache unnecessarily when updating target addresses in code. · eabf0602
      plind44@gmail.com authored 
      Port r21380 (ef20a0a)

Original commit message:
This CL updates RelocInfo update operations and set_target_address_at to enable
skipping of the icache flush if it going to be batched up later.
Code::CopyFrom and Code::Relocate are modified to avoid individual icache
flushes since the whole code area will be flushed after the reloc info is
updated.

These changes reduce a regression when enabling the OOL constant pool on Arm,
since this change can cause MovT/MovW instructions for relocatable targets
if the constant pool is full.

Scores for Mandreel latency on a Nexus 5:
- OOL CP disabled: 3533
- OOL CP enabled, without this CL: 1825
- OOL CP enabled, with change: 3015

BUG=
R=plind44@gmail.com

Review URL: https://codereview.chromium.org/296723003

Patch from Balazs Kilvady <kilvadyb@homejinni.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21390 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      eabf0602
  23. 16 May, 2014 1 commit
    • yangguo@chromium.org's avatar
      Decouple CpuFeatures from serializer state. · fe243379
      yangguo@chromium.org authored 
      Traditionally, we cross compile a snapshot iff the serializer is enabled.
This will change in the future.

Changes:
 - CpuFeatures probing is done once per process, depending on whether we
   cross compile.
 - CpuFeatures are consolidated into the platform-independent assembler.h
   as much as possible.
 - FLAG_enable_<feature> will only be checked at probing time (already the
   case for ARM).
 - The serializer state is cached by the MacroAssembler.
 - PlatformFeatureScope is no longer necessary.
 - CPUFeature enum values no longer map to CPUID bit fields.

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/285233010

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21347 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      fe243379
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    • plind44@gmail.com's avatar
      MIPS: Add big-endian support for MIPS. · 5a016958
      plind44@gmail.com authored 
      Important notices:

- The snapshot cannot be created for big-endian target in cross-compilation
  environment on little-endian host using simulator.

- In order to have i18n support working on big-endian target, the icudt46b.dat and
  icudt46b_dat.S files should be generated and upstreamed to ICU repo.

- The mjsunit 'nans' test is endian dependent, it is skipped for mips target.

- The zlib and Mandreel from Octane 2.0 benchmark are endian dependent due to
  use of typed arrays.

TEST=
BUG=
R=jkummerow@chromium.org, plind44@gmail.com

Review URL: https://codereview.chromium.org/228943009

Patch from Dusan Milosavljevic <Dusan.Milosavljevic@rt-rk.com>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20778 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
      5a016958
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