MIPS: [turbofan] Add backend support for float32.

Port r24179 (41b81c2)

LOG=n
BUG=v8:3589
TEST=compiler-unittests,cctest
R=paul.lind@imgtec.com

Review URL: https://codereview.chromium.org/601783002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24192 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

src/mips/assembler-mips-inl.h

@@ -99,6 +99,11 @@ int DoubleRegister::NumAllocatableRegisters() {
 }
 
 
+int DoubleRegister::NumAllocatableAliasedRegisters() {
+  return NumAllocatableRegisters();
+}
+
+
 int FPURegister::ToAllocationIndex(FPURegister reg) {
   DCHECK(reg.code() % 2 == 0);
   DCHECK(reg.code() / 2 < kMaxNumAllocatableRegisters);

src/mips/assembler-mips.h

@@ -222,6 +222,10 @@ struct FPURegister {
 
   inline static int NumRegisters();
   inline static int NumAllocatableRegisters();
+
+  // TODO(turbofan): Proper support for float32.
+  inline static int NumAllocatableAliasedRegisters();
+
   inline static int ToAllocationIndex(FPURegister reg);
   static const char* AllocationIndexToString(int index);
 

src/mips64/assembler-mips64-inl.h

@@ -99,6 +99,11 @@ int DoubleRegister::NumAllocatableRegisters() {
 }
 
 
+int DoubleRegister::NumAllocatableAliasedRegisters() {
+  return NumAllocatableRegisters();
+}
+
+
 int FPURegister::ToAllocationIndex(FPURegister reg) {
   DCHECK(reg.code() % 2 == 0);
   DCHECK(reg.code() / 2 < kMaxNumAllocatableRegisters);

src/mips64/assembler-mips64.h

@@ -211,6 +211,10 @@ struct FPURegister {
 
   inline static int NumRegisters();
   inline static int NumAllocatableRegisters();
+
+  // TODO(turbofan): Proper support for float32.
+  inline static int NumAllocatableAliasedRegisters();
+
   inline static int ToAllocationIndex(FPURegister reg);
   static const char* AllocationIndexToString(int index);