- 01 Feb, 2017 1 commit
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bbudge authored
- Adds vqadd.s/u, vqsub.s/u for all integer lane sizes. - Refactors disassembler and simulator, using switches instead of long if-else chains. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2649323012 Cr-Commit-Position: refs/heads/master@{#42865}
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- 23 Jan, 2017 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2629223005 Cr-Commit-Position: refs/heads/master@{#42610}
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- 16 Jan, 2017 1 commit
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bbudge authored
- Adds vmin, vmax for FP and integer vectors, both signed and unsigned. - Regularizes switching logic in disasm and simulator for special codes 4 and 6. - Factors vrecpe, vrsqrte, vrecps, vrsqrts into helper fns. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2623993006 Cr-Commit-Position: refs/heads/master@{#42385}
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- 12 Jan, 2017 2 commits
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2620343002 Cr-Commit-Position: refs/heads/master@{#42273}
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bbudge authored
- Floating point, signed, and unsigned. - Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2602293002 Cr-Commit-Position: refs/heads/master@{#42262}
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- 10 Jan, 2017 1 commit
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bbudge authored
- Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2600153002 Cr-Commit-Position: refs/heads/master@{#42176}
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- 06 Jan, 2017 1 commit
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martyn.capewell authored
Remove unused size variable from disassembler. BUG= Review-Url: https://codereview.chromium.org/2615633004 Cr-Commit-Position: refs/heads/master@{#42107}
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- 20 Dec, 2016 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2593443002 Cr-Commit-Position: refs/heads/master@{#41859}
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- 17 Dec, 2016 1 commit
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bbudge authored
- Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
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- 15 Dec, 2016 1 commit
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bbudge authored
- Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
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- 25 Nov, 2016 1 commit
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bbudge authored
- Adds vmov, vswp instructions for QwNeonRegisters. - Refactors existing vswp implementation, moves non-Neon adaption to MacroAssembler. - Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2523933002 Cr-Commit-Position: refs/heads/master@{#41291}
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- 08 Sep, 2016 1 commit
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martyn.capewell authored
Reason for revert: Breaks g++ build. Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} BUG= Review-Url: https://codereview.chromium.org/2314043002 Cr-Commit-Position: refs/heads/master@{#39264}
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- 06 Sep, 2016 4 commits
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machenbach authored
Revert of [turbofan] ARM: Implement vswp and use in gap resolver (patchset #2 id:20001 of https://codereview.chromium.org/2313803003/ ) Reason for revert: Breaks arm compilation: https://build.chromium.org/p/client.v8.ports/builders/V8%20Arm%20-%20builder/builds/3549 Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} TBR=bmeurer@chromium.org,epertoso@chromium.org,martyn.capewell@arm.com # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG= Review-Url: https://codereview.chromium.org/2314003003 Cr-Commit-Position: refs/heads/master@{#39210}
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martyn.capewell authored
Use vswp to switch double-precision registers in the gap resolver, with fall back temp register-based code if NEON is not available. BUG= Review-Url: https://codereview.chromium.org/2313803003 Cr-Commit-Position: refs/heads/master@{#39209}
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jacob.bramley authored
ARMv6 has the same basic barriers as ARMv7+, but they are accessed using the CP15 coprocessor. This patch allows the assembler to select the appropriate instruction. This also fixes TurboFan's atomic loads and stores for ARMv6 platforms. BUG= Review-Url: https://codereview.chromium.org/2318553002 Cr-Commit-Position: refs/heads/master@{#39203}
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jacob.bramley authored
These are ARMv8 instructions that will be used in a follow-up patch. BUG= Review-Url: https://codereview.chromium.org/2273003002 Cr-Commit-Position: refs/heads/master@{#39193}
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- 30 Aug, 2016 1 commit
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jacob.bramley authored
This replaces the target-selection options (such as "--enable-vfp3") with a simpler, absolute "--arm-arch" option. This eliminates inferences and avoids surprising behaviour in impossible situations (such as "--enable-vfp3 --no-enable-armv7"). The available options are: --arm-arch=armv6 ARMv6 + VFPv2 --arm-arch=armv7 ARMv7 + VFPv3-D32 + NEON --arm-arch=armv7+sudiv ARMv7 + VFPv4-D32 + NEON + SUDIV --arm-arch=armv8 ARMv8 (+ all of the above) For now, the default setting is "armv8", which results in behaviour very similar to the existing defaults. BUG=v8:5077 Review-Url: https://codereview.chromium.org/2223433002 Cr-Commit-Position: refs/heads/master@{#39004}
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- 26 Jul, 2016 1 commit
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yangguo authored
Doing so in a -pie build would make the snapshot non-deterministic. R=bmeurer@chromium.org BUG=v8:5233 Review-Url: https://codereview.chromium.org/2178093003 Cr-Commit-Position: refs/heads/master@{#38042}
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- 27 Jun, 2016 1 commit
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bbudge authored
Replaces ArchDefault method with Crankshaft and Turbofan getters. Eliminates IsAllocated method on Register, FloatRegister, DoubleRegister. Eliminates ToString method too. Changes call sites to access appropriate arch default RegisterConfiguration. LOG=N BUG= Review-Url: https://codereview.chromium.org/2092413002 Cr-Commit-Position: refs/heads/master@{#37297}
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- 24 May, 2016 1 commit
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machenbach authored
For cross-compiler-compatibility and standards compliance %p requires a void*, rather than any pointer type. BUG=chromium:474921 Review-Url: https://codereview.chromium.org/2001073002 Cr-Commit-Position: refs/heads/master@{#36466}
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- 19 May, 2016 1 commit
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binji authored
R=jarin@chromium.org,bmeurer@chromium.org Review-Url: https://codereview.chromium.org/1993033002 Cr-Commit-Position: refs/heads/master@{#36380}
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- 06 Apr, 2016 1 commit
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jacob.bramley authored
BUG= Review URL: https://codereview.chromium.org/1862993002 Cr-Commit-Position: refs/heads/master@{#35292}
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- 14 Mar, 2016 1 commit
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martyn.capewell authored
Reduce the amount of code generated for OutOfLineLoadFloat* by computing sqrt(-1) rather than move the NaN as an immediate. Add support for single precision floating point immediate moves to enable this. BUG= Review URL: https://codereview.chromium.org/1758003003 Cr-Commit-Position: refs/heads/master@{#34746}
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- 10 Mar, 2016 1 commit
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jacob.bramley authored
Only CPSR_f is supported, and then only for the flags that we actually simulate (NZCV). This isn't currently used, but will be useful for some tests. BUG= Review URL: https://codereview.chromium.org/1776933003 Cr-Commit-Position: refs/heads/master@{#34662}
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- 17 Feb, 2016 1 commit
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binji authored
This is not currently implemented in the simulator, just the assembler and disassembler. BUG=v8:4614 LOG=y Review URL: https://codereview.chromium.org/1699173003 Cr-Commit-Position: refs/heads/master@{#34093}
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- 16 Feb, 2016 1 commit
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rodolph.perfetta authored
Let me know if this is not the right approach Review URL: https://codereview.chromium.org/1698483002 Cr-Commit-Position: refs/heads/master@{#34028}
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- 25 Nov, 2015 1 commit
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ahaas authored
The Float32RoundTruncate operator rounds float32 numbers towards zero. The operator is currently implemented on x64, ia32, arm, and arm64. Additionally I added support for the float32 vrintz, vrintn, and vrinta instructions to the arm simulator. R=titzer@chromium.org Review URL: https://codereview.chromium.org/1468303005 Cr-Commit-Position: refs/heads/master@{#32301}
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- 02 Oct, 2015 3 commits
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf Cr-Commit-Position: refs/heads/master@{#31075} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31087}
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danno authored
Revert of Reland: Remove register index/code indirection (patchset #20 id:380001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on MIPS Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} > > Committed: https://crrev.com/7b7a8205d9a00c678fb7a6e032a55fecbc1509cf > Cr-Commit-Position: refs/heads/master@{#31075} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1380863004 Cr-Commit-Position: refs/heads/master@{#31083}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 Cr-Commit-Position: refs/heads/master@{#30913} Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#31075}
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- 24 Sep, 2015 2 commits
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danno authored
Revert of Remove register index/code indirection (patchset #17 id:320001 of https://codereview.chromium.org/1287383003/ ) Reason for revert: Failures on greedy RegAlloc, Fuzzer Original issue's description: > Remove register index/code indirection > > Previous to this patch, both the lithium and TurboFan register > allocators tracked allocated registers by "indices", rather than > the register codes used elsewhere in the runtime. This patch > ensures that codes are used everywhere, and in the process cleans > up a bunch of redundant code and adds more structure to how the > set of allocatable registers is defined. > > Some highlights of changes: > > * TurboFan's RegisterConfiguration class moved to V8's top level > so that it can be shared with Crankshaft. > * Various "ToAllocationIndex" and related methods removed. > * Code that can be easily shared between Register classes on > different platforms is now shared. > * The list of allocatable registers on each platform is declared > as a list rather than implicitly via the register index <-> > code mapping. > > Committed: https://crrev.com/80bc6f6e11f79524e3f1ad05579583adfd5f18b2 > Cr-Commit-Position: refs/heads/master@{#30913} TBR=akos.palfi@imgtec.com,bmeurer@chromium.org,jarin@chromium.org,paul.lind@imgtec.com,titzer@chromium.org NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true Review URL: https://codereview.chromium.org/1365073002 Cr-Commit-Position: refs/heads/master@{#30914}
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danno authored
Previous to this patch, both the lithium and TurboFan register allocators tracked allocated registers by "indices", rather than the register codes used elsewhere in the runtime. This patch ensures that codes are used everywhere, and in the process cleans up a bunch of redundant code and adds more structure to how the set of allocatable registers is defined. Some highlights of changes: * TurboFan's RegisterConfiguration class moved to V8's top level so that it can be shared with Crankshaft. * Various "ToAllocationIndex" and related methods removed. * Code that can be easily shared between Register classes on different platforms is now shared. * The list of allocatable registers on each platform is declared as a list rather than implicitly via the register index <-> code mapping. Review URL: https://codereview.chromium.org/1287383003 Cr-Commit-Position: refs/heads/master@{#30913}
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- 17 Aug, 2015 1 commit
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mstarzinger authored
R=yangguo@chromium.org Review URL: https://codereview.chromium.org/1299563003 Cr-Commit-Position: refs/heads/master@{#30187}
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- 01 Jun, 2015 1 commit
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erikcorry authored
When compiling on a laptop I like to concatenate the small test files. This makes a big difference to compile times. These changes make that easier. R=ulan@chromium.org BUG= Review URL: https://codereview.chromium.org/1163803002 Cr-Commit-Position: refs/heads/master@{#28742}
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- 30 Mar, 2015 1 commit
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bmeurer authored
This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
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- 04 Mar, 2015 1 commit
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thakis authored
Shouldn't make a difference in practice, but it's a bit more readable and it gets the case of a 0 shift correct without undefined behavior. BUG=463436 LOG=N Review URL: https://codereview.chromium.org/975283002 Cr-Commit-Position: refs/heads/master@{#26975}
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- 10 Nov, 2014 1 commit
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bmeurer@chromium.org authored
TEST=cctest,msjunit/asm,unittests R=jarin@chromium.org Review URL: https://codereview.chromium.org/709123005 Cr-Commit-Position: refs/heads/master@{#25228} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 30 Oct, 2014 1 commit
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sigurds@chromium.org authored
R=rodolph.perfetta@gmail.com, ulan@chromium.org, bmeurer@chromium.org, rodolph.perfetta@arm.com Review URL: https://codereview.chromium.org/682643002 Cr-Commit-Position: refs/heads/master@{#25013} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25013 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 17 Oct, 2014 1 commit
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bmeurer@chromium.org authored
R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/659663005 Patch from Ben Noordhuis <ben@strongloop.com>. git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24672 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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- 14 Oct, 2014 1 commit
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bmeurer@chromium.org authored
Apparently SMMLS r, b, c, a computes r = ((a << 32) - b * c) >> 32 while the documentation is kinda misleading and states that it should compute r = a - ((b * c) >> 32) The actual behavior is kinda useless, so we drop the instruction again. TEST=cctest,unittests TBR=dcarney@chromium.org Review URL: https://codereview.chromium.org/654653004 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24577 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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