1. 18 Oct, 2017 1 commit
  2. 25 Sep, 2017 1 commit
  3. 06 Sep, 2017 2 commits
  4. 24 Aug, 2017 1 commit
  5. 17 Aug, 2017 1 commit
  6. 20 Jul, 2017 1 commit
  7. 17 Jul, 2017 1 commit
  8. 13 Jul, 2017 1 commit
  9. 12 Jul, 2017 1 commit
  10. 03 Jul, 2017 1 commit
  11. 28 Jun, 2017 1 commit
  12. 27 Jun, 2017 1 commit
  13. 20 Jun, 2017 1 commit
  14. 08 Jun, 2017 1 commit
    • bbudge's avatar
      [WASM] Eliminate SIMD boolean vector types. · 381f7da0
      bbudge authored
      - Eliminates b1x4, b1x8, and b1x16 as distinct WASM types.
      - All vector comparisons return v128 type.
      - Eliminates b1xN and, or, xor, not.
      - Selects take a v128 mask vector and are now bit-wise.
      - Adds a new test for Select, where mask is non-canonical (not 0's and -1's).
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2919203002
      Cr-Commit-Position: refs/heads/master@{#45795}
      381f7da0
  15. 05 Jun, 2017 1 commit
  16. 01 Jun, 2017 1 commit
  17. 24 May, 2017 1 commit
    • dusan.simicic's avatar
      MIPS[64]: Support for some SIMD operations (7) · a8421ddd
      dusan.simicic authored
      Add support for I8x16Add, I8x16AddSaturateS, I8x16Sub, I8x16SubSaturateS,
      I8x16Mul, I8x16MaxS, I8x16MinS, I8x16Eq, I8x16Ne, I8x16LtS,
      I8x16LeS, I8x16ShrU, I8x16AddSaturateU, I8x16SubSaturateU, I8x16MaxU,
      I8x16MinU, I8x16LtU, I8x16LeU, S128And, S128Or, S128Xor, S128Not for
      mips32 and mips64 architectures.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2798853003
      Cr-Commit-Position: refs/heads/master@{#45512}
      a8421ddd
  18. 21 May, 2017 1 commit
    • gdeepti's avatar
      [wasm] Swap the implementation of SIMD compare ops using Gt/Ge insteas of Lt/Le · eeefc74a
      gdeepti authored
      Currently SIMD integer comparison ops are implemented using Lt/Le, this is
      sub-optimal on Intel, because all compares are done using pcmpgt(d/w/b) that
      clobber the destination register, and will need additional instructions to
      when using Lt/Le as the base implementation. This CL proposes moving to Gt/Ge
      as the underlying implementation as this will only require swapping operands
      on MIPS and is consistent with x86/ARM instructions.
      
      BUG=v8:6020
      
      R=bbudge@chromium.org, bmeurer@chromium.org, bradnelson@chromium.org
      
      Review-Url: https://codereview.chromium.org/2874403002
      Cr-Commit-Position: refs/heads/master@{#45440}
      eeefc74a
  19. 16 May, 2017 1 commit
  20. 15 May, 2017 1 commit
    • dusan.simicic's avatar
      MIPS[64]: Support for some SIMD operations (6) · b99a1ba0
      dusan.simicic authored
      Add support for I16x8Mul, I16x8MaxS, I16x8MinS, I16x8Eq, I16x8Ne,
      I16x8LtS, I16x8LeS, I16x8AddSaturateU, I16x8SubSaturateU, I16x8MaxU,
      I16x8MinU, I16x8LtU, I16x8LeU, I8x16Splat, I8x16ExtractLane,
      I8x16ReplaceLane, I8x16Neg, I8x16Shl, I8x16ShrS, S16x8Select,
      S8x16Select for mips32 and mips64 architectures.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2791213003
      Cr-Commit-Position: refs/heads/master@{#45312}
      b99a1ba0
  21. 09 May, 2017 2 commits
  22. 04 May, 2017 1 commit
  23. 21 Apr, 2017 1 commit
    • bbudge's avatar
      [WASM SIMD] Remove opcodes that are slow on some platforms. · dddfcfd0
      bbudge authored
      These can be synthesized from existing operations and scheduled for
      better performance than if we have to generate blocks of instructions
      that take many cycles to complete.
      - Remove F32x4RecipRefine, F32x4RecipSqrtRefine. Clients are better off
        synthesizing these from splats, multiplies and adds.
      - Remove F32x4Div, F32x4Sqrt, F32x4MinNum, F32x4MaxNum. Clients are
        better off synthesizing these or using the reciprocal approximations,
        possibly with a refinement step.
      
      LOG=N
      BUG=v8:6020
      
      Review-Url: https://codereview.chromium.org/2827143002
      Cr-Commit-Position: refs/heads/master@{#44784}
      dddfcfd0
  24. 12 Apr, 2017 1 commit
  25. 11 Apr, 2017 2 commits
  26. 04 Apr, 2017 1 commit
  27. 03 Apr, 2017 1 commit
  28. 31 Mar, 2017 1 commit
  29. 16 Mar, 2017 1 commit
  30. 13 Mar, 2017 1 commit
  31. 09 Mar, 2017 1 commit
  32. 07 Mar, 2017 1 commit
  33. 24 Feb, 2017 1 commit
  34. 21 Feb, 2017 1 commit
    • bbudge's avatar
      [V8] Implement SIMD Boolean vector types to allow mask registers. · 9fe0b4c7
      bbudge authored
      - Adds new machine types SimdBool4/8/16 for the different boolean vector types.
      - Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
      - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
        opcodes from the Boolean types. These are unlikely to be well supported natively,
        and can be synthesized using Select.
      - Changes the signature of Relational opcodes to return boolean vectors.
      - Changes the signature of Select opcodes to take boolean vectors.
      - Updates the ARM implementation of Relational and Select opcodes.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2700813002
      Cr-Commit-Position: refs/heads/master@{#43348}
      9fe0b4c7
  35. 10 Feb, 2017 1 commit
  36. 09 Feb, 2017 2 commits