Commit 5b8f1f84 authored by ivica.bogosavljevic's avatar ivica.bogosavljevic Committed by Commit bot

MIPS64: Fix corner case for Word64And(Word64Shr(val,0)) reduction

In instruction selector, in the reduction of Word64And(Word64Shr(val,0),
0xFFF...) to EXT instruction, the case where shift value is 0 and mask is
0xFFFFFFFFFFFFFFFF was not supported. We now generate NOP for this case
since no bit extraction is necessary.
We implement the same behavior for MIPS32 even though there are no tests
that are failing.

TEST=cctest/test-run-machops/Regression5951
BUG=

Review-Url: https://codereview.chromium.org/2718433002
Cr-Commit-Position: refs/heads/master@{#43408}
parent 208014ab
......@@ -405,9 +405,13 @@ void InstructionSelector::VisitWord32And(Node* node) {
// zeros.
if (lsb + mask_width > 32) mask_width = 32 - lsb;
Emit(kMipsExt, g.DefineAsRegister(node),
g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
g.TempImmediate(mask_width));
if (lsb == 0 && mask_width == 32) {
Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(mleft.left().node()));
} else {
Emit(kMipsExt, g.DefineAsRegister(node),
g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
g.TempImmediate(mask_width));
}
return;
}
// Other cases fall through to the normal And operation.
......
......@@ -562,9 +562,13 @@ void InstructionSelector::VisitWord64And(Node* node) {
// zeros.
if (lsb + mask_width > 64) mask_width = 64 - lsb;
Emit(kMips64Dext, g.DefineAsRegister(node),
g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
g.TempImmediate(static_cast<int32_t>(mask_width)));
if (lsb == 0 && mask_width == 64) {
Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(mleft.left().node()));
} else {
Emit(kMips64Dext, g.DefineAsRegister(node),
g.UseRegister(mleft.left().node()), g.TempImmediate(lsb),
g.TempImmediate(static_cast<int32_t>(mask_width)));
}
return;
}
// Other cases fall through to the normal And operation.
......
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