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  1. 14 Sep, 2017 1 commit
  3. 07 Sep, 2017 1 commit
  5. 06 Sep, 2017 1 commit
    • Clemens Hammacher's avatar
      [assembler] Make Register et al. real classes · 9e995e12
      Clemens Hammacher authored 
      Up to now, each architecture defined all Register types as structs,
with lots of redundancy. An often found comment noted that they cannot
be classes due to initialization order problems. As these problems are
gone with C++11 constexpr constants, I now tried making Registers
classes again.
All register types now inherit from RegisterBase, which provides a
default set of methods and named constructors (like ::from_code,
code(), bit(), is_valid(), ...).
This design allows to guarantee an interesting property: Each register
is either valid, or it's the no_reg register. There are no other
invalid registers. This is guaranteed statically by the constexpr
constructor, and dynamically by ::from_code.

I decided to disallow the default constructor completely, so instead of
"Register reg;" you now need "Register reg = no_reg;". This makes
explicit how the Register is initialized.

I did this change to the x64, ia32, arm, arm64, mips and mips64 ports.
Overall, code got much more compact and more safe. In theory, it should
also increase performance (since the is_valid() check is simpler), but
this is probably not measurable.

R=mstarzinger@chromium.org

Change-Id: I5ccfa4050daf4e146a557970e9d37fd3d2788d4a
Reviewed-on: https://chromium-review.googlesource.com/650927Reviewed-by: 's avatarJakob Gruber <jgruber@chromium.org>
Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
Reviewed-by: 's avatarIgor Sheludko <ishell@chromium.org>
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#47847}
      9e995e12
  7. 17 Aug, 2017 1 commit
  9. 16 Aug, 2017 1 commit
  11. 14 Aug, 2017 1 commit
  13. 11 Aug, 2017 1 commit
  15. 28 Jul, 2017 1 commit
    • sreten.kovacevic's avatar
      MIPS[64]: Port `[arm] Introduce UseScratchRegisterScope` · 3eb4de34
      sreten.kovacevic authored 
      Add UseScratchRegisterScope for MIPS and use it instead of using at register directly.

Original commit message:
`Introduce a stripped down version of UseScratchRegisterScope for ARM and use it
inside the assembler and macro-assembler. At the exception of the Call
instructions, we now use this scope instead of using the ip register
directly. This is inspired from how the ARM64 backend works.

In general, the benefit of doing this is we can catch cases where ip is being
used both by the caller and by the assembler. But more specifically, TurboFan
reserves r9 as an extra scratch register because ip can already be used by the
assembler. With this utility, we can isolate the cases in the code generator
which need an extra register and potentially fix them, allowing us to give r9
back to the register allocator.

This patch uncovered places in the assembler where we were using ip
unconditionally when we could have re-used the destination register instead.`

Bug: 
Change-Id: I1a35c1661579882801605337abfc95f75b47f052
Reviewed-on: https://chromium-review.googlesource.com/574923
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46963}
      3eb4de34
  17. 13 Jul, 2017 1 commit
  19. 12 Jul, 2017 1 commit
  21. 11 Jul, 2017 1 commit
  23. 10 Jul, 2017 3 commits
  25. 05 Jul, 2017 1 commit
  27. 27 Jun, 2017 1 commit
    • Ilija Pavlovic's avatar
      MIPS[64]: Fix restartability issues. · 7a6d35e6
      Ilija Pavlovic authored 
      For handling restartability issues, following conditions must be
fulfilled:
- For Branch-and-link restartability: GPR 31 (ra register) must not be
used for the source register rs.
- For Jump-and-Link restartability: Register specifiers rs and rd must
not be equal.
This CL implements checking that GPR 31 is not used as source register.

TEST=
BUG=

Change-Id: I568ff9c497b4efca73f1a5353cb7520202524479
Reviewed-on: https://chromium-review.googlesource.com/549362Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46252}
      7a6d35e6
  29. 20 Jun, 2017 2 commits
  31. 01 Jun, 2017 1 commit
  33. 31 May, 2017 1 commit
    • neis's avatar
      [compiler] Delay allocation of code-embedded heap numbers. · 659e8f7b
      neis authored 
      Instead of allocating and embedding certain heap numbers into the code
during code assembly, emit dummies but record the allocation requests.
Later then, in Assembler::GetCode, allocate the heap numbers and patch
the code by replacing the dummies with the actual objects. The
RelocInfos for the embedded objects are already recorded correctly when
emitting the dummies.

R=jarin@chromium.org
BUG=v8:6048

Review-Url: https://codereview.chromium.org/2900683002
Cr-Commit-Position: refs/heads/master@{#45635}
      659e8f7b
  35. 22 May, 2017 1 commit
  37. 28 Apr, 2017 1 commit
  39. 25 Apr, 2017 1 commit
    • Miran.Karic's avatar
      MIPS: Use JIC/JIALC offset when possible · fe916cd2
      Miran.Karic authored 
      Until now JIC and JIALC compact branches were emited without using their
offset. Here we optimize their use by using offset after addition and/or
load immediate operations.

The CL also fixes a problem with deserialization that occurs when a code
object ends with an optimized LUI/AUI and JIC/JIALC instruction pair.
Deserializer processed these instruction pairs by moving to a location
immediately after it, but when this location is the end of the object it
would finish with the current object before doing relocation. This is
fixed by moving the deserializer one instruction before the location of
the instruction pair end.

BUG=

Review-Url: https://codereview.chromium.org/2542403002
Cr-Commit-Position: refs/heads/master@{#44841}
      fe916cd2
  41. 27 Mar, 2017 1 commit
  43. 21 Mar, 2017 1 commit
    • Ilija.Pavlovic's avatar
      MIPS: Move ldc1/sdc1 to macro-assembler. · 47da8de2
      Ilija.Pavlovic authored 
      For MIPS32, instructions ldc1 and sdc1 are moved into macro-assembler
and renamed as Ldc1 and Sdc1. The reason for placing them into
macro-assembler is that they emmit two or three instructions.

TEST=test/cctest/test-assembler-mips,
     test/cctest/test-code-stubs-mips,
     test/cctest/test-macro-assembler-mips
BUG=

Review-Url: https://codereview.chromium.org/2751973002
Cr-Commit-Position: refs/heads/master@{#43977}
      47da8de2
  45. 20 Mar, 2017 1 commit
  47. 17 Mar, 2017 1 commit
    • neis's avatar
      Disentangle assembler from isolate. · 94b088ca
      neis authored 
      This is a first step towards moving Turbofan code generation off the main thread.

Summary of the changes:
- AssemblerBase no longer has a pointer to the isolate. Instead, its
  constructor receives the few things that it needs from the isolate (on most
  architectures this is just the serializer_enabled flag).
- RelocInfo no longer has a pointer to the isolate. Instead, the functions
  that need it take it as an argument.  (There are currently still a few that
  implicitly access the isolate through a HeapObject.)
- The MacroAssembler now explicitly holds a pointer to the isolate (before, it
  used to get it from the Assembler).
- The jit_cookie also moved from AssemblerBase to the MacroAssemblers, since
  it's not used at all in the Assemblers.
- A few architectures implemented parts of the Assembler with the help
  of a Codepatcher that is based on MacroAssembler.  Since the Assembler no
  longer has the isolate, but the MacroAssembler still needs it, this doesn't
  work anymore.  Instead, these Assemblers now use a new PatchingAssembler.

BUG=v8:6048

Review-Url: https://codereview.chromium.org/2732273003
Cr-Commit-Position: refs/heads/master@{#43890}
      94b088ca
  49. 09 Mar, 2017 1 commit
  51. 10 Jan, 2017 1 commit
  53. 01 Dec, 2016 2 commits
  55. 15 Nov, 2016 1 commit
  57. 14 Nov, 2016 2 commits
  59. 14 Sep, 2016 1 commit
  61. 26 Aug, 2016 1 commit
  63. 19 Aug, 2016 1 commit
  65. 26 Jul, 2016 1 commit
  67. 29 Jun, 2016 2 commits