MIPS[64]: Fix memory load/store helper.

The CL introducing optimizations in memory load/store helper,
https://chromium-review.googlesource.com/c/552119/, caused several
failures on r6 builders. The problem was in Sdc1 macro instruction where
address in at register was overwritten before being used. Also in debug
mode a DCHECK was failing because an incorrect type was used.

BUG=

Change-Id: If38f9dfbbe2e72dfce05c24f7b6019060ef28334
Reviewed-on: https://chromium-review.googlesource.com/565297Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Miran Karić <Miran.Karic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46521}

src/mips/assembler-mips.cc

@@ -1995,7 +1995,7 @@ void Assembler::AdjustBaseAndOffset(MemOperand& src,
     offset_high += (offset_low < 0)
                        ? 1
                        : 0;  // Account for offset sign extension in load/store.
-    aui(at, src.rm(), offset_high);
+    aui(at, src.rm(), static_cast<uint16_t>(offset_high));
     if (two_accesses && !is_int16(static_cast<int32_t>(
                             offset_low + second_access_add_to_offset))) {
       // Avoid overflow in the 16-bit offset of the load/store instruction when

src/mips/macro-assembler-mips.cc

@@ -1335,7 +1335,7 @@ void MacroAssembler::Ldc1(FPURegister fd, const MemOperand& src) {
     DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
     DCHECK(!src.rm().is(at));
     lw(at, MemOperand(tmp.rm(), tmp.offset() + Register::kExponentOffset));
-    mthc1(at, fd);
+    Mthc1(at, fd);
   }
 }
 
@@ -1355,9 +1355,9 @@ void MacroAssembler::Sdc1(FPURegister fd, const MemOperand& src) {
     DCHECK(IsFp64Mode() || IsFpxxMode());
     // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6
     DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
-    DCHECK(!src.rm().is(at));
-    mfhc1(at, fd);
-    sw(at, MemOperand(tmp.rm(), tmp.offset() + Register::kExponentOffset));
+    DCHECK(!src.rm().is(t8));
+    Mfhc1(t8, fd);
+    sw(t8, MemOperand(tmp.rm(), tmp.offset() + Register::kExponentOffset));
   }
 }
 

src/mips64/assembler-mips64.cc

@@ -2143,15 +2143,15 @@ void Assembler::AdjustBaseAndOffset(MemOperand& src,
     src.offset_ += kMinOffsetForSimpleAdjustment;
   } else if (kArchVariant == kMips64r6) {
     // On r6 take advantage of the daui instruction, e.g.:
-    //    daui   AT, base, offset_high
-    //   [dahi   AT, 1]                       // When `offset` is close to +2GB.
-    //    lw     reg_lo, offset_low(AT)
-    //   [lw     reg_hi, (offset_low+4)(AT)]  // If misaligned 64-bit load.
+    //    daui   at, base, offset_high
+    //   [dahi   at, 1]                       // When `offset` is close to +2GB.
+    //    lw     reg_lo, offset_low(at)
+    //   [lw     reg_hi, (offset_low+4)(at)]  // If misaligned 64-bit load.
     // or when offset_low+4 overflows int16_t:
-    //    daui   AT, base, offset_high
-    //    daddiu AT, AT, 8
-    //    lw     reg_lo, (offset_low-8)(AT)
-    //    lw     reg_hi, (offset_low-4)(AT)
+    //    daui   at, base, offset_high
+    //    daddiu at, at, 8
+    //    lw     reg_lo, (offset_low-8)(at)
+    //    lw     reg_hi, (offset_low-4)(at)
     int16_t offset_low = static_cast<uint16_t>(src.offset());
     int32_t offset_low32 = offset_low;
     int16_t offset_high = static_cast<uint16_t>(src.offset() >> 16);
@@ -2162,7 +2162,7 @@ void Assembler::AdjustBaseAndOffset(MemOperand& src,
       offset_high++;
       overflow_hi16 = (offset_high == -32768);
     }
-    daui(at, src.rm(), offset_high);
+    daui(at, src.rm(), static_cast<uint16_t>(offset_high));
 
     if (overflow_hi16) {
       dahi(at, 1);