1. 23 Feb, 2017 1 commit
  2. 21 Feb, 2017 1 commit
    • bbudge's avatar
      [V8] Implement SIMD Boolean vector types to allow mask registers. · 9fe0b4c7
      bbudge authored
      - Adds new machine types SimdBool4/8/16 for the different boolean vector types.
      - Adds a kSimdMaskRegisters flag for each platform. These are all false for now.
      - Removes Create, ExtractLane, ReplaceLane, Equal, NotEqual, Swizzle and Shuffle
        opcodes from the Boolean types. These are unlikely to be well supported natively,
        and can be synthesized using Select.
      - Changes the signature of Relational opcodes to return boolean vectors.
      - Changes the signature of Select opcodes to take boolean vectors.
      - Updates the ARM implementation of Relational and Select opcodes.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2700813002
      Cr-Commit-Position: refs/heads/master@{#43348}
      9fe0b4c7
  3. 10 Feb, 2017 1 commit
  4. 09 Feb, 2017 2 commits
  5. 23 Dec, 2016 1 commit
    • ivica.bogosavljevic's avatar
      MIPS: Reland of `Fix bad RegisterConfiguration usage in InstructionSequence unit tests` · c42bbec9
      ivica.bogosavljevic authored
      Reland 0cf56232
      
      The original patch got reverted because testing RegisterConfiguration was
      overwritten by turbofan RegisterConfiguration. This caused some test cases not being
      properly tested. The new patch uses correct RegisterConfiguration.
      
      Original commit message:
      Test InstructionSequenceTest has been initialized with a testing RegisterConfiguration
      instance defined in instruction-sequence-unittest.h, whereas class ExplicitOperand which
      is being tested used RegisterConfiguration from instruction.cc. In case these two
      instances are different, the tests would fail. The issue is fixed by using the same
      instance of RegisterConfiguration both for test code and code under test.
      
      Additionally, the tests in register-allocator-unittest.cc use hardcoded values
      for register and begin failing is the hardcoded register is not available for
      allocation. Fix by forcing the use of allocatable registers only.
      
      TEST=unittests.MoveOptimizerTest.RemovesRedundantExplicit,unittests.RegisterAllocatorTest.SpillPhi
      BUG=
      
      Review-Url: https://codereview.chromium.org/2595293002
      Cr-Commit-Position: refs/heads/master@{#41938}
      c42bbec9
  6. 16 Dec, 2016 1 commit
    • mtrofin's avatar
      Revert of MIPS: Fix bad RegisterConfiguration usage in InstructionSequence... · 8e833623
      mtrofin authored
      Revert of MIPS: Fix bad RegisterConfiguration usage in InstructionSequence unit tests. (patchset #3 id:40001 of https://codereview.chromium.org/2433093002/ )
      
      Reason for revert:
      This change rendered InstructionSequenceTest::SetNumRegs ineffectual, thus
      loosening the tests that were using that API to ensure correct register
      allocation under intentionally constrained setups.
      
      For the problem stated in this CL, a solution needs to continue supporting the
      intentionally set-up test configuration.
      
      Original issue's description:
      > MIPS: Fix bad RegisterConfiguration usage in InstructionSequence unit tests.
      >
      > Test InstructionSequenceTest has been initialized with a testing RegisterConfiguration
      > instance defined in instruction-sequence-unittest.h, whereas class ExplicitOperand which
      > is being tested used RegisterConfiguration from instruction.cc. In case these two
      > instances are different, the tests would fail. The issue is fixed by using the same
      > instance of RegisterConfiguration both for test code and code under test.
      >
      > Additionally, the tests in register-allocator-unittest.cc use hardcoded values
      > for register and begin failing is the hardcoded register is not available for
      > allocation. Fix by forcing the use of allocatable registers only.
      >
      > TEST=unittests.MoveOptimizerTest.RemovesRedundantExplicit,unittests.RegisterAllocatorTest.SpillPhi
      > BUG=
      >
      > Committed: https://crrev.com/0cf56232209d4c9c669b8426680de18806f6c29a
      > Cr-Commit-Position: refs/heads/master@{#40862}
      
      TBR=dcarney@chromium.org,bmeurer@chromium.org,mstarzinger@chromium.org,vogelheim@chromium.org,titzer@chromium.org,ivica.bogosavljevic@imgtec.com
      # Not skipping CQ checks because original CL landed more than 1 days ago.
      BUG=
      
      Review-Url: https://codereview.chromium.org/2587593002
      Cr-Commit-Position: refs/heads/master@{#41777}
      8e833623
  7. 15 Dec, 2016 1 commit
    • ahaas's avatar
      [wasm] Introduce the TrapIf and TrapUnless operators to generate trap code. · 7bd61b60
      ahaas authored
      Some instructions in WebAssembly trap for some inputs, which means that the
      execution is terminated and (at least at the moment) a JavaScript exception is
      thrown. Examples for traps are out-of-bounds memory accesses, or integer
      divisions by zero.
      
      Without the TrapIf and TrapUnless operators trap check in WebAssembly introduces 5
      TurboFan nodes (branch, if_true, if_false, trap-reason constant, trap-position
      constant), in addition to the trap condition itself. Additionally, each
      WebAssembly function has four TurboFan nodes (merge, effect_phi, 2 phis) whose
      number of inputs is linear to the number of trap checks in the function.
      Especially for functions with high numbers of trap checks we observe a
      significant slowdown in compilation time, down to 0.22 MiB/s in the sqlite
      benchmark instead of the average of 3 MiB/s in other benchmarks. By introducing
      a TrapIf common operator only a single node is necessary per trap check, in
      addition to the trap condition. Also the nodes which are shared between trap
      checks (merge, effect_phi, 2 phis) would disappear. First measurements suggest a
      speedup of 30-50% on average.
      
      This CL only implements TrapIf and TrapUnless on x64. The implementation is also
      hidden behind the --wasm-trap-if flag.
      
      Please take a special look at how the source position is transfered from the
      instruction selector to the code generator, and at the context that is used for
      the runtime call.
      
      R=titzer@chromium.org
      
      Review-Url: https://codereview.chromium.org/2562393002
      Cr-Commit-Position: refs/heads/master@{#41720}
      7bd61b60
  8. 09 Nov, 2016 2 commits
    • bbudge's avatar
      [Turbofan] Reduce register allocation work when we can. · 472cb045
      bbudge authored
      - Track representations of virtual registers in InstructionSequence.
      - Skip extra aliasing work when no floats or SIMD registers are used.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2468233004
      Cr-Commit-Position: refs/heads/master@{#40870}
      472cb045
    • ivica.bogosavljevic's avatar
      MIPS: Fix bad RegisterConfiguration usage in InstructionSequence unit tests. · 0cf56232
      ivica.bogosavljevic authored
      Test InstructionSequenceTest has been initialized with a testing RegisterConfiguration
      instance defined in instruction-sequence-unittest.h, whereas class ExplicitOperand which
      is being tested used RegisterConfiguration from instruction.cc. In case these two
      instances are different, the tests would fail. The issue is fixed by using the same
      instance of RegisterConfiguration both for test code and code under test.
      
      Additionally, the tests in register-allocator-unittest.cc use hardcoded values
      for register and begin failing is the hardcoded register is not available for
      allocation. Fix by forcing the use of allocatable registers only.
      
      TEST=unittests.MoveOptimizerTest.RemovesRedundantExplicit,unittests.RegisterAllocatorTest.SpillPhi
      BUG=
      
      Review-Url: https://codereview.chromium.org/2433093002
      Cr-Commit-Position: refs/heads/master@{#40862}
      0cf56232
  9. 26 Oct, 2016 1 commit
    • bbudge's avatar
      [Turbofan] Add concept of FP register aliasing on ARM 32. · 09ab8e6a
      bbudge authored
      - Modifies RegisterConfiguration to specify complex aliasing on ARM 32.
      - Modifies RegisterAllocator to consider aliasing.
      - Modifies ParallelMove::PrepareInsertAfter to handle aliasing.
      - Modifies GapResolver to split wider register moves when interference
      with smaller moves is detected.
      - Modifies MoveOptimizer to handle aliasing.
      - Adds ARM 32 macro-assembler pseudo move instructions to handle cases where
        split moves don't correspond to actual s-registers.
      - Modifies CodeGenerator::AssembleMove and AssembleSwap to handle moves of
        different widths, and moves involving pseudo-s-registers.
      - Adds unit tests for FP operand interference checking and PrepareInsertAfter.
      - Adds more tests of FP for the move optimizer and register allocator.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2410673002
      Cr-Commit-Position: refs/heads/master@{#40597}
      09ab8e6a
  10. 11 Oct, 2016 1 commit
    • mtrofin's avatar
      [turbofan] Avoid large deopt blocks · 33629651
      mtrofin authored
      Treat allocation of splintered ranges differently, by optimizing for move
      counts (i.e. try to have less move counts), rather than optimizing for
      quality of moves (which is what normal allocation does).
      
      We can see reductions in code size in the benchmarks that measure it
      (e.g. Unity)
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2347563004
      Cr-Commit-Position: refs/heads/master@{#40178}
      33629651
  11. 19 Sep, 2016 1 commit
  12. 06 Sep, 2016 1 commit
  13. 01 Sep, 2016 1 commit
  14. 16 Aug, 2016 1 commit
  15. 29 Jul, 2016 1 commit
  16. 18 Jul, 2016 1 commit
    • bmeurer's avatar
      [turbofan] Add support for eager/soft deoptimization reasons. · db635d5b
      bmeurer authored
      So far TurboFan wasn't adding the deoptimization reasons for eager/soft
      deoptimization exits that can be used by either the DevTools profiler or
      the --trace-deopt flag. This adds basic support for deopt reasons on
      Deoptimize, DeoptimizeIf and DeoptimizeUnless nodes and threads through
      the reasons to the code generation.
      
      Also moves the DeoptReason to it's own file (to resolve include cycles)
      and drops unused reasons.
      
      R=jarin@chromium.org
      
      Review-Url: https://codereview.chromium.org/2161543002
      Cr-Commit-Position: refs/heads/master@{#37823}
      db635d5b
  17. 04 Jul, 2016 1 commit
  18. 30 Jun, 2016 1 commit
    • ahaas's avatar
      [turbofan] Don't call String::Flatten in Constant::ToHeapObject() · 5d8cfbbd
      ahaas authored
      The call to String::Flatten can cause garbage collection and in general adds
      complexity to the code generation. It also blocks the way to run code generation on worker threads.
      
      The call to String::Flatten in Constant::ToHeapObject() seems not to be necessary
      for correctness. If removing this call affects performance negatively, we can revert
      this CL.
      
      Review-Url: https://codereview.chromium.org/2107243002
      Cr-Commit-Position: refs/heads/master@{#37422}
      5d8cfbbd
  19. 29 Jun, 2016 2 commits
    • georgia.kouveli's avatar
      [arm64] Generate adds/ands. · 317dc057
      georgia.kouveli authored
      Perform the following transformation:
      
          | Before           | After               |
          |------------------+---------------------|
          | add w2, w0, w1   | adds w2, w0, w1     |
          | cmp w2, #0x0     | b.<cond'> <addr>    |
          | b.<cond> <addr>  |                     |
          |------------------+---------------------|
          | add w2, w0, w1   | adds w2, w0, w1     |
          | cmp #0x0, w2     | b.<cond'> <addr>    |
          | b.<cond> <addr>  |                     |
      
      and the same for and instructions instead of add.  When the result of the
      add/and is not used, generate cmn/tst instead. We need to take care with which
      conditions we can handle and what new condition we map them to.
      
      BUG=
      
      Review-Url: https://codereview.chromium.org/2065243005
      Cr-Commit-Position: refs/heads/master@{#37400}
      317dc057
    • bbudge's avatar
      [Turbofan] Simplify operand canonicalization on archs with simple FP aliasing. · 4b76dc85
      bbudge authored
      - Changes InstructionOperand canonicalization to map all FP operands to kFloat64 on Intel and other platforms with simple aliasing.
      - Bypass expensive interference calculations and fixed FP live range processing for platforms with simple aliasing.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2101653003
      Cr-Commit-Position: refs/heads/master@{#37388}
      4b76dc85
  20. 27 Jun, 2016 1 commit
  21. 24 Jun, 2016 2 commits
    • bbudge's avatar
      [Turbofan] Add the concept of aliasing to RegisterConfiguration. · a933b704
      bbudge authored
      - Adds the concept of FP register aliasing to RegisterConfiguration.
      - Changes RegisterAllocator to distinguish between FP representations
      when allocating.
      - Changes LinearScanAllocator to detect interference when FP register
      aliasing is combining, as on ARM.
      - Changes ARM code generation to allow all registers s0 - s31 to be
      accessed.
      - Adds unit tests for RegisterConfiguration, mostly to test aliasing
      calculations.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/2086653003
      Cr-Commit-Position: refs/heads/master@{#37251}
      a933b704
    • balazs.kilvady's avatar
      Fix '[tests] Don't test moves between different reps in test-gap-resolver.cc' · 5cda2db7
      balazs.kilvady authored
      Port fc59eb8a
      
      Original commit message:
      Moves between operands with different representations shouldn't happen,
      so don't test them. This makes it easier to modify canonicalization to
      differentiate between floating point types, which is needed to support
      floating point register aliasing for ARM and MIPS.
      
      This change also expands tests to include explicit FP moves (both register and stack slot).
      
      LOG=N
      BUG=v8:4124
      BUG=chromium:622619
      
      Review-Url: https://codereview.chromium.org/2090993002
      Cr-Commit-Position: refs/heads/master@{#37241}
      5cda2db7
  22. 15 Jun, 2016 1 commit
  23. 03 Jun, 2016 1 commit
  24. 27 May, 2016 1 commit
  25. 10 May, 2016 1 commit
    • bbudge's avatar
      [turbofan] Rename floating point register / slot methods. · 8c8600db
      bbudge authored
      Renames IsDouble* predicates to IsFP*.
      Adds specific IsFloat*, IsDouble*, and IsSimd128* predicates.
      Adds specific GetFloatRegister, GetDoubleRegister, and
      GetSimd128Register methods.
      
      This is mostly a mechanical renaming of IsDouble* to IsFP* methods.
      
      This shouldn't change code generation at all. All fp registers are still
      treated as double registers.
      
      LOG=N
      BUG=v8:4124
      
      Review-Url: https://codereview.chromium.org/1959763002
      Cr-Commit-Position: refs/heads/master@{#36146}
      8c8600db
  26. 04 May, 2016 1 commit
    • gdeepti's avatar
      Add new relocation type WASM_MEMORY_SIZE_REFERENCE, use relocatable pointers... · 117a56b7
      gdeepti authored
      Add new relocation type WASM_MEMORY_SIZE_REFERENCE, use relocatable pointers to update wasm memory size references in generated code.
       - Add new RelocInfo mode WASM_MEMORY_SIZE_REFERENCE in the assembler and add relocation information to immediates in compare instructions.
       - Use relocatable constants for MemSize/BoundsCheck in the wasm compiler
      
      R=titzer@chromium.org, yangguo@chromium.org, bradnelson@chromium.org
      
      Review-Url: https://codereview.chromium.org/1921203002
      Cr-Commit-Position: refs/heads/master@{#36044}
      117a56b7
  27. 30 Apr, 2016 1 commit
    • bmeurer's avatar
      [turbofan] Run everything after representation selection concurrently. · d1b3d426
      bmeurer authored
      Further refactor the pipeline to even run the first scheduler (part of
      the effect control linearization) concurrently. This temporarily
      disables most of the write barrier elimination, but we will get back to
      that later.
      
      Drive-by-fix: Remove the dead code from ChangeLowering, and stack
      allocate the Typer in the pipeline. Also migrate the AllocateStub to a
      native code builtin, so that we have the code object + a handle to it
      available all the time.
      
      CQ_INCLUDE_TRYBOTS=tryserver.v8:v8_linux64_tsan_rel
      R=mstarzinger@chromium.org
      BUG=v8:4969
      LOG=n
      
      Review-Url: https://codereview.chromium.org/1926023002
      Cr-Commit-Position: refs/heads/master@{#35918}
      d1b3d426
  28. 28 Apr, 2016 2 commits
  29. 23 Apr, 2016 1 commit
    • mtrofin's avatar
      [turbofan] Single entry into deferred · 5ae587cf
      mtrofin authored
      If a deferred block has multiple predecessors, they have to be
      all deferred. Otherwise, we can run into a situation where if a range
      that spills only in deferred blocks inserts its spill in the block, and
      other ranges need moves inserted by ResolveControlFlow in the predecessors,
      the register of the range spilled in the deferred block may be clobbered.
      
      To avoid that, when a deferred block has multiple predecessors, and some
      are not deferred, we add a non-deferred block to collect all such edges.
      
      This CL addresses the validator assertion failure the referenced issue, as well
      as the greedy allocator failure - which was caused by the situation described
      above.
      
      BUG=v8:4940
      LOG=n
      
      Review URL: https://codereview.chromium.org/1912093005
      
      Cr-Commit-Position: refs/heads/master@{#35742}
      5ae587cf
  30. 21 Apr, 2016 1 commit
  31. 12 Apr, 2016 2 commits
  32. 11 Apr, 2016 1 commit
  33. 01 Apr, 2016 2 commits