Improve the code used to check for encodable logical immediates, fix some corner
cases associated with moving kWMinInt into W registers, and add tests.

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/364653003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22148 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=verwaest@chromium.org

Review URL: https://codereview.chromium.org/334323003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22129 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This reverts r22120 due to build breakage of arm64.debug target.

TBR=m.m.capewell@googlemail.com

Review URL: https://codereview.chromium.org/361973002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22123 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ulan@chromium.org, bmeurer@chromium.org

BUG=

Review URL: https://codereview.chromium.org/355853003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22121 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Improve the code used to check for encodable logical immediates, fix some corner
cases associated with moving kWMinInt into W registers, and add tests.

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/341123003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22120 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=
R=ishell@chromium.org

Review URL: https://codereview.chromium.org/352173006

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22117 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

On arm, arm64 and x64 there is a different register specification between LoadIC and KeyedLoadIC.

It would be nicer if these are the same, allowing some key optimizations.

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/338963003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22103 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Also split v8-core independent methods from checks.h to base/logging.h and
merge v8checks with the rest of checks.

The CPU::FlushICache method is moved to CpuFeatures::FlushICache

RoundUp and related methods are moved to base/macros.h

Remove all layering violations from src/libplatform

BUG=none
R=jkummerow@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/358363002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22092 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This reverts commit r22082 for breaking arm64 build.

TBR=verwaest@chromium.org

Review URL: https://codereview.chromium.org/360023003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22083 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=verwaest@chromium.org

Review URL: https://codereview.chromium.org/355793003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22082 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=
R=rossberg@chromium.org

Review URL: https://codereview.chromium.org/354173002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22066 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Split SetProperty(...attributes, strictmode) into DefineProperty(...attributes) and SetProperty(...strictmode)

BUG=
R=rossberg@chromium.org

Review URL: https://codereview.chromium.org/351853005

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22064 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=bmeurer@chromium.org, ulan@chromium.org

BUG=

Review URL: https://codereview.chromium.org/357973002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22051 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/350633003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22041 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/356713003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22035 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=jkummerow@chromium.org, mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/346413004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22018 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Make CallInterfaceDescriptor work like CodeStubInterfaceDescriptor, owning it's
register and representation arrays. This also eliminates a host of TSAN warnings
for static arrays.

This CL depends on https://codereview.chromium.org/352583002 landing first
(a conceptual dependency at least).

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/350293003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22014 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Centralize a register definition in an IC that provides:
1) symbolic names for the register (like, edx == receiver)
2) defines ordering when passed on the stack

Code that implements or uses the IC should use this definition instead of "knowing" what the registers are. Or at least have the definition to validate it's assumptions.

As a side effect of avoiding runtime static initializers (enforced by tools/check-static-initializers.sh, neat), I gave ownership of the registers array to CodeStubInterfaceDescriptor. This prompted a cleanup of that struct.

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/352583002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22011 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

As a result the constant pool marker was always 0.

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/350923003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21987 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/349973007

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21957 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ulan@chromium.org, jochen@chromium.org

Review URL: https://codereview.chromium.org/268673003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21945 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This reverts commit r21939 due to a static initializer issue.

TBR=marja@chromium.org

Review URL: https://codereview.chromium.org/339663008

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21943 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

1) symbolic names for the register (like, edx == receiver)
2) can return an array of registers
3) defines ordering when passed on the stack

Code that implements or uses the IC should use this RegisterSpec instead of "knowing" what the registers are. Or at least have the RegisterSpec to validate it's assumptions.

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/340363002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21939 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

BUG=368580
LOG=Y
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/339663007

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21937 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Currently the literal pool implemetation is inherited from the arm 32-bit port
and it shares the same limitations: 4k of range and 1000 entries max. In arm64
the load literal has a 1MB range giving us more flexibility.

Immutable entries are now shared.

BUG=
R=rmcilroy@chromium.org

Review URL: https://codereview.chromium.org/338523005

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21924 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/332673002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21908 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=rossberg@chromium.org

Review URL: https://codereview.chromium.org/333013002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21894 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/338883003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=jarin@chromium.org
BUG=385002
LOG=N

Review URL: https://codereview.chromium.org/339883002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21874 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Add wrappers to utils.h instead.

BUG=none
R=jkummerow@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/328343003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21846 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=rossberg@chromium.org
BUG=http://code.google.com/p/v8/issues/detail?id=2735
LOG=N

Review URL: https://codereview.chromium.org/332663004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21820 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This avoids endless IC patching cycles between "normal" and "nonexistent" handlers when objects having and not having the property are seen alternatingly

R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/328353002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21816 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

About a 32% boost.

Before - 5:31

Richards: 84.5
DeltaBlue: 128
Crypto: 65.3
RayTrace: 203
EarleyBoyer: 149
RegExp: 23.4
Splay: 121
NavierStokes: 98.9
----
Score (version 7): 93.8

After - 4:10

Richards: 107
DeltaBlue: 175
Crypto: 93.9
RayTrace: 258
EarleyBoyer: 186
RegExp: 32.7
Splay: 165
NavierStokes: 124
----
Score (version 7): 124

R=jacob.bramley@arm.com, svenpanne@chromium.org

Committed: https://code.google.com/p/v8/source/detail?r=21448

Review URL: https://codereview.chromium.org/213943002

Patch from Fritz Koenig <frkoenig@google.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21804 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

This CL tickled an unrelated arm64 bug which was is fixed separately.

The MIPS port (originally landed 21784) is also included.

TBR=verwaest@chromium.org

Review URL: https://codereview.chromium.org/331633002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21803 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=ulan@chromium.org

Review URL: https://codereview.chromium.org/330593003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21798 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Due to lingering arm64 failures in Test262

TBR=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/332663003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21790 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=verwaest@chromium.org

Review URL: https://codereview.chromium.org/57123002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21781 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Due to arm64 and GCMole failures

TBR=mstarzinger@chromium.org

Review URL: https://codereview.chromium.org/329253003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21776 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

R=verwaest@chromium.org

Review URL: https://codereview.chromium.org/57123002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21774 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

Avoid right shifts by zero bits: On ARM it actually means shifting by
32 bits (correctness issue) and on other platforms they are useless
(performance issue). This is fix for the fix in r20544.

BUG=v8:3259
LOG=y
R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/324403003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21769 ce2b1a6d-e550-0410-aec6-3dcde31c8c00