Bug: v8:11074
Change-Id: I478f4390523ddf7cfb87dd22cef5ed331be5c875
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2558267Reviewed-by: Andreas Haas <ahaas@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71468}

Port d6c586f7

R=solanes@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com
BUG=
LOG=N

Change-Id: I73098589bc2246e389432be18b11bcf3242df308
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2488021Reviewed-by: Santiago Aboy Solanes <solanes@chromium.org>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#70681}

Change-Id: I88adc527fea64c8ab6e9b32cfd8d40927e78da9a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1874087Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#64931}

LoadReverseSimd128 and StoreReverseSimd128 are implemented
to support the above instruction selection.

Change-Id: I5dcb30ce68b3478c69668b7589e77a52e77d9388
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1846460
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#64350}

Bug: v8:9247
Change-Id: I2f999ed3a8cc0931e5092f2ac6e709b8ff3f9e42
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1630678
Commit-Queue: Yang Guo <yangguo@chromium.org>
Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#61896}